Lines Matching +full:20 +full:w
29 /* R/W SDMA System Address register 0x0 */
32 /* R/W Host DMA Buffer Boundary and Transfer Block Size Register 0x0 */
35 /* R/W Blocks count for current transfer 0x0 */
38 /* R/W Command Argument Register 0x0 */
41 /* R/W Transfer Mode Setting Register 0x0 */
51 /* R/W Command Register 0x0 */
70 /* R/W Buffer Data Register 0x0 */
86 FIELD(SDHC_PRNSTS, DAT_LVL, 20, 4);
91 /* R/W Host control Register 0x0 */
107 /* R/W Power Control Register 0x0 */
112 /* R/W Block Gap Control Register 0x0 */
117 /* R/W WakeUp Control Register 0x0 */
131 /* R/W Timeout Control Register 0x0 */
135 /* R/W Software Reset Register 0x0 */
162 /* R/W Normal Interrupt Status Enable Register 0x0 */
173 /* R/W Error Interrupt Status Enable Register 0x0 */
180 /* R/W Normal Interrupt Signal Enable Register 0x0 */
185 /* R/W Error Interrupt Signal Enable Register 0x0 */
216 FIELD(SDHC_CAPAB, ADMA1, 20, 1); /* v1 only? */
228 FIELD(SDHC_CAPAB, UHS_II, 35, 8); /* since v4.20 */
237 FIELD(SDHC_CAPAB, ADMA3, 59, 1); /* since v4.20 */
238 FIELD(SDHC_CAPAB, V18_VDD2, 60, 1); /* since v4.20 */
245 FIELD(SDHC_MAXCURR, V18_VDD2, 32, 8); /* since v4.20 */
247 /* W Force Event Auto CMD12 Error Interrupt Register 0x0000 */
249 /* W Force Event Error Interrupt Register Error Interrupt 0x0000 */
252 /* R/W ADMA Error Status Register 0x00 */
260 /* R/W ADMA System Address Register 0x00 */
299 * max host controller R/W buffers size: 512B