13e0a4e85SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */
21da177e4SLinus Torvalds /*
31da177e4SLinus Torvalds * Workbit NinjaSCSI-32Bi/UDE PCI/CardBus SCSI Host Bus Adapter driver
41da177e4SLinus Torvalds * Basic data header
51da177e4SLinus Torvalds */
61da177e4SLinus Torvalds
71da177e4SLinus Torvalds #ifndef _NSP32_H
81da177e4SLinus Torvalds #define _NSP32_H
91da177e4SLinus Torvalds
101da177e4SLinus Torvalds //#define NSP32_DEBUG 9
111da177e4SLinus Torvalds
121da177e4SLinus Torvalds /*
131da177e4SLinus Torvalds * VENDOR/DEVICE ID
141da177e4SLinus Torvalds */
151da177e4SLinus Torvalds #define PCI_VENDOR_ID_IODATA 0x10fc
161da177e4SLinus Torvalds #define PCI_VENDOR_ID_WORKBIT 0x1145
171da177e4SLinus Torvalds
181da177e4SLinus Torvalds #define PCI_DEVICE_ID_NINJASCSI_32BI_CBSC_II 0x0005
191da177e4SLinus Torvalds #define PCI_DEVICE_ID_NINJASCSI_32BI_KME 0xf007
201da177e4SLinus Torvalds #define PCI_DEVICE_ID_NINJASCSI_32BI_WBT 0x8007
211da177e4SLinus Torvalds #define PCI_DEVICE_ID_WORKBIT_STANDARD 0xf010
221da177e4SLinus Torvalds #define PCI_DEVICE_ID_WORKBIT_DUALEDGE 0xf011
231da177e4SLinus Torvalds #define PCI_DEVICE_ID_NINJASCSI_32BI_LOGITEC 0xf012
241da177e4SLinus Torvalds #define PCI_DEVICE_ID_NINJASCSI_32BIB_LOGITEC 0xf013
251da177e4SLinus Torvalds #define PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO 0xf015
261da177e4SLinus Torvalds #define PCI_DEVICE_ID_NINJASCSI_32UDE_MELCO_II 0x8009
271da177e4SLinus Torvalds
281da177e4SLinus Torvalds /*
291da177e4SLinus Torvalds * MODEL
301da177e4SLinus Torvalds */
311da177e4SLinus Torvalds enum {
321da177e4SLinus Torvalds MODEL_IODATA = 0,
331da177e4SLinus Torvalds MODEL_KME = 1,
341da177e4SLinus Torvalds MODEL_WORKBIT = 2,
351da177e4SLinus Torvalds MODEL_LOGITEC = 3,
361da177e4SLinus Torvalds MODEL_PCI_WORKBIT = 4,
371da177e4SLinus Torvalds MODEL_PCI_LOGITEC = 5,
381da177e4SLinus Torvalds MODEL_PCI_MELCO = 6,
391da177e4SLinus Torvalds };
401da177e4SLinus Torvalds
411da177e4SLinus Torvalds static char * nsp32_model[] = {
421da177e4SLinus Torvalds "I-O DATA CBSC-II CardBus card",
431da177e4SLinus Torvalds "KME SCSI CardBus card",
441da177e4SLinus Torvalds "Workbit duo SCSI CardBus card",
451da177e4SLinus Torvalds "Logitec CardBus card with external ROM",
461da177e4SLinus Torvalds "Workbit / I-O DATA PCI card",
471da177e4SLinus Torvalds "Logitec PCI card with external ROM",
481da177e4SLinus Torvalds "Melco CardBus/PCI card with external ROM",
491da177e4SLinus Torvalds };
501da177e4SLinus Torvalds
511da177e4SLinus Torvalds
521da177e4SLinus Torvalds /*
531da177e4SLinus Torvalds * SCSI Generic Definitions
541da177e4SLinus Torvalds */
551da177e4SLinus Torvalds #define EXTENDED_SDTR_LEN 0x03
561da177e4SLinus Torvalds
571da177e4SLinus Torvalds /* Little Endian */
581da177e4SLinus Torvalds typedef u32 u32_le;
591da177e4SLinus Torvalds typedef u16 u16_le;
601da177e4SLinus Torvalds
611da177e4SLinus Torvalds /*
621da177e4SLinus Torvalds * BASIC Definitions
631da177e4SLinus Torvalds */
641da177e4SLinus Torvalds #ifndef TRUE
651da177e4SLinus Torvalds # define TRUE 1
661da177e4SLinus Torvalds #endif
671da177e4SLinus Torvalds #ifndef FALSE
681da177e4SLinus Torvalds # define FALSE 0
691da177e4SLinus Torvalds #endif
701da177e4SLinus Torvalds #define ASSERT 1
711da177e4SLinus Torvalds #define NEGATE 0
721da177e4SLinus Torvalds
731da177e4SLinus Torvalds
741da177e4SLinus Torvalds /*******************/
751da177e4SLinus Torvalds /* normal register */
761da177e4SLinus Torvalds /*******************/
771da177e4SLinus Torvalds /*
781da177e4SLinus Torvalds * Don't access below register with Double Word:
791da177e4SLinus Torvalds * +00, +04, +08, +0c, +64, +80, +84, +88, +90, +c4, +c8, +cc, +d0.
801da177e4SLinus Torvalds */
811da177e4SLinus Torvalds #define IRQ_CONTROL 0x00 /* BASE+00, W, W */
821da177e4SLinus Torvalds #define IRQ_STATUS 0x00 /* BASE+00, W, R */
831da177e4SLinus Torvalds # define IRQSTATUS_LATCHED_MSG BIT(0)
841da177e4SLinus Torvalds # define IRQSTATUS_LATCHED_IO BIT(1)
851da177e4SLinus Torvalds # define IRQSTATUS_LATCHED_CD BIT(2)
861da177e4SLinus Torvalds # define IRQSTATUS_LATCHED_BUS_FREE BIT(3)
871da177e4SLinus Torvalds # define IRQSTATUS_RESELECT_OCCUER BIT(4)
881da177e4SLinus Torvalds # define IRQSTATUS_PHASE_CHANGE_IRQ BIT(5)
891da177e4SLinus Torvalds # define IRQSTATUS_SCSIRESET_IRQ BIT(6)
901da177e4SLinus Torvalds # define IRQSTATUS_TIMER_IRQ BIT(7)
911da177e4SLinus Torvalds # define IRQSTATUS_FIFO_SHLD_IRQ BIT(8)
921da177e4SLinus Torvalds # define IRQSTATUS_PCI_IRQ BIT(9)
931da177e4SLinus Torvalds # define IRQSTATUS_BMCNTERR_IRQ BIT(10)
941da177e4SLinus Torvalds # define IRQSTATUS_AUTOSCSI_IRQ BIT(11)
951da177e4SLinus Torvalds # define PCI_IRQ_MASK BIT(12)
961da177e4SLinus Torvalds # define TIMER_IRQ_MASK BIT(13)
971da177e4SLinus Torvalds # define FIFO_IRQ_MASK BIT(14)
981da177e4SLinus Torvalds # define SCSI_IRQ_MASK BIT(15)
991da177e4SLinus Torvalds # define IRQ_CONTROL_ALL_IRQ_MASK (PCI_IRQ_MASK | \
1001da177e4SLinus Torvalds TIMER_IRQ_MASK | \
1011da177e4SLinus Torvalds FIFO_IRQ_MASK | \
1021da177e4SLinus Torvalds SCSI_IRQ_MASK )
1031da177e4SLinus Torvalds # define IRQSTATUS_ANY_IRQ (IRQSTATUS_RESELECT_OCCUER | \
1041da177e4SLinus Torvalds IRQSTATUS_PHASE_CHANGE_IRQ | \
1051da177e4SLinus Torvalds IRQSTATUS_SCSIRESET_IRQ | \
1061da177e4SLinus Torvalds IRQSTATUS_TIMER_IRQ | \
1071da177e4SLinus Torvalds IRQSTATUS_FIFO_SHLD_IRQ | \
1081da177e4SLinus Torvalds IRQSTATUS_PCI_IRQ | \
1091da177e4SLinus Torvalds IRQSTATUS_BMCNTERR_IRQ | \
1101da177e4SLinus Torvalds IRQSTATUS_AUTOSCSI_IRQ )
1111da177e4SLinus Torvalds
1121da177e4SLinus Torvalds #define TRANSFER_CONTROL 0x02 /* BASE+02, W, W */
1131da177e4SLinus Torvalds #define TRANSFER_STATUS 0x02 /* BASE+02, W, R */
1141da177e4SLinus Torvalds # define CB_MMIO_MODE BIT(0)
1151da177e4SLinus Torvalds # define CB_IO_MODE BIT(1)
1161da177e4SLinus Torvalds # define BM_TEST BIT(2)
1171da177e4SLinus Torvalds # define BM_TEST_DIR BIT(3)
1181da177e4SLinus Torvalds # define DUAL_EDGE_ENABLE BIT(4)
1191da177e4SLinus Torvalds # define NO_TRANSFER_TO_HOST BIT(5)
1201da177e4SLinus Torvalds # define TRANSFER_GO BIT(7)
1211da177e4SLinus Torvalds # define BLIEND_MODE BIT(8)
1221da177e4SLinus Torvalds # define BM_START BIT(9)
1231da177e4SLinus Torvalds # define ADVANCED_BM_WRITE BIT(10)
1241da177e4SLinus Torvalds # define BM_SINGLE_MODE BIT(11)
1251da177e4SLinus Torvalds # define FIFO_TRUE_FULL BIT(12)
1261da177e4SLinus Torvalds # define FIFO_TRUE_EMPTY BIT(13)
1271da177e4SLinus Torvalds # define ALL_COUNTER_CLR BIT(14)
1281da177e4SLinus Torvalds # define FIFOTEST BIT(15)
1291da177e4SLinus Torvalds
1301da177e4SLinus Torvalds #define INDEX_REG 0x04 /* BASE+04, Byte(R/W), Word(R) */
1311da177e4SLinus Torvalds
1321da177e4SLinus Torvalds #define TIMER_SET 0x06 /* BASE+06, W, R/W */
1331da177e4SLinus Torvalds # define TIMER_CNT_MASK (0xff)
1341da177e4SLinus Torvalds # define TIMER_STOP BIT(8)
1351da177e4SLinus Torvalds
1361da177e4SLinus Torvalds #define DATA_REG_LOW 0x08 /* BASE+08, LowW, R/W */
1371da177e4SLinus Torvalds #define DATA_REG_HI 0x0a /* BASE+0a, Hi-W, R/W */
1381da177e4SLinus Torvalds
1391da177e4SLinus Torvalds #define FIFO_REST_CNT 0x0c /* BASE+0c, W, R/W */
1401da177e4SLinus Torvalds # define FIFO_REST_MASK 0x1ff
1411da177e4SLinus Torvalds # define FIFO_EMPTY_SHLD_FLAG BIT(14)
1421da177e4SLinus Torvalds # define FIFO_FULL_SHLD_FLAG BIT(15)
1431da177e4SLinus Torvalds
1441da177e4SLinus Torvalds #define SREQ_SMPL_RATE 0x0f /* BASE+0f, B, R/W */
1451da177e4SLinus Torvalds # define SREQSMPLRATE_RATE0 BIT(0)
1461da177e4SLinus Torvalds # define SREQSMPLRATE_RATE1 BIT(1)
1471da177e4SLinus Torvalds # define SAMPLING_ENABLE BIT(2)
1481da177e4SLinus Torvalds # define SMPL_40M (0) /* 40MHz: 0-100ns/period */
1491da177e4SLinus Torvalds # define SMPL_20M (SREQSMPLRATE_RATE0) /* 20MHz: 100-200ns/period */
1501da177e4SLinus Torvalds # define SMPL_10M (SREQSMPLRATE_RATE1) /* 10Mhz: 200- ns/period */
1511da177e4SLinus Torvalds
1521da177e4SLinus Torvalds #define SCSI_BUS_CONTROL 0x10 /* BASE+10, B, R/W */
1531da177e4SLinus Torvalds # define BUSCTL_SEL BIT(0)
1541da177e4SLinus Torvalds # define BUSCTL_RST BIT(1)
1551da177e4SLinus Torvalds # define BUSCTL_DATAOUT_ENB BIT(2)
1561da177e4SLinus Torvalds # define BUSCTL_ATN BIT(3)
1571da177e4SLinus Torvalds # define BUSCTL_ACK BIT(4)
1581da177e4SLinus Torvalds # define BUSCTL_BSY BIT(5)
1591da177e4SLinus Torvalds # define AUTODIRECTION BIT(6)
1601da177e4SLinus Torvalds # define ACKENB BIT(7)
1611da177e4SLinus Torvalds
1621da177e4SLinus Torvalds #define CLR_COUNTER 0x12 /* BASE+12, B, W */
1631da177e4SLinus Torvalds # define ACK_COUNTER_CLR BIT(0)
1641da177e4SLinus Torvalds # define SREQ_COUNTER_CLR BIT(1)
1651da177e4SLinus Torvalds # define FIFO_HOST_POINTER_CLR BIT(2)
1661da177e4SLinus Torvalds # define FIFO_REST_COUNT_CLR BIT(3)
1671da177e4SLinus Torvalds # define BM_COUNTER_CLR BIT(4)
1681da177e4SLinus Torvalds # define SAVED_ACK_CLR BIT(5)
1691da177e4SLinus Torvalds # define CLRCOUNTER_ALLMASK (ACK_COUNTER_CLR | \
1701da177e4SLinus Torvalds SREQ_COUNTER_CLR | \
1711da177e4SLinus Torvalds FIFO_HOST_POINTER_CLR | \
1721da177e4SLinus Torvalds FIFO_REST_COUNT_CLR | \
1731da177e4SLinus Torvalds BM_COUNTER_CLR | \
1741da177e4SLinus Torvalds SAVED_ACK_CLR )
1751da177e4SLinus Torvalds
1761da177e4SLinus Torvalds #define SCSI_BUS_MONITOR 0x12 /* BASE+12, B, R */
1771da177e4SLinus Torvalds # define BUSMON_MSG BIT(0)
1781da177e4SLinus Torvalds # define BUSMON_IO BIT(1)
1791da177e4SLinus Torvalds # define BUSMON_CD BIT(2)
1801da177e4SLinus Torvalds # define BUSMON_BSY BIT(3)
1811da177e4SLinus Torvalds # define BUSMON_ACK BIT(4)
1821da177e4SLinus Torvalds # define BUSMON_REQ BIT(5)
1831da177e4SLinus Torvalds # define BUSMON_SEL BIT(6)
1841da177e4SLinus Torvalds # define BUSMON_ATN BIT(7)
1851da177e4SLinus Torvalds
1861da177e4SLinus Torvalds #define COMMAND_DATA 0x14 /* BASE+14, B, R/W */
1871da177e4SLinus Torvalds
1881da177e4SLinus Torvalds #define PARITY_CONTROL 0x16 /* BASE+16, B, W */
1891da177e4SLinus Torvalds # define PARITY_CHECK_ENABLE BIT(0)
1901da177e4SLinus Torvalds # define PARITY_ERROR_CLEAR BIT(1)
1911da177e4SLinus Torvalds #define PARITY_STATUS 0x16 /* BASE+16, B, R */
1921da177e4SLinus Torvalds //# define PARITY_CHECK_ENABLE BIT(0)
1931da177e4SLinus Torvalds # define PARITY_ERROR_NORMAL BIT(1)
1941da177e4SLinus Torvalds # define PARITY_ERROR_LSB BIT(1)
1951da177e4SLinus Torvalds # define PARITY_ERROR_MSB BIT(2)
1961da177e4SLinus Torvalds
1971da177e4SLinus Torvalds #define RESELECT_ID 0x18 /* BASE+18, B, R */
1981da177e4SLinus Torvalds
1991da177e4SLinus Torvalds #define COMMAND_CONTROL 0x18 /* BASE+18, W, W */
2001da177e4SLinus Torvalds # define CLEAR_CDB_FIFO_POINTER BIT(0)
2011da177e4SLinus Torvalds # define AUTO_COMMAND_PHASE BIT(1)
2021da177e4SLinus Torvalds # define AUTOSCSI_START BIT(2)
2031da177e4SLinus Torvalds # define AUTOSCSI_RESTART BIT(3)
2041da177e4SLinus Torvalds # define AUTO_PARAMETER BIT(4)
2051da177e4SLinus Torvalds # define AUTO_ATN BIT(5)
2061da177e4SLinus Torvalds # define AUTO_MSGIN_00_OR_04 BIT(6)
2071da177e4SLinus Torvalds # define AUTO_MSGIN_02 BIT(7)
2081da177e4SLinus Torvalds # define AUTO_MSGIN_03 BIT(8)
2091da177e4SLinus Torvalds
2101da177e4SLinus Torvalds #define SET_ARBIT 0x1a /* BASE+1a, B, W */
2111da177e4SLinus Torvalds # define ARBIT_GO BIT(0)
2121da177e4SLinus Torvalds # define ARBIT_CLEAR BIT(1)
2131da177e4SLinus Torvalds
2141da177e4SLinus Torvalds #define ARBIT_STATUS 0x1a /* BASE+1a, B, R */
2151da177e4SLinus Torvalds //# define ARBIT_GO BIT(0)
2161da177e4SLinus Torvalds # define ARBIT_WIN BIT(1)
2171da177e4SLinus Torvalds # define ARBIT_FAIL BIT(2)
2181da177e4SLinus Torvalds # define AUTO_PARAMETER_VALID BIT(3)
2191da177e4SLinus Torvalds # define SGT_VALID BIT(4)
2201da177e4SLinus Torvalds
2211da177e4SLinus Torvalds #define SYNC_REG 0x1c /* BASE+1c, B, R/W */
2221da177e4SLinus Torvalds
2231da177e4SLinus Torvalds #define ACK_WIDTH 0x1d /* BASE+1d, B, R/W */
2241da177e4SLinus Torvalds
2251da177e4SLinus Torvalds #define SCSI_DATA_WITH_ACK 0x20 /* BASE+20, B, R/W */
2261da177e4SLinus Torvalds #define SCSI_OUT_LATCH_TARGET_ID 0x22 /* BASE+22, B, W */
2271da177e4SLinus Torvalds #define SCSI_DATA_IN 0x22 /* BASE+22, B, R */
2281da177e4SLinus Torvalds
2291da177e4SLinus Torvalds #define SCAM_CONTROL 0x24 /* BASE+24, B, W */
2301da177e4SLinus Torvalds #define SCAM_STATUS 0x24 /* BASE+24, B, R */
2311da177e4SLinus Torvalds # define SCAM_MSG BIT(0)
2321da177e4SLinus Torvalds # define SCAM_IO BIT(1)
2331da177e4SLinus Torvalds # define SCAM_CD BIT(2)
2341da177e4SLinus Torvalds # define SCAM_BSY BIT(3)
2351da177e4SLinus Torvalds # define SCAM_SEL BIT(4)
2361da177e4SLinus Torvalds # define SCAM_XFEROK BIT(5)
2371da177e4SLinus Torvalds
2381da177e4SLinus Torvalds #define SCAM_DATA 0x26 /* BASE+26, B, R/W */
2391da177e4SLinus Torvalds # define SD0 BIT(0)
2401da177e4SLinus Torvalds # define SD1 BIT(1)
2411da177e4SLinus Torvalds # define SD2 BIT(2)
2421da177e4SLinus Torvalds # define SD3 BIT(3)
2431da177e4SLinus Torvalds # define SD4 BIT(4)
2441da177e4SLinus Torvalds # define SD5 BIT(5)
2451da177e4SLinus Torvalds # define SD6 BIT(6)
2461da177e4SLinus Torvalds # define SD7 BIT(7)
2471da177e4SLinus Torvalds
2481da177e4SLinus Torvalds #define SACK_CNT 0x28 /* BASE+28, DW, R/W */
2491da177e4SLinus Torvalds #define SREQ_CNT 0x2c /* BASE+2c, DW, R/W */
2501da177e4SLinus Torvalds
2511da177e4SLinus Torvalds #define FIFO_DATA_LOW 0x30 /* BASE+30, B/W/DW, R/W */
2521da177e4SLinus Torvalds #define FIFO_DATA_HIGH 0x32 /* BASE+32, B/W, R/W */
2531da177e4SLinus Torvalds #define BM_START_ADR 0x34 /* BASE+34, DW, R/W */
2541da177e4SLinus Torvalds
2551da177e4SLinus Torvalds #define BM_CNT 0x38 /* BASE+38, DW, R/W */
2561da177e4SLinus Torvalds # define BM_COUNT_MASK 0x0001ffffUL
2571da177e4SLinus Torvalds # define SGTEND BIT(31) /* Last SGT marker */
2581da177e4SLinus Torvalds
2591da177e4SLinus Torvalds #define SGT_ADR 0x3c /* BASE+3c, DW, R/W */
2601da177e4SLinus Torvalds #define WAIT_REG 0x40 /* Bi only */
2611da177e4SLinus Torvalds
2621da177e4SLinus Torvalds #define SCSI_EXECUTE_PHASE 0x40 /* BASE+40, W, R */
2631da177e4SLinus Torvalds # define COMMAND_PHASE BIT(0)
2641da177e4SLinus Torvalds # define DATA_IN_PHASE BIT(1)
2651da177e4SLinus Torvalds # define DATA_OUT_PHASE BIT(2)
2661da177e4SLinus Torvalds # define MSGOUT_PHASE BIT(3)
2671da177e4SLinus Torvalds # define STATUS_PHASE BIT(4)
2681da177e4SLinus Torvalds # define ILLEGAL_PHASE BIT(5)
2691da177e4SLinus Torvalds # define BUS_FREE_OCCUER BIT(6)
2701da177e4SLinus Torvalds # define MSG_IN_OCCUER BIT(7)
2711da177e4SLinus Torvalds # define MSG_OUT_OCCUER BIT(8)
2721da177e4SLinus Torvalds # define SELECTION_TIMEOUT BIT(9)
2731da177e4SLinus Torvalds # define MSGIN_00_VALID BIT(10)
2741da177e4SLinus Torvalds # define MSGIN_02_VALID BIT(11)
2751da177e4SLinus Torvalds # define MSGIN_03_VALID BIT(12)
2761da177e4SLinus Torvalds # define MSGIN_04_VALID BIT(13)
2771da177e4SLinus Torvalds # define AUTOSCSI_BUSY BIT(15)
2781da177e4SLinus Torvalds
2791da177e4SLinus Torvalds #define SCSI_CSB_IN 0x42 /* BASE+42, B, R */
2801da177e4SLinus Torvalds
2811da177e4SLinus Torvalds #define SCSI_MSG_OUT 0x44 /* BASE+44, DW, R/W */
2821da177e4SLinus Torvalds # define MSGOUT_COUNT_MASK (BIT(0)|BIT(1))
2831da177e4SLinus Torvalds # define MV_VALID BIT(7)
2841da177e4SLinus Torvalds
2851da177e4SLinus Torvalds #define SEL_TIME_OUT 0x48 /* BASE+48, W, R/W */
2861da177e4SLinus Torvalds #define SAVED_SACK_CNT 0x4c /* BASE+4c, DW, R */
2871da177e4SLinus Torvalds
2881da177e4SLinus Torvalds #define HTOSDATADELAY 0x50 /* BASE+50, B, R/W */
2891da177e4SLinus Torvalds #define STOHDATADELAY 0x54 /* BASE+54, B, R/W */
2901da177e4SLinus Torvalds #define ACKSUMCHECKRD 0x58 /* BASE+58, W, R */
2911da177e4SLinus Torvalds #define REQSUMCHECKRD 0x5c /* BASE+5c, W, R */
2921da177e4SLinus Torvalds
2931da177e4SLinus Torvalds
2941da177e4SLinus Torvalds /********************/
2951da177e4SLinus Torvalds /* indexed register */
2961da177e4SLinus Torvalds /********************/
2971da177e4SLinus Torvalds
2981da177e4SLinus Torvalds #define CLOCK_DIV 0x00 /* BASE+08, IDX+00, B, R/W */
2991da177e4SLinus Torvalds # define CLOCK_2 BIT(0) /* MCLK/2 */
3001da177e4SLinus Torvalds # define CLOCK_4 BIT(1) /* MCLK/4 */
3011da177e4SLinus Torvalds # define PCICLK BIT(7) /* PCICLK (33MHz) */
3021da177e4SLinus Torvalds
3031da177e4SLinus Torvalds #define TERM_PWR_CONTROL 0x01 /* BASE+08, IDX+01, B, R/W */
3041da177e4SLinus Torvalds # define BPWR BIT(0)
3051da177e4SLinus Torvalds # define SENSE BIT(1) /* Read Only */
3061da177e4SLinus Torvalds
3071da177e4SLinus Torvalds #define EXT_PORT_DDR 0x02 /* BASE+08, IDX+02, B, R/W */
3081da177e4SLinus Torvalds #define EXT_PORT 0x03 /* BASE+08, IDX+03, B, R/W */
3091da177e4SLinus Torvalds # define LED_ON (0)
3101da177e4SLinus Torvalds # define LED_OFF BIT(0)
3111da177e4SLinus Torvalds
3121da177e4SLinus Torvalds #define IRQ_SELECT 0x04 /* BASE+08, IDX+04, W, R/W */
3131da177e4SLinus Torvalds # define IRQSELECT_RESELECT_IRQ BIT(0)
3141da177e4SLinus Torvalds # define IRQSELECT_PHASE_CHANGE_IRQ BIT(1)
3151da177e4SLinus Torvalds # define IRQSELECT_SCSIRESET_IRQ BIT(2)
3161da177e4SLinus Torvalds # define IRQSELECT_TIMER_IRQ BIT(3)
3171da177e4SLinus Torvalds # define IRQSELECT_FIFO_SHLD_IRQ BIT(4)
3181da177e4SLinus Torvalds # define IRQSELECT_TARGET_ABORT_IRQ BIT(5)
3191da177e4SLinus Torvalds # define IRQSELECT_MASTER_ABORT_IRQ BIT(6)
3201da177e4SLinus Torvalds # define IRQSELECT_SERR_IRQ BIT(7)
3211da177e4SLinus Torvalds # define IRQSELECT_PERR_IRQ BIT(8)
3221da177e4SLinus Torvalds # define IRQSELECT_BMCNTERR_IRQ BIT(9)
3231da177e4SLinus Torvalds # define IRQSELECT_AUTO_SCSI_SEQ_IRQ BIT(10)
3241da177e4SLinus Torvalds
3251da177e4SLinus Torvalds #define OLD_SCSI_PHASE 0x05 /* BASE+08, IDX+05, B, R */
3261da177e4SLinus Torvalds # define OLD_MSG BIT(0)
3271da177e4SLinus Torvalds # define OLD_IO BIT(1)
3281da177e4SLinus Torvalds # define OLD_CD BIT(2)
3291da177e4SLinus Torvalds # define OLD_BUSY BIT(3)
3301da177e4SLinus Torvalds
3311da177e4SLinus Torvalds #define FIFO_FULL_SHLD_COUNT 0x06 /* BASE+08, IDX+06, B, R/W */
3321da177e4SLinus Torvalds #define FIFO_EMPTY_SHLD_COUNT 0x07 /* BASE+08, IDX+07, B, R/W */
3331da177e4SLinus Torvalds
3341da177e4SLinus Torvalds #define EXP_ROM_CONTROL 0x08 /* BASE+08, IDX+08, B, R/W */ /* external ROM control */
3351da177e4SLinus Torvalds # define ROM_WRITE_ENB BIT(0)
3361da177e4SLinus Torvalds # define IO_ACCESS_ENB BIT(1)
3371da177e4SLinus Torvalds # define ROM_ADR_CLEAR BIT(2)
3381da177e4SLinus Torvalds
3391da177e4SLinus Torvalds #define EXP_ROM_ADR 0x09 /* BASE+08, IDX+09, W, R/W */
3401da177e4SLinus Torvalds
3411da177e4SLinus Torvalds #define EXP_ROM_DATA 0x0a /* BASE+08, IDX+0a, B, R/W */
3421da177e4SLinus Torvalds
3431da177e4SLinus Torvalds #define CHIP_MODE 0x0b /* BASE+08, IDX+0b, B, R */ /* NinjaSCSI-32Bi only */
3441da177e4SLinus Torvalds # define OEM0 BIT(1) /* OEM select */ /* 00=I-O DATA, 01=KME, 10=Workbit, 11=Ext ROM */
3451da177e4SLinus Torvalds # define OEM1 BIT(2) /* OEM select */
3461da177e4SLinus Torvalds # define OPTB BIT(3) /* KME mode select */
3471da177e4SLinus Torvalds # define OPTC BIT(4) /* KME mode select */
3481da177e4SLinus Torvalds # define OPTD BIT(5) /* KME mode select */
3491da177e4SLinus Torvalds # define OPTE BIT(6) /* KME mode select */
3501da177e4SLinus Torvalds # define OPTF BIT(7) /* Power management */
3511da177e4SLinus Torvalds
3521da177e4SLinus Torvalds #define MISC_WR 0x0c /* BASE+08, IDX+0c, W, R/W */
3531da177e4SLinus Torvalds #define MISC_RD 0x0c
3541da177e4SLinus Torvalds # define SCSI_DIRECTION_DETECTOR_SELECT BIT(0)
3551da177e4SLinus Torvalds # define SCSI2_HOST_DIRECTION_VALID BIT(1) /* Read only */
3561da177e4SLinus Torvalds # define HOST2_SCSI_DIRECTION_VALID BIT(2) /* Read only */
3571da177e4SLinus Torvalds # define DELAYED_BMSTART BIT(3)
3581da177e4SLinus Torvalds # define MASTER_TERMINATION_SELECT BIT(4)
3591da177e4SLinus Torvalds # define BMREQ_NEGATE_TIMING_SEL BIT(5)
3601da177e4SLinus Torvalds # define AUTOSEL_TIMING_SEL BIT(6)
3611da177e4SLinus Torvalds # define MISC_MABORT_MASK BIT(7)
3621da177e4SLinus Torvalds # define BMSTOP_CHANGE2_NONDATA_PHASE BIT(8)
3631da177e4SLinus Torvalds
3641da177e4SLinus Torvalds #define BM_CYCLE 0x0d /* BASE+08, IDX+0d, B, R/W */
3651da177e4SLinus Torvalds # define BM_CYCLE0 BIT(0)
3661da177e4SLinus Torvalds # define BM_CYCLE1 BIT(1)
3671da177e4SLinus Torvalds # define BM_FRAME_ASSERT_TIMING BIT(2)
3681da177e4SLinus Torvalds # define BM_IRDY_ASSERT_TIMING BIT(3)
3691da177e4SLinus Torvalds # define BM_SINGLE_BUS_MASTER BIT(4)
3701da177e4SLinus Torvalds # define MEMRD_CMD0 BIT(5)
3711da177e4SLinus Torvalds # define SGT_AUTO_PARA_MEMED_CMD BIT(6)
3721da177e4SLinus Torvalds # define MEMRD_CMD1 BIT(7)
3731da177e4SLinus Torvalds
3741da177e4SLinus Torvalds
3751da177e4SLinus Torvalds #define SREQ_EDGH 0x0e /* BASE+08, IDX+0e, B, W */
3761da177e4SLinus Torvalds # define SREQ_EDGH_SELECT BIT(0)
3771da177e4SLinus Torvalds
3781da177e4SLinus Torvalds #define UP_CNT 0x0f /* BASE+08, IDX+0f, B, W */
3791da177e4SLinus Torvalds # define REQCNT_UP BIT(0)
3801da177e4SLinus Torvalds # define ACKCNT_UP BIT(1)
3811da177e4SLinus Torvalds # define BMADR_UP BIT(4)
3821da177e4SLinus Torvalds # define BMCNT_UP BIT(5)
3831da177e4SLinus Torvalds # define SGT_CNT_UP BIT(7)
3841da177e4SLinus Torvalds
3851da177e4SLinus Torvalds #define CFG_CMD_STR 0x10 /* BASE+08, IDX+10, W, R */
3861da177e4SLinus Torvalds #define CFG_LATE_CACHE 0x11 /* BASE+08, IDX+11, W, R/W */
3871da177e4SLinus Torvalds #define CFG_BASE_ADR_1 0x12 /* BASE+08, IDX+12, W, R */
3881da177e4SLinus Torvalds #define CFG_BASE_ADR_2 0x13 /* BASE+08, IDX+13, W, R */
3891da177e4SLinus Torvalds #define CFG_INLINE 0x14 /* BASE+08, IDX+14, W, R */
3901da177e4SLinus Torvalds
3911da177e4SLinus Torvalds #define SERIAL_ROM_CTL 0x15 /* BASE+08, IDX+15, B, R */
3921da177e4SLinus Torvalds # define SCL BIT(0)
3931da177e4SLinus Torvalds # define ENA BIT(1)
3941da177e4SLinus Torvalds # define SDA BIT(2)
3951da177e4SLinus Torvalds
3961da177e4SLinus Torvalds #define FIFO_HST_POINTER 0x16 /* BASE+08, IDX+16, B, R/W */
3971da177e4SLinus Torvalds #define SREQ_DELAY 0x17 /* BASE+08, IDX+17, B, R/W */
3981da177e4SLinus Torvalds #define SACK_DELAY 0x18 /* BASE+08, IDX+18, B, R/W */
3991da177e4SLinus Torvalds #define SREQ_NOISE_CANCEL 0x19 /* BASE+08, IDX+19, B, R/W */
4001da177e4SLinus Torvalds #define SDP_NOISE_CANCEL 0x1a /* BASE+08, IDX+1a, B, R/W */
4011da177e4SLinus Torvalds #define DELAY_TEST 0x1b /* BASE+08, IDX+1b, B, R/W */
4021da177e4SLinus Torvalds #define SD0_NOISE_CANCEL 0x20 /* BASE+08, IDX+20, B, R/W */
4031da177e4SLinus Torvalds #define SD1_NOISE_CANCEL 0x21 /* BASE+08, IDX+21, B, R/W */
4041da177e4SLinus Torvalds #define SD2_NOISE_CANCEL 0x22 /* BASE+08, IDX+22, B, R/W */
4051da177e4SLinus Torvalds #define SD3_NOISE_CANCEL 0x23 /* BASE+08, IDX+23, B, R/W */
4061da177e4SLinus Torvalds #define SD4_NOISE_CANCEL 0x24 /* BASE+08, IDX+24, B, R/W */
4071da177e4SLinus Torvalds #define SD5_NOISE_CANCEL 0x25 /* BASE+08, IDX+25, B, R/W */
4081da177e4SLinus Torvalds #define SD6_NOISE_CANCEL 0x26 /* BASE+08, IDX+26, B, R/W */
4091da177e4SLinus Torvalds #define SD7_NOISE_CANCEL 0x27 /* BASE+08, IDX+27, B, R/W */
4101da177e4SLinus Torvalds
4111da177e4SLinus Torvalds
4121da177e4SLinus Torvalds /*
4131da177e4SLinus Torvalds * Useful Bus Monitor status combinations.
4141da177e4SLinus Torvalds */
4151da177e4SLinus Torvalds #define BUSMON_BUS_FREE 0
4161da177e4SLinus Torvalds #define BUSMON_COMMAND ( BUSMON_BSY | BUSMON_CD | BUSMON_REQ )
4171da177e4SLinus Torvalds #define BUSMON_MESSAGE_IN ( BUSMON_BSY | BUSMON_MSG | BUSMON_IO | BUSMON_CD | BUSMON_REQ )
4181da177e4SLinus Torvalds #define BUSMON_MESSAGE_OUT ( BUSMON_BSY | BUSMON_MSG | BUSMON_CD | BUSMON_REQ )
4191da177e4SLinus Torvalds #define BUSMON_DATA_IN ( BUSMON_BSY | BUSMON_IO | BUSMON_REQ )
4201da177e4SLinus Torvalds #define BUSMON_DATA_OUT ( BUSMON_BSY | BUSMON_REQ )
4211da177e4SLinus Torvalds #define BUSMON_STATUS ( BUSMON_BSY | BUSMON_IO | BUSMON_CD | BUSMON_REQ )
4221da177e4SLinus Torvalds #define BUSMON_RESELECT ( BUSMON_IO | BUSMON_SEL)
4231da177e4SLinus Torvalds #define BUSMON_PHASE_MASK ( BUSMON_MSG | BUSMON_IO | BUSMON_CD | BUSMON_SEL)
4241da177e4SLinus Torvalds
4251da177e4SLinus Torvalds #define BUSPHASE_COMMAND ( BUSMON_COMMAND & BUSMON_PHASE_MASK )
4261da177e4SLinus Torvalds #define BUSPHASE_MESSAGE_IN ( BUSMON_MESSAGE_IN & BUSMON_PHASE_MASK )
4271da177e4SLinus Torvalds #define BUSPHASE_MESSAGE_OUT ( BUSMON_MESSAGE_OUT & BUSMON_PHASE_MASK )
4281da177e4SLinus Torvalds #define BUSPHASE_DATA_IN ( BUSMON_DATA_IN & BUSMON_PHASE_MASK )
4291da177e4SLinus Torvalds #define BUSPHASE_DATA_OUT ( BUSMON_DATA_OUT & BUSMON_PHASE_MASK )
4301da177e4SLinus Torvalds #define BUSPHASE_STATUS ( BUSMON_STATUS & BUSMON_PHASE_MASK )
4311da177e4SLinus Torvalds #define BUSPHASE_SELECT ( BUSMON_SEL | BUSMON_IO )
4321da177e4SLinus Torvalds
4331da177e4SLinus Torvalds
4341da177e4SLinus Torvalds /************************************************************************
4351da177e4SLinus Torvalds * structure for DMA/Scatter Gather list
4361da177e4SLinus Torvalds */
4371da177e4SLinus Torvalds #define NSP32_SG_SIZE SG_ALL
4381da177e4SLinus Torvalds
4391da177e4SLinus Torvalds typedef struct _nsp32_sgtable {
4401da177e4SLinus Torvalds /* values must be little endian */
4411da177e4SLinus Torvalds u32_le addr; /* transfer address */
4421da177e4SLinus Torvalds u32_le len; /* transfer length. BIT(31) is for SGT_END mark */
4431da177e4SLinus Torvalds } __attribute__ ((packed)) nsp32_sgtable;
4441da177e4SLinus Torvalds
4451da177e4SLinus Torvalds typedef struct _nsp32_sglun {
4461da177e4SLinus Torvalds nsp32_sgtable sgt[NSP32_SG_SIZE+1]; /* SG table */
4471da177e4SLinus Torvalds } __attribute__ ((packed)) nsp32_sglun;
4481da177e4SLinus Torvalds #define NSP32_SG_TABLE_SIZE (sizeof(nsp32_sgtable) * NSP32_SG_SIZE * MAX_TARGET * MAX_LUN)
4491da177e4SLinus Torvalds
4501da177e4SLinus Torvalds /* Auto parameter mode memory map. */
4511da177e4SLinus Torvalds /* All values must be little endian. */
4521da177e4SLinus Torvalds typedef struct _nsp32_autoparam {
4531da177e4SLinus Torvalds u8 cdb[4 * 0x10]; /* SCSI Command */
4541da177e4SLinus Torvalds u32_le msgout; /* outgoing messages */
4551da177e4SLinus Torvalds u8 syncreg; /* sync register value */
4561da177e4SLinus Torvalds u8 ackwidth; /* ack width register value */
4571da177e4SLinus Torvalds u8 target_id; /* target/host device id */
4581da177e4SLinus Torvalds u8 sample_reg; /* hazard killer sampling rate */
4591da177e4SLinus Torvalds u16_le command_control; /* command control register */
4601da177e4SLinus Torvalds u16_le transfer_control; /* transfer control register */
4611da177e4SLinus Torvalds u32_le sgt_pointer; /* SG table physical address for DMA */
4621da177e4SLinus Torvalds u32_le dummy[2];
4631da177e4SLinus Torvalds } __attribute__ ((packed)) nsp32_autoparam; /* must be packed struct */
4641da177e4SLinus Torvalds
4651da177e4SLinus Torvalds /*
4661da177e4SLinus Torvalds * host data structure
4671da177e4SLinus Torvalds */
4681da177e4SLinus Torvalds /* message in/out buffer */
4691da177e4SLinus Torvalds #define MSGOUTBUF_MAX 20
4701da177e4SLinus Torvalds #define MSGINBUF_MAX 20
4711da177e4SLinus Torvalds
4721da177e4SLinus Torvalds /* flag for trans_method */
4731da177e4SLinus Torvalds #define NSP32_TRANSFER_BUSMASTER BIT(0)
4741da177e4SLinus Torvalds #define NSP32_TRANSFER_MMIO BIT(1) /* Not supported yet */
4751da177e4SLinus Torvalds #define NSP32_TRANSFER_PIO BIT(2) /* Not supported yet */
4761da177e4SLinus Torvalds
4771da177e4SLinus Torvalds
4781da177e4SLinus Torvalds /*
4791da177e4SLinus Torvalds * structure for connected LUN dynamic data
4801da177e4SLinus Torvalds *
4811da177e4SLinus Torvalds * Note: Currently tagged queuing is disabled, each nsp32_lunt holds
4821da177e4SLinus Torvalds * one SCSI command and one state.
4831da177e4SLinus Torvalds */
4841da177e4SLinus Torvalds #define DISCPRIV_OK BIT(0) /* DISCPRIV Enable mode */
4851da177e4SLinus Torvalds #define MSGIN03 BIT(1) /* Auto Msg In 03 Flag */
4861da177e4SLinus Torvalds
4871da177e4SLinus Torvalds typedef struct _nsp32_lunt {
4881da177e4SLinus Torvalds struct scsi_cmnd *SCpnt; /* Current Handling struct scsi_cmnd */
4891da177e4SLinus Torvalds unsigned long save_datp; /* Save Data Pointer - saved position from initial address */
4901da177e4SLinus Torvalds int msgin03; /* auto msg in 03 flag */
4911da177e4SLinus Torvalds unsigned int sg_num; /* Total number of SG entries */
4921da177e4SLinus Torvalds int cur_entry; /* Current SG entry number */
4931da177e4SLinus Torvalds nsp32_sglun *sglun; /* sg table per lun */
4941da177e4SLinus Torvalds dma_addr_t sglun_paddr; /* sglun physical address */
4951da177e4SLinus Torvalds } nsp32_lunt;
4961da177e4SLinus Torvalds
4971da177e4SLinus Torvalds
4981da177e4SLinus Torvalds /*
4991da177e4SLinus Torvalds * SCSI TARGET/LUN definition
5001da177e4SLinus Torvalds */
5011da177e4SLinus Torvalds #define NSP32_HOST_SCSIID 7 /* SCSI initiator is every time defined as 7 */
5021da177e4SLinus Torvalds #define MAX_TARGET 8
5031da177e4SLinus Torvalds #define MAX_LUN 8 /* XXX: In SPI3, max number of LUN is 64. */
5041da177e4SLinus Torvalds
5051da177e4SLinus Torvalds
5061da177e4SLinus Torvalds typedef struct _nsp32_sync_table {
5071da177e4SLinus Torvalds unsigned char period_num; /* period number */
5081da177e4SLinus Torvalds unsigned char ackwidth; /* ack width designated by period */
5091da177e4SLinus Torvalds unsigned char start_period; /* search range - start period */
5101da177e4SLinus Torvalds unsigned char end_period; /* search range - end period */
5111da177e4SLinus Torvalds unsigned char sample_rate; /* hazard killer parameter */
5121da177e4SLinus Torvalds } nsp32_sync_table;
5131da177e4SLinus Torvalds
5141da177e4SLinus Torvalds
5151da177e4SLinus Torvalds /*
5161da177e4SLinus Torvalds * structure for target device static data
5171da177e4SLinus Torvalds */
5181da177e4SLinus Torvalds /* flag for nsp32_target.sync_flag */
5191da177e4SLinus Torvalds #define SDTR_INITIATOR BIT(0) /* sending SDTR from initiator */
5201da177e4SLinus Torvalds #define SDTR_TARGET BIT(1) /* sending SDTR from target */
5211da177e4SLinus Torvalds #define SDTR_DONE BIT(2) /* exchanging SDTR has been processed */
5221da177e4SLinus Torvalds
5231da177e4SLinus Torvalds /* syncronous period value for nsp32_target.config_max */
5241da177e4SLinus Torvalds #define FAST5M 0x32
5251da177e4SLinus Torvalds #define FAST10M 0x19
5261da177e4SLinus Torvalds #define ULTRA20M 0x0c
5271da177e4SLinus Torvalds
5281da177e4SLinus Torvalds /* flag for nsp32_target.{sync_offset}, period */
5291da177e4SLinus Torvalds #define ASYNC_OFFSET 0 /* asynchronous transfer */
5301da177e4SLinus Torvalds #define SYNC_OFFSET 0xf /* synchronous transfer max offset */
5311da177e4SLinus Torvalds
5321da177e4SLinus Torvalds /* syncreg:
5331da177e4SLinus Torvalds bit:07 06 05 04 03 02 01 00
5341da177e4SLinus Torvalds ---PERIOD-- ---OFFSET-- */
5351da177e4SLinus Torvalds #define TO_SYNCREG(period, offset) (((period) & 0x0f) << 4 | ((offset) & 0x0f))
5361da177e4SLinus Torvalds
537*195771c5SBart Van Assche struct nsp32_cmd_priv {
538*195771c5SBart Van Assche enum sam_status status;
539*195771c5SBart Van Assche };
540*195771c5SBart Van Assche
nsp32_priv(struct scsi_cmnd * cmd)541*195771c5SBart Van Assche static inline struct nsp32_cmd_priv *nsp32_priv(struct scsi_cmnd *cmd)
542*195771c5SBart Van Assche {
543*195771c5SBart Van Assche return scsi_cmd_priv(cmd);
544*195771c5SBart Van Assche }
545*195771c5SBart Van Assche
5461da177e4SLinus Torvalds typedef struct _nsp32_target {
5471da177e4SLinus Torvalds unsigned char syncreg; /* value for SYNCREG */
5481da177e4SLinus Torvalds unsigned char ackwidth; /* value for ACKWIDTH */
5491da177e4SLinus Torvalds unsigned char period; /* sync period (0-255) */
5501da177e4SLinus Torvalds unsigned char offset; /* sync offset (0-15) */
5511da177e4SLinus Torvalds int sync_flag; /* SDTR_*, 0 */
5521da177e4SLinus Torvalds int limit_entry; /* max speed limit entry designated
5531da177e4SLinus Torvalds by EEPROM configuration */
5541da177e4SLinus Torvalds unsigned char sample_reg; /* SREQ hazard killer register */
5551da177e4SLinus Torvalds } nsp32_target;
5561da177e4SLinus Torvalds
5571da177e4SLinus Torvalds typedef struct _nsp32_hw_data {
5581da177e4SLinus Torvalds int IrqNumber;
5591da177e4SLinus Torvalds int BaseAddress;
5601da177e4SLinus Torvalds int NumAddress;
5611da177e4SLinus Torvalds void __iomem *MmioAddress;
5621da177e4SLinus Torvalds #define NSP32_MMIO_OFFSET 0x0800
5631da177e4SLinus Torvalds unsigned long MmioLength;
5641da177e4SLinus Torvalds
5651da177e4SLinus Torvalds struct scsi_cmnd *CurrentSC;
5661da177e4SLinus Torvalds
5671da177e4SLinus Torvalds struct pci_dev *Pci;
5681da177e4SLinus Torvalds const struct pci_device_id *pci_devid;
5691da177e4SLinus Torvalds struct Scsi_Host *Host;
5701da177e4SLinus Torvalds spinlock_t Lock;
5711da177e4SLinus Torvalds
5721da177e4SLinus Torvalds char info_str[100];
5731da177e4SLinus Torvalds
5741da177e4SLinus Torvalds /* allocated memory region */
5751da177e4SLinus Torvalds nsp32_sglun *sg_list; /* sglist virtuxal address */
5761da177e4SLinus Torvalds dma_addr_t sg_paddr; /* physical address of hw_sg_table */
5771da177e4SLinus Torvalds nsp32_autoparam *autoparam; /* auto parameter transfer region */
5781da177e4SLinus Torvalds dma_addr_t auto_paddr; /* physical address of autoparam */
5791da177e4SLinus Torvalds int cur_entry; /* current sgt entry */
5801da177e4SLinus Torvalds
5811da177e4SLinus Torvalds /* target/LUN */
5821da177e4SLinus Torvalds nsp32_lunt *cur_lunt; /* Current connected LUN table */
5831da177e4SLinus Torvalds nsp32_lunt lunt[MAX_TARGET][MAX_LUN]; /* All LUN table */
5841da177e4SLinus Torvalds
5851da177e4SLinus Torvalds nsp32_target *cur_target; /* Current connected SCSI ID */
5861da177e4SLinus Torvalds nsp32_target target[MAX_TARGET]; /* SCSI ID */
5871da177e4SLinus Torvalds int cur_id; /* Current connected target ID */
5881da177e4SLinus Torvalds int cur_lun; /* Current connected target LUN */
5891da177e4SLinus Torvalds
5901da177e4SLinus Torvalds /* behavior setting parameters */
5911da177e4SLinus Torvalds int trans_method; /* transfer method flag */
5921da177e4SLinus Torvalds int resettime; /* Reset time */
5931da177e4SLinus Torvalds int clock; /* clock dividing flag */
5941da177e4SLinus Torvalds nsp32_sync_table *synct; /* sync_table determined by clock */
5951da177e4SLinus Torvalds int syncnum; /* the max number of synct element */
5961da177e4SLinus Torvalds
5971da177e4SLinus Torvalds /* message buffer */
5981da177e4SLinus Torvalds unsigned char msgoutbuf[MSGOUTBUF_MAX]; /* msgout buffer */
5991da177e4SLinus Torvalds char msgout_len; /* msgoutbuf length */
6001da177e4SLinus Torvalds unsigned char msginbuf [MSGINBUF_MAX]; /* megin buffer */
6011da177e4SLinus Torvalds char msgin_len; /* msginbuf length */
6021da177e4SLinus Torvalds
6031da177e4SLinus Torvalds } nsp32_hw_data;
6041da177e4SLinus Torvalds
6051da177e4SLinus Torvalds /*
6061da177e4SLinus Torvalds * TIME definition
6071da177e4SLinus Torvalds */
6081da177e4SLinus Torvalds #define RESET_HOLD_TIME 10000 /* reset time in us (SCSI-2 says the
6091da177e4SLinus Torvalds minimum is 25us) */
6101da177e4SLinus Torvalds #define SEL_TIMEOUT_TIME 10000 /* 250ms defined in SCSI specification
6111da177e4SLinus Torvalds (25.6us/1unit) */
6121da177e4SLinus Torvalds #define ARBIT_TIMEOUT_TIME 100 /* 100us */
6131da177e4SLinus Torvalds #define REQSACK_TIMEOUT_TIME 10000 /* max wait time for REQ/SACK assertion
6141da177e4SLinus Torvalds or negation, 10000us == 10ms */
6151da177e4SLinus Torvalds
6161da177e4SLinus Torvalds #endif /* _NSP32_H */
6171da177e4SLinus Torvalds /* end */
618