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/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage_256M8_1.cfg1 # SPDX-License-Identifier: GPL-2.0+
7 # Refer doc/README.kwbimage for more details about how-to configure
10 # This configuration applies to COGE5 design (ARM-part)
11 # Two 8-Bit devices are connected on the 16-Bit bus on the same
12 # chip-select. The supported devices are
13 # MT47H256M8EB-3IT:C
14 # MT47H256M8EB-25EIT:C
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
[all …]
H A Dkwbimage_128M16_1.cfg1 # SPDX-License-Identifier: GPL-2.0+
12 # Refer doc/README.kwbimage for more details about how-to configure
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
23 # bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5])
24 # bit 19-16: 1, MPPSel4 NF_IO[6]
25 # bit 23-20: 1, MPPSel5 NF_IO[7]
26 # bit 27-24: 1, MPPSel6 SYSRST_O
27 # bit 31-28: 0, MPPSel7 GPO[7]
[all …]
H A Dkwbimage-memphis.cfg1 # SPDX-License-Identifier: GPL-2.0+
8 # Refer doc/README.kwbimage for more details about how-to configure
16 # bit 3-0: MPPSel0 2, NF_IO[2]
17 # bit 7-4: MPPSel1 2, NF_IO[3]
18 # bit 12-8: MPPSel2 2, NF_IO[4]
19 # bit 15-12: MPPSel3 2, NF_IO[5]
20 # bit 19-16: MPPSel4 1, NF_IO[6]
21 # bit 23-20: MPPSel5 1, NF_IO[7]
22 # bit 27-24: MPPSel6 1, SYSRST_O
23 # bit 31-28: MPPSel7 0, GPO[7]
[all …]
H A Dkwbimage.cfg1 # SPDX-License-Identifier: GPL-2.0+
5 # Refer doc/README.kwbimage for more details about how-to configure
13 # bit 3-0: MPPSel0 2, NF_IO[2]
14 # bit 7-4: MPPSel1 2, NF_IO[3]
15 # bit 12-8: MPPSel2 2, NF_IO[4]
16 # bit 15-12: MPPSel3 2, NF_IO[5]
17 # bit 19-16: MPPSel4 1, NF_IO[6]
18 # bit 23-20: MPPSel5 1, NF_IO[7]
19 # bit 27-24: MPPSel6 1, SYSRST_O
20 # bit 31-28: MPPSel7 0, GPO[7]
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-stih410/
H A Dsdhci.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
11 #define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_UNIT_MHZ BIT(24)
12 #define FLASHSS_MMC_CORECFG_TIMEOUT_CLK_FREQ_MIN BIT(12)
19 #define FLASHSS_MMC_CORECFG_HIGH_SPEED BIT(28)
20 #define FLASHSS_MMC_CORECFG_8BIT_EMMC BIT(20)
21 #define MAX_BLK_LENGTH_1024 BIT(16)
36 #define FLASHSS_MMC_CORECFG_SLOT_TYPE_EMMC BIT(28)
37 #define FLASHSS_MMC_CORECFG_ASYNCH_INTR_SUPPORT BIT(20)
38 #define FLASHSS_MMC_CORECFG_3P3_VOLT BIT(8)
[all …]
/openbmc/u-boot/drivers/clk/sunxi/
H A Dclk_a23.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <clk-uclass.h>
12 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
13 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
20 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
21 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
[all …]
H A Dclk_a64.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <clk-uclass.h>
12 #include <dt-bindings/clock/sun50i-a64-ccu.h>
13 #include <dt-bindings/reset/sun50i-a64-ccu.h>
16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
[all …]
H A Dclk_a83t.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <clk-uclass.h>
12 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
13 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_BUS_EMAC] = GATE(0x060, BIT(17)),
20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
[all …]
H A Dclk_a80.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <clk-uclass.h>
12 #include <dt-bindings/clock/sun9i-a80-ccu.h>
13 #include <dt-bindings/reset/sun9i-a80-ccu.h>
16 [CLK_SPI0] = GATE(0x430, BIT(31)),
17 [CLK_SPI1] = GATE(0x434, BIT(31)),
18 [CLK_SPI2] = GATE(0x438, BIT(31)),
19 [CLK_SPI3] = GATE(0x43c, BIT(31)),
21 [CLK_BUS_MMC] = GATE(0x580, BIT(8)),
22 [CLK_BUS_SPI0] = GATE(0x580, BIT(20)),
[all …]
H A Dclk_r40.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <clk-uclass.h>
12 #include <dt-bindings/clock/sun8i-r40-ccu.h>
13 #include <dt-bindings/reset/sun8i-r40-ccu.h>
16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_BUS_MMC3] = GATE(0x060, BIT(11)),
20 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
21 [CLK_BUS_SPI1] = GATE(0x060, BIT(21)),
[all …]
H A Dclk_a31.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <clk-uclass.h>
12 #include <dt-bindings/clock/sun6i-a31-ccu.h>
13 #include <dt-bindings/reset/sun6i-a31-ccu.h>
16 [CLK_AHB1_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_AHB1_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_AHB1_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_AHB1_MMC3] = GATE(0x060, BIT(11)),
20 [CLK_AHB1_EMAC] = GATE(0x060, BIT(17)),
21 [CLK_AHB1_SPI0] = GATE(0x060, BIT(20)),
[all …]
H A Dclk_v3s.c1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <clk-uclass.h>
12 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
13 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
16 [CLK_BUS_MMC0] = GATE(0x060, BIT(8)),
17 [CLK_BUS_MMC1] = GATE(0x060, BIT(9)),
18 [CLK_BUS_MMC2] = GATE(0x060, BIT(10)),
19 [CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
20 [CLK_BUS_OTG] = GATE(0x060, BIT(24)),
22 [CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[all …]
/openbmc/u-boot/arch/mips/mach-jz47xx/jz4780/
H A Dtimer.c1 // SPDX-License-Identifier: GPL-2.0+
40 #define TCU_TCSR_PWM_SD BIT(9)
41 #define TCU_TCSR_PWM_INITL_HIGH BIT(8)
42 #define TCU_TCSR_PWM_EN BIT(7)
51 #define TCU_TCSR_EXT_EN BIT(2)
52 #define TCU_TCSR_RTC_EN BIT(1)
53 #define TCU_TCSR_PCK_EN BIT(0)
55 #define TCU_TER_TCEN5 BIT(5)
56 #define TCU_TER_TCEN4 BIT(4)
57 #define TCU_TER_TCEN3 BIT(3)
[all …]
/openbmc/u-boot/drivers/net/
H A Dftgmac100.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 * Po-Yu Chuang <ratbert@faraday-tech.com>
73 #define FTGMAC100_INT_RPKT_BUF BIT(0)
74 #define FTGMAC100_INT_RPKT_FIFO BIT(1)
75 #define FTGMAC100_INT_NO_RXBUF BIT(2)
76 #define FTGMAC100_INT_RPKT_LOST BIT(3)
77 #define FTGMAC100_INT_XPKT_ETH BIT(4)
78 #define FTGMAC100_INT_XPKT_FIFO BIT(5)
79 #define FTGMAC100_INT_NO_NPTXBUF BIT(6)
80 #define FTGMAC100_INT_XPKT_LOST BIT(7)
[all …]
/openbmc/u-boot/include/dt-bindings/mfd/
H A Dstm32f4-rcc.h1 /* SPDX-License-Identifier: GPL-2.0 */
23 #define STM32F4_RCC_AHB1_CCMDATARAM 20
34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) argument
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8)) argument
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20) argument
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) argument
52 #define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) argument
70 #define STM32F4_RCC_APB1_UART5 20
81 #define STM32F4_APB1_RESET(bit) (STM32F4_RCC_APB1_##bit + (0x20 * 8)) argument
[all …]
/openbmc/openbmc/meta-facebook/meta-catalina/recipes-phosphor/state/phosphor-state-manager/catalina/
H A Dpower-cmd3 # shellcheck source=meta-facebook/recipes-fb/obmc_functions/files/fb-common-functions
4 source /usr/libexec/fb-common-functions
28 output=$(i2ctransfer -y -f 14 w1@0x1e 0x00 r16)
33 read -ra hex_array <<< "$output"
45 [[ $1 -eq 1 ]] && echo "deassert" || echo "assert"
51 # reg[3], bit 3, wCHASSIS0_LEAK_Q_N_PLD_db
53 # reg[3], bit 2, wCHASSIS1_LEAK_Q_N_PLD_db
55 # reg[3], bit 1, wCHASSIS2_LEAK_Q_N_PLD_db
57 # reg[3], bit 0, wCHASSIS3_LEAK_Q_N_PLD_db
62 # reg[11], bit 7, PWRGD_P3V3_AUX_PLD
[all …]
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/servalt/
H A Dservalt_icpu_cfg.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
14 #define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3)
15 #define ICPU_RESET_CORE_RST_PROTECT BIT(2)
16 #define ICPU_RESET_CORE_RST_FORCE BIT(1)
17 #define ICPU_RESET_MEM_RST_FORCE BIT(0)
21 #define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(14)
22 #define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(13)
23 #define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(12)
24 #define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(11)
25 #define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ADDR_SEL BIT(10)
[all …]
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/serval/
H A Dserval_icpu_cfg.h1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
14 #define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3)
15 #define ICPU_RESET_CORE_RST_PROTECT BIT(2)
16 #define ICPU_RESET_CORE_RST_FORCE BIT(1)
17 #define ICPU_RESET_MEM_RST_FORCE BIT(0)
21 #define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(11)
22 #define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(10)
23 #define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(9)
24 #define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(8)
25 #define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ENA BIT(7)
[all …]
/openbmc/u-boot/drivers/video/meson/
H A Dmeson_dw_hdmi.h1 /* SPDX-License-Identifier: GPL-2.0 */
12 * Bit 7 RW Reserved. Default 1.
13 * Bit 6 RW Reserved. Default 1.
14 * Bit 5 RW Reserved. Default 1.
15 * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
17 * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
20 * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset.
22 * Bit 1 RW sw_reset_rnd: random number interface to HDCP. 1=Apply reset;
24 * Bit 0 RW sw_reset_core: connects to IP's ~irstz. 1=Apply reset;
30 * Bit 12 RW i2s_ws_inv:1=Invert i2s_ws; 0=No invert. Default 0.
[all …]
/openbmc/u-boot/arch/mips/mach-ath79/include/mach/
H A Dar71xx_regs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
6 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
7 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
17 #ifndef BIT
18 #define BIT(nr) (1 << (nr)) macro
295 #define AR71XX_AHB_DIV_SHIFT 20
327 #define AR913X_ETH0_PLL_SHIFT 20
342 #define AR933X_PLL_CLK_CTRL_BYPASS BIT(2)
368 #define AR934X_PLL_CPU_CONFIG_PLLPWD BIT(30)
[all …]
/openbmc/openbmc/meta-openembedded/meta-gnome/recipes-gnome/gjs/gjs/
H A D0002-meson.build-Do-not-add-dir-installed-tests-when-inst.patch2 From: =?UTF-8?q?Andreas=20M=C3=BCller=20installed=5Ftests=20is=20false?=
4 Date: Wed, 27 Oct 2021 20:04:02 +0200
5 Subject: [PATCH] meson.build: Do not add dir installed-tests when
6 MIME-Version: 1.0
7 Content-Type: text/plain; charset=UTF-8
8 Content-Transfer-Encoding: 8bit
10 MIME-Version: 1.0
11 Content-Type: text/plain; charset=UTF-8
12 Content-Transfer-Encoding: 8bit
14 MIME-Version: 1.0
[all …]
/openbmc/u-boot/arch/mips/mach-mscc/include/mach/jr2/
H A Djr2_icpu_cfg.h1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
14 #define ICPU_RESET_CORE_RST_CPU_ONLY BIT(3)
15 #define ICPU_RESET_CORE_RST_PROTECT BIT(2)
16 #define ICPU_RESET_CORE_RST_FORCE BIT(1)
17 #define ICPU_RESET_MEM_RST_FORCE BIT(0)
21 #define ICPU_GENERAL_CTRL_CPU_BUSIF_SLEEP_DIS BIT(15)
22 #define ICPU_GENERAL_CTRL_CPU_BUSIF_WERR_ENA BIT(14)
23 #define ICPU_GENERAL_CTRL_CPU_8051_IROM_ENA BIT(13)
24 #define ICPU_GENERAL_CTRL_CPU_MIPS_DIS BIT(12)
25 #define ICPU_GENERAL_CTRL_IF_MIIM_SLV_ENA BIT(11)
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/upm/upm/
H A D0001-Use-stdint-types.patch3 Date: Tue, 9 Jul 2019 05:21:59 -0700
8 Upstream-Status: Pending
10 Signed-off-by: Paul Eggleton <paul.eggleton@linux.intel.com>
11 ---
12 src/bma250e/bma250e.cxx | 16 ++++++++--------
13 src/bmg160/bmg160.cxx | 10 +++++-----
14 src/bmi160/bosch_bmi160.h | 2 +-
15 src/bmm150/bmm150.cxx | 8 ++++----
16 4 files changed, 18 insertions(+), 18 deletions(-)
18 diff --git a/src/bma250e/bma250e.cxx b/src/bma250e/bma250e.cxx
[all …]
/openbmc/u-boot/cmd/aspeed/nettest/
H A Dmactest.c1 // SPDX-License-Identifier: GPL-2.0+
55 .base_reset_assert = 0x40, .bit_reset_assert = BIT(11),
56 .base_reset_deassert = 0x44,.bit_reset_deassert = BIT(11),
57 .base_clk_stop = 0x80, .bit_clk_stop = BIT(20),
58 .base_clk_start = 0x84, .bit_clk_start = BIT(20),
61 .base_reset_assert = 0x40, .bit_reset_assert = BIT(12),
62 .base_reset_deassert = 0x44,.bit_reset_deassert = BIT(12),
63 .base_clk_stop = 0x80, .bit_clk_stop = BIT(21),
64 .base_clk_start = 0x84,.bit_clk_start = BIT(21),
67 .base_reset_assert = 0x50, .bit_reset_assert = BIT(20),
[all …]
/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dmv_ddr_spd.c1 // SPDX-License-Identifier: GPL-2.0
18 unsigned int byte, bit, start_cl; in mv_ddr_spd_supported_cls_calc() local
20 start_cl = (spd_data->all_bytes[23] & 0x8) ? 23 : 7; in mv_ddr_spd_supported_cls_calc()
22 for (byte = 20; byte < 23; byte++) { in mv_ddr_spd_supported_cls_calc()
23 for (bit = 0; bit < 8; bit++) { in mv_ddr_spd_supported_cls_calc()
24 if (spd_data->all_bytes[byte] & (1 << bit)) in mv_ddr_spd_supported_cls_calc()
25 mv_ddr_spd_supported_cls[(byte - 20) * 8 + bit] = start_cl + (byte - 20) * 8 + bit; in mv_ddr_spd_supported_cls_calc()
27 mv_ddr_spd_supported_cls[(byte - 20) * 8 + bit] = 0; in mv_ddr_spd_supported_cls_calc()
31 for (byte = 23, bit = 0; bit < 6; bit++) { in mv_ddr_spd_supported_cls_calc()
32 if (spd_data->all_bytes[byte] & (1 << bit)) in mv_ddr_spd_supported_cls_calc()
[all …]

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