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/openbmc/linux/drivers/mtd/spi-nor/
H A Dsfdp.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #define SFDP_DWORD(i) ((i) - 1)
22 /* JESD216 rev D defines a Basic Flash Parameter Table of 20 DWORDs. */
23 #define BFPT_DWORD_MAX 20
34 #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
39 #define BFPT_DWORD1_DTR BIT(19)
40 #define BFPT_DWORD1_FAST_READ_1_2_2 BIT(20)
41 #define BFPT_DWORD1_FAST_READ_1_4_4 BIT(21)
42 #define BFPT_DWORD1_FAST_READ_1_1_4 BIT(22)
45 #define BFPT_DWORD5_FAST_READ_2_2_2 BIT(0)
[all …]
/openbmc/linux/sound/soc/mediatek/mt8186/
H A Dmt8186-reg.h1 /* SPDX-License-Identifier: GPL-2.0
3 * mt8186-reg.h -- Mediatek 8186 audio driver reg definition
12 /* reg bit enum */
26 #define RESERVED_MASK_SFT BIT(31)
28 #define AHB_IDLE_EN_INT_MASK_SFT BIT(30)
30 #define AHB_IDLE_EN_EXT_MASK_SFT BIT(29)
32 #define PDN_NLE_MASK_SFT BIT(28)
34 #define PDN_TML_MASK_SFT BIT(27)
36 #define PDN_DAC_PREDIS_MASK_SFT BIT(26)
38 #define PDN_DAC_MASK_SFT BIT(25)
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/openbmc/linux/include/linux/mfd/syscon/
H A Dimx6q-iomuxc-gpr.h1 /* SPDX-License-Identifier: GPL-2.0-only */
50 #define IMX6Q_GPR0_CLOCK_2_MUX_SEL_MASK (0x3 << 20)
51 #define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2_MUXED (0x0 << 20)
52 #define IMX6Q_GPR0_CLOCK_2_MUX_SEL_AUDMUX_RXCLK_P2 (0x1 << 20)
53 #define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_SSI_SRCK (0x2 << 20)
54 #define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_RX_BIT_CLK (0x3 << 20)
69 #define IMX6Q_GPR0_DMAREQ_MUX_SEL7_MASK BIT(7)
71 #define IMX6Q_GPR0_DMAREQ_MUX_SEL7_IOMUX BIT(7)
72 #define IMX6Q_GPR0_DMAREQ_MUX_SEL6_MASK BIT(6)
74 #define IMX6Q_GPR0_DMAREQ_MUX_SEL6_I2C3 BIT(6)
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/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac4.h1 /* SPDX-License-Identifier: GPL-2.0-only */
67 #define GMAC_RXQCTRL_MCBCQEN BIT(20)
68 #define GMAC_RXQCTRL_MCBCQEN_SHIFT 20
69 #define GMAC_RXQCTRL_TACPQE BIT(21)
75 #define GMAC_PACKET_FILTER_PR BIT(0)
76 #define GMAC_PACKET_FILTER_HMC BIT(2)
77 #define GMAC_PACKET_FILTER_PM BIT(4)
78 #define GMAC_PACKET_FILTER_PCF BIT(7)
79 #define GMAC_PACKET_FILTER_HPF BIT(10)
80 #define GMAC_PACKET_FILTER_VTFE BIT(16)
[all …]
/openbmc/u-boot/board/keymile/km_arm/
H A Dkwbimage_256M8_1.cfg1 # SPDX-License-Identifier: GPL-2.0+
7 # Refer doc/README.kwbimage for more details about how-to configure
10 # This configuration applies to COGE5 design (ARM-part)
11 # Two 8-Bit devices are connected on the 16-Bit bus on the same
12 # chip-select. The supported devices are
13 # MT47H256M8EB-3IT:C
14 # MT47H256M8EB-25EIT:C
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_MOSI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
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H A Dkwbimage_128M16_1.cfg1 # SPDX-License-Identifier: GPL-2.0+
12 # Refer doc/README.kwbimage for more details about how-to configure
20 # bit 3-0: 2, MPPSel0 SPI_CSn (1=NF_IO[2])
21 # bit 7-4: 2, MPPSel1 SPI_SI (1=NF_IO[3])
22 # bit 12-8: 2, MPPSel2 SPI_SCK (1=NF_IO[4])
23 # bit 15-12: 2, MPPSel3 SPI_SO (1=NF_IO[5])
24 # bit 19-16: 1, MPPSel4 NF_IO[6]
25 # bit 23-20: 1, MPPSel5 NF_IO[7]
26 # bit 27-24: 1, MPPSel6 SYSRST_O
27 # bit 31-28: 0, MPPSel7 GPO[7]
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/openbmc/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
41 #define MT_TX_FREE_PAIR BIT(31)
50 #define MT_TXD1_LONG_FORMAT BIT(31)
51 #define MT_TXD1_TGID BIT(30)
53 #define MT_TXD1_AMSDU BIT(23)
54 #define MT_TXD1_TID GENMASK(22, 20)
58 #define MT_TXD1_ETH_802_3 BIT(15)
59 #define MT_TXD1_VTA BIT(10)
62 #define MT_TXD2_FIX_RATE BIT(31)
63 #define MT_TXD2_FIXED_RATE BIT(30)
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H A Dmt76_connac3_mac.h1 /* SPDX-License-Identifier: ISC */
28 #define MT_RXD0_MESH BIT(18)
29 #define MT_RXD0_MHCP BIT(19)
31 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
32 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
40 #define MT_RXD1_NORMAL_GROUP_1 BIT(16)
41 #define MT_RXD1_NORMAL_GROUP_2 BIT(17)
42 #define MT_RXD1_NORMAL_GROUP_3 BIT(18)
43 #define MT_RXD1_NORMAL_GROUP_4 BIT(19)
44 #define MT_RXD1_NORMAL_GROUP_5 BIT(20)
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/openbmc/linux/drivers/net/phy/mscc/
H A Dmscc_mac.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
77 #define MSCC_MAC_CFG_ENA_CFG_RX_CLK_ENA BIT(0)
78 #define MSCC_MAC_CFG_ENA_CFG_TX_CLK_ENA BIT(4)
79 #define MSCC_MAC_CFG_ENA_CFG_RX_SW_RST BIT(8)
80 #define MSCC_MAC_CFG_ENA_CFG_TX_SW_RST BIT(12)
81 #define MSCC_MAC_CFG_ENA_CFG_RX_ENA BIT(16)
82 #define MSCC_MAC_CFG_ENA_CFG_TX_ENA BIT(20)
84 #define MSCC_MAC_CFG_MODE_CFG_FORCE_CW_UPDATE_INTERVAL(x) ((x) << 20)
85 #define MSCC_MAC_CFG_MODE_CFG_FORCE_CW_UPDATE_INTERVAL_M GENMASK(29, 20)
86 #define MSCC_MAC_CFG_MODE_CFG_FORCE_CW_UPDATE BIT(16)
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/openbmc/linux/include/soc/mscc/
H A Docelot_sys.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
17 #define SYS_FRONT_PORT_MODE_HDX_MODE BIT(0)
19 #define SYS_FRM_AGING_AGE_TX_ENA BIT(20)
31 #define SYS_SW_STATUS_PORT_RX_PAUSED BIT(0)
33 #define SYS_MISC_CFG_PTP_RSRV_CLR BIT(1)
34 #define SYS_MISC_CFG_PTP_DIS_NEG_RO BIT(0)
59 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG(x) (((x) << 20) & GENMASK(25, 20))
60 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_M GENMASK(25, 20)
61 #define SYS_MAC_FC_CFG_FC_LATENCY_CFG_X(x) (((x) & GENMASK(25, 20)) >> 20)
62 #define SYS_MAC_FC_CFG_ZERO_PAUSE_ENA BIT(18)
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H A Docelot_hsio.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
85 #define HSIO_PLL5G_CFG0_ENA_ROT BIT(31)
86 #define HSIO_PLL5G_CFG0_ENA_LANE BIT(30)
87 #define HSIO_PLL5G_CFG0_ENA_CLKTREE BIT(29)
88 #define HSIO_PLL5G_CFG0_DIV4 BIT(28)
89 #define HSIO_PLL5G_CFG0_ENA_LOCK_FINE BIT(27)
99 #define HSIO_PLL5G_CFG0_ENA_VCO_CONTRH BIT(15)
100 #define HSIO_PLL5G_CFG0_ENA_CP1 BIT(14)
101 #define HSIO_PLL5G_CFG0_ENA_VCO_BUF BIT(13)
102 #define HSIO_PLL5G_CFG0_ENA_BIAS BIT(12)
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H A Docelot_ana.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define ANA_ANAGEFIL_B_DOM_EN BIT(22)
12 #define ANA_ANAGEFIL_B_DOM_VAL BIT(21)
13 #define ANA_ANAGEFIL_AGE_LOCKED BIT(20)
14 #define ANA_ANAGEFIL_PID_EN BIT(19)
18 #define ANA_ANAGEFIL_VID_EN BIT(13)
27 #define ANA_STORMLIMIT_CFG_STORM_UNIT BIT(2)
31 #define ANA_AUTOAGE_AGE_FAST BIT(21)
32 #define ANA_AUTOAGE_AGE_PERIOD(x) (((x) << 1) & GENMASK(20, 1))
33 #define ANA_AUTOAGE_AGE_PERIOD_M GENMASK(20, 1)
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/openbmc/linux/drivers/clk/stm32/
H A Dstm32mp13_rcc.h1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
3 * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
229 #define RCC_SECCFGR_TIMG3SEC 20
238 #define RCC_MP_SREQSETR_STPREQ_P0 BIT(0)
241 #define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0)
244 #define RCC_MP_APRSTCR_RDCTLEN BIT(0)
257 #define RCC_MP_GRSTCSETR_MPSYSRST BIT(0)
258 #define RCC_MP_GRSTCSETR_MPUP0RST BIT(4)
261 #define RCC_BR_RSTSCLRR_PORRSTF BIT(0)
262 #define RCC_BR_RSTSCLRR_BORRSTF BIT(1)
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/openbmc/linux/Documentation/userspace-api/media/rc/
H A Drc-protos.rst1 .. SPDX-License-Identifier: GPL-2.0 OR GFDL-1.1-no-invariants-or-later
17 Other things can be encoded too. Some IR protocols encode a toggle bit; this
20 toggle bit will invert from one IR message to the next.
22 Some remotes have a pointer-type device which can used to control the
29 rc-5 (RC_PROTO_RC5)
30 -------------------
38 .. flat-table:: rc5 bits scancode mapping
41 * - rc-5 bit
43 - scancode bit
45 - description
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/openbmc/linux/sound/soc/hisilicon/
H A Dhi6210-i2s.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/sound/soc/hisilicon/hi6210-i2s.h
22 #define HII2S_SW_RST_N__ST_DL_WORDLEN_SHIFT 20
29 #define HII2S_SW_RST_N__SW_RST_N BIT(0)
41 #define HII2S_IF_CLK_EN_CFG__THIRDMD_UPLINK_EN BIT(25)
42 #define HII2S_IF_CLK_EN_CFG__THIRDMD_DLINK_EN BIT(24)
43 #define HII2S_IF_CLK_EN_CFG__S3_IF_CLK_EN BIT(20)
44 #define HII2S_IF_CLK_EN_CFG__S2_IF_CLK_EN BIT(16)
45 #define HII2S_IF_CLK_EN_CFG__S2_OL_MIXER_EN BIT(15)
46 #define HII2S_IF_CLK_EN_CFG__S2_OL_SRC_EN BIT(14)
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/openbmc/linux/sound/soc/mediatek/mt7986/
H A Dmt7986-reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * mt7986-reg.h -- MediaTek 7986 audio driver reg definition
75 #define CLK_OUT5_PDN BIT(14)
76 #define CLK_OUT5_PDN_MASK BIT(14)
77 #define CLK_IN5_PDN BIT(7)
78 #define CLK_IN5_PDN_MASK BIT(7)
81 #define PDN_APLL_TUNER2 BIT(12)
82 #define PDN_APLL_TUNER2_MASK BIT(12)
85 #define AUD_APLL2_EN BIT(3)
86 #define AUD_APLL2_EN_MASK BIT(3)
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/openbmc/linux/drivers/gpu/drm/mcde/
H A Dmcde_dsi_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #define DSI_MCTL_MAIN_DATA_CTL_LINK_EN BIT(0)
9 #define DSI_MCTL_MAIN_DATA_CTL_IF1_MODE BIT(1)
10 #define DSI_MCTL_MAIN_DATA_CTL_VID_EN BIT(2)
11 #define DSI_MCTL_MAIN_DATA_CTL_TVG_SEL BIT(3)
12 #define DSI_MCTL_MAIN_DATA_CTL_TBG_SEL BIT(4)
13 #define DSI_MCTL_MAIN_DATA_CTL_IF1_TE_EN BIT(5)
14 #define DSI_MCTL_MAIN_DATA_CTL_IF2_TE_EN BIT(6)
15 #define DSI_MCTL_MAIN_DATA_CTL_REG_TE_EN BIT(7)
16 #define DSI_MCTL_MAIN_DATA_CTL_READ_EN BIT(8)
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/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7603/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
10 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
11 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
12 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
13 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
14 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
15 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
29 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
30 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
34 #define MT_RXD1_NORMAL_BEACON_UC BIT(5)
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H A Dregs.h1 /* SPDX-License-Identifier: ISC */
28 #define MT_INT_RX_DONE(_n) BIT(_n)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
33 #define MT_INT_RX_COHERENT BIT(20)
34 #define MT_INT_TX_COHERENT BIT(21)
35 #define MT_INT_MAC_IRQ3 BIT(27)
37 #define MT_INT_MCU_CMD BIT(30)
40 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
41 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
42 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
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/openbmc/linux/arch/mips/loongson2ef/common/
H A Dmem.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 memblock_add(0x0, (memsize << 20)); in prom_init_memory()
24 int bit; in prom_init_memory() local
26 bit = fls(memsize + highmemsize); in prom_init_memory()
27 if (bit != ffs(memsize + highmemsize)) in prom_init_memory()
28 bit += 20; in prom_init_memory()
30 bit = bit + 20 - 1; in prom_init_memory()
32 /* set cpu window3 to map CPU to DDR: 2G -> 2G */ in prom_init_memory()
34 0x80000000ul, (1 << bit)); in prom_init_memory()
41 memblock_add(LOONGSON_HIGHMEM_START, highmemsize << 20); in prom_init_memory()
/openbmc/linux/drivers/phy/amlogic/
H A Dphy-meson-g12a-usb2.c1 // SPDX-License-Identifier: GPL-2.0
35 #define PHY_CTRL_R4_I_C2L_CAL_EN BIT(24)
36 #define PHY_CTRL_R4_I_C2L_CAL_RESET_N BIT(25)
37 #define PHY_CTRL_R4_I_C2L_CAL_DONE BIT(26)
38 #define PHY_CTRL_R4_TEST_BYPASS_MODE_EN BIT(27)
52 #define PHY_CTRL_R13_LOAD_STAT BIT(14)
53 #define PHY_CTRL_R13_UPDATE_PMA_SIGNALS BIT(15)
54 #define PHY_CTRL_R13_MIN_COUNT_FOR_SYNC_DET GENMASK(20, 16)
55 #define PHY_CTRL_R13_CLEAR_HOLD_HS_DISCONNECT BIT(21)
56 #define PHY_CTRL_R13_BYPASS_HOST_DISCONNECT_VAL BIT(22)
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/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
25 #define MT_RXD1_MID_AMSDU_FRAME BIT(1)
26 #define MT_RXD1_LAST_AMSDU_FRAME BIT(0)
27 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
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/openbmc/linux/drivers/phy/mediatek/
H A Dphy-mtk-hdmi-mt8195.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <linux/clk-provider.h>
23 #define RG_HDMITX21_DRV_IMP_EN GENMASK(23, 20)
29 #define RG_HDMITX21_DRV_IBIAS_D1 GENMASK(25, 20)
34 #define RG_HDMITX21_VREF_SEL BIT(4)
35 #define RG_HDMITX21_BIAS_PE_VREF_SELB BIT(10)
37 #define RG_HDMITX21_BG_PWD BIT(20)
42 #define RG_HDMITX21_DRV_IMP_D2_EN1 GENMASK(25, 20)
46 #define RG_HDMITX21_CKLDO_EN BIT(3)
47 #define RG_HDMITX21_SLDOLPF_EN BIT(7)
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/openbmc/linux/drivers/staging/sm750fb/
H A Dddk750_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #define DE_STATE1_DE_ABORT BIT(0)
10 #define DE_STATE2_DE_FIFO_EMPTY BIT(3)
11 #define DE_STATE2_DE_STATUS_BUSY BIT(2)
12 #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1)
20 #define SYSTEM_CTRL_PCI_BURST BIT(29)
21 #define SYSTEM_CTRL_PCI_MASTER BIT(25)
22 #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24)
23 #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23)
24 #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22)
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/openbmc/u-boot/arch/mips/mach-jz47xx/jz4780/
H A Dtimer.c1 // SPDX-License-Identifier: GPL-2.0+
40 #define TCU_TCSR_PWM_SD BIT(9)
41 #define TCU_TCSR_PWM_INITL_HIGH BIT(8)
42 #define TCU_TCSR_PWM_EN BIT(7)
51 #define TCU_TCSR_EXT_EN BIT(2)
52 #define TCU_TCSR_RTC_EN BIT(1)
53 #define TCU_TCSR_PCK_EN BIT(0)
55 #define TCU_TER_TCEN5 BIT(5)
56 #define TCU_TER_TCEN4 BIT(4)
57 #define TCU_TER_TCEN3 BIT(3)
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