clk/sunxi/clk_v3s.c

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <clk-uclass.h>
12 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
13 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
16 	[CLK_BUS_MMC0]		= GATE(0x060, BIT(8)),
17 	[CLK_BUS_MMC1]		= GATE(0x060, BIT(9)),
18 	[CLK_BUS_MMC2]		= GATE(0x060, BIT(10)),
19 	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
20 	[CLK_BUS_OTG]		= GATE(0x060, BIT(24)),
22 	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
23 	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
24 	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
26 	[CLK_SPI0]		= GATE(0x0a0, BIT(31)),
28 	[CLK_USB_PHY0]          = GATE(0x0cc, BIT(8)),
32 	[RST_USB_PHY0]		= RESET(0x0cc, BIT(0)),
34 	[RST_BUS_MMC0]		= RESET(0x2c0, BIT(8)),
35 	[RST_BUS_MMC1]		= RESET(0x2c0, BIT(9)),
36 	[RST_BUS_MMC2]		= RESET(0x2c0, BIT(10)),
37 	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
38 	[RST_BUS_OTG]		= RESET(0x2c0, BIT(24)),
40 	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
41 	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
42 	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
56 	{ .compatible = "allwinner,sun8i-v3s-ccu",