1 /* SPDX-License-Identifier: GPL-2.0 */
23 #define STM32F4_RCC_AHB1_CCMDATARAM	20
34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8))  argument
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit)  argument
44 #define STM32F4_AHB2_RESET(bit)	(STM32F4_RCC_AHB2_##bit + (0x14 * 8))  argument
45 #define STM32F4_AHB2_CLOCK(bit)	(STM32F4_RCC_AHB2_##bit + 0x20)  argument
51 #define STM32F4_AHB3_RESET(bit)	(STM32F4_RCC_AHB3_##bit + (0x18 * 8))  argument
52 #define STM32F4_AHB3_CLOCK(bit)	(STM32F4_RCC_AHB3_##bit + 0x40)  argument
70 #define STM32F4_RCC_APB1_UART5	20
81 #define STM32F4_APB1_RESET(bit)	(STM32F4_RCC_APB1_##bit + (0x20 * 8))  argument
82 #define STM32F4_APB1_CLOCK(bit)	(STM32F4_RCC_APB1_##bit + 0x80)  argument
99 #define STM32F4_RCC_APB2_SPI5	20
105 #define STM32F4_APB2_RESET(bit)	(STM32F4_RCC_APB2_##bit + (0x24 * 8))  argument
106 #define STM32F4_APB2_CLOCK(bit)	(STM32F4_RCC_APB2_##bit + 0xA0)  argument