Lines Matching +full:20 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
6 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
7 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
17 #ifndef BIT
18 #define BIT(nr) (1 << (nr)) macro
295 #define AR71XX_AHB_DIV_SHIFT 20
327 #define AR913X_ETH0_PLL_SHIFT 20
342 #define AR933X_PLL_CLK_CTRL_BYPASS BIT(2)
368 #define AR934X_PLL_CPU_CONFIG_PLLPWD BIT(30)
369 #define AR934X_PLL_CPU_CONFIG_UPDATING BIT(31)
381 #define AR934X_PLL_DDR_CONFIG_PLLPWD BIT(30)
382 #define AR934X_PLL_DDR_CONFIG_UPDATING BIT(31)
384 #define AR934X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
385 #define AR934X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
386 #define AR934X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
393 #define AR934X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
394 #define AR934X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
395 #define AR934X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
397 #define AR934X_PLL_SWITCH_CLK_CTRL_MDIO_CLK_SEL BIT(6)
403 #define AR934X_PLL_DDR_DIT_FRAC_STEP_SHIFT 20
407 #define AR934X_PLL_DDR_DIT_DITHER_EN BIT(31)
417 #define AR934X_PLL_CPU_DIT_DITHER_EN BIT(31)
445 #define QCA953X_PLL_CONFIG_PWD BIT(30)
447 #define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
448 #define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
449 #define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
456 #define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
457 #define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
458 #define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
473 #define QCA953X_PLL_DDR_DIT_FRAC_STEP_SHIFT 20
478 #define QCA953X_PLL_DIT_FRAC_EN BIT(31)
504 #define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
505 #define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
506 #define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
513 #define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
514 #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
515 #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
547 #define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
548 #define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
549 #define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
556 #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20)
557 #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21)
558 #define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
611 #define MISC_INT_MIPS_SI_TIMERINT_MASK BIT(28)
612 #define MISC_INT_ETHSW BIT(12)
613 #define MISC_INT_TIMER4 BIT(10)
614 #define MISC_INT_TIMER3 BIT(9)
615 #define MISC_INT_TIMER2 BIT(8)
616 #define MISC_INT_DMA BIT(7)
617 #define MISC_INT_OHCI BIT(6)
618 #define MISC_INT_PERFC BIT(5)
619 #define MISC_INT_WDOG BIT(4)
620 #define MISC_INT_UART BIT(3)
621 #define MISC_INT_GPIO BIT(2)
622 #define MISC_INT_ERROR BIT(1)
623 #define MISC_INT_TIMER BIT(0)
625 #define AR71XX_RESET_EXTERNAL BIT(28)
626 #define AR71XX_RESET_FULL_CHIP BIT(24)
627 #define AR71XX_RESET_CPU_NMI BIT(21)
628 #define AR71XX_RESET_CPU_COLD BIT(20)
629 #define AR71XX_RESET_DMA BIT(19)
630 #define AR71XX_RESET_SLIC BIT(18)
631 #define AR71XX_RESET_STEREO BIT(17)
632 #define AR71XX_RESET_DDR BIT(16)
633 #define AR71XX_RESET_GE1_MAC BIT(13)
634 #define AR71XX_RESET_GE1_PHY BIT(12)
635 #define AR71XX_RESET_USBSUS_OVERRIDE BIT(10)
636 #define AR71XX_RESET_GE0_MAC BIT(9)
637 #define AR71XX_RESET_GE0_PHY BIT(8)
638 #define AR71XX_RESET_USB_OHCI_DLL BIT(6)
639 #define AR71XX_RESET_USB_HOST BIT(5)
640 #define AR71XX_RESET_USB_PHY BIT(4)
641 #define AR71XX_RESET_PCI_BUS BIT(1)
642 #define AR71XX_RESET_PCI_CORE BIT(0)
644 #define AR7240_RESET_USB_HOST BIT(5)
645 #define AR7240_RESET_OHCI_DLL BIT(3)
647 #define AR724X_RESET_GE1_MDIO BIT(23)
648 #define AR724X_RESET_GE0_MDIO BIT(22)
649 #define AR724X_RESET_PCIE_PHY_SERIAL BIT(10)
650 #define AR724X_RESET_PCIE_PHY BIT(7)
651 #define AR724X_RESET_PCIE BIT(6)
652 #define AR724X_RESET_USB_HOST BIT(5)
653 #define AR724X_RESET_USB_PHY BIT(4)
654 #define AR724X_RESET_USBSUS_OVERRIDE BIT(3)
656 #define AR913X_RESET_AMBA2WMAC BIT(22)
657 #define AR913X_RESET_USBSUS_OVERRIDE BIT(10)
658 #define AR913X_RESET_USB_HOST BIT(5)
659 #define AR913X_RESET_USB_PHY BIT(4)
661 #define AR933X_RESET_GE1_MDIO BIT(23)
662 #define AR933X_RESET_GE0_MDIO BIT(22)
663 #define AR933X_RESET_ETH_SWITCH_ANALOG BIT(14)
664 #define AR933X_RESET_GE1_MAC BIT(13)
665 #define AR933X_RESET_WMAC BIT(11)
666 #define AR933X_RESET_GE0_MAC BIT(9)
667 #define AR933X_RESET_ETH_SWITCH BIT(8)
668 #define AR933X_RESET_USB_HOST BIT(5)
669 #define AR933X_RESET_USB_PHY BIT(4)
670 #define AR933X_RESET_USBSUS_OVERRIDE BIT(3)
672 #define AR934X_RESET_HOST BIT(31)
673 #define AR934X_RESET_SLIC BIT(30)
674 #define AR934X_RESET_HDMA BIT(29)
675 #define AR934X_RESET_EXTERNAL BIT(28)
676 #define AR934X_RESET_RTC BIT(27)
677 #define AR934X_RESET_PCIE_EP_INT BIT(26)
678 #define AR934X_RESET_CHKSUM_ACC BIT(25)
679 #define AR934X_RESET_FULL_CHIP BIT(24)
680 #define AR934X_RESET_GE1_MDIO BIT(23)
681 #define AR934X_RESET_GE0_MDIO BIT(22)
682 #define AR934X_RESET_CPU_NMI BIT(21)
683 #define AR934X_RESET_CPU_COLD BIT(20)
684 #define AR934X_RESET_HOST_RESET_INT BIT(19)
685 #define AR934X_RESET_PCIE_EP BIT(18)
686 #define AR934X_RESET_UART1 BIT(17)
687 #define AR934X_RESET_DDR BIT(16)
688 #define AR934X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
689 #define AR934X_RESET_NANDF BIT(14)
690 #define AR934X_RESET_GE1_MAC BIT(13)
691 #define AR934X_RESET_ETH_SWITCH_ANALOG BIT(12)
692 #define AR934X_RESET_USB_PHY_ANALOG BIT(11)
693 #define AR934X_RESET_HOST_DMA_INT BIT(10)
694 #define AR934X_RESET_GE0_MAC BIT(9)
695 #define AR934X_RESET_ETH_SWITCH BIT(8)
696 #define AR934X_RESET_PCIE_PHY BIT(7)
697 #define AR934X_RESET_PCIE BIT(6)
698 #define AR934X_RESET_USB_HOST BIT(5)
699 #define AR934X_RESET_USB_PHY BIT(4)
700 #define AR934X_RESET_USBSUS_OVERRIDE BIT(3)
701 #define AR934X_RESET_LUT BIT(2)
702 #define AR934X_RESET_MBOX BIT(1)
703 #define AR934X_RESET_I2S BIT(0)
705 #define QCA953X_RESET_USB_EXT_PWR BIT(29)
706 #define QCA953X_RESET_EXTERNAL BIT(28)
707 #define QCA953X_RESET_RTC BIT(27)
708 #define QCA953X_RESET_FULL_CHIP BIT(24)
709 #define QCA953X_RESET_GE1_MDIO BIT(23)
710 #define QCA953X_RESET_GE0_MDIO BIT(22)
711 #define QCA953X_RESET_CPU_NMI BIT(21)
712 #define QCA953X_RESET_CPU_COLD BIT(20)
713 #define QCA953X_RESET_DDR BIT(16)
714 #define QCA953X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
715 #define QCA953X_RESET_GE1_MAC BIT(13)
716 #define QCA953X_RESET_ETH_SWITCH_ANALOG BIT(12)
717 #define QCA953X_RESET_USB_PHY_ANALOG BIT(11)
718 #define QCA953X_RESET_GE0_MAC BIT(9)
719 #define QCA953X_RESET_ETH_SWITCH BIT(8)
720 #define QCA953X_RESET_PCIE_PHY BIT(7)
721 #define QCA953X_RESET_PCIE BIT(6)
722 #define QCA953X_RESET_USB_HOST BIT(5)
723 #define QCA953X_RESET_USB_PHY BIT(4)
724 #define QCA953X_RESET_USBSUS_OVERRIDE BIT(3)
726 #define QCA955X_RESET_HOST BIT(31)
727 #define QCA955X_RESET_SLIC BIT(30)
728 #define QCA955X_RESET_HDMA BIT(29)
729 #define QCA955X_RESET_EXTERNAL BIT(28)
730 #define QCA955X_RESET_RTC BIT(27)
731 #define QCA955X_RESET_PCIE_EP_INT BIT(26)
732 #define QCA955X_RESET_CHKSUM_ACC BIT(25)
733 #define QCA955X_RESET_FULL_CHIP BIT(24)
734 #define QCA955X_RESET_GE1_MDIO BIT(23)
735 #define QCA955X_RESET_GE0_MDIO BIT(22)
736 #define QCA955X_RESET_CPU_NMI BIT(21)
737 #define QCA955X_RESET_CPU_COLD BIT(20)
738 #define QCA955X_RESET_HOST_RESET_INT BIT(19)
739 #define QCA955X_RESET_PCIE_EP BIT(18)
740 #define QCA955X_RESET_UART1 BIT(17)
741 #define QCA955X_RESET_DDR BIT(16)
742 #define QCA955X_RESET_USB_PHY_PLL_PWD_EXT BIT(15)
743 #define QCA955X_RESET_NANDF BIT(14)
744 #define QCA955X_RESET_GE1_MAC BIT(13)
745 #define QCA955X_RESET_SGMII_ANALOG BIT(12)
746 #define QCA955X_RESET_USB_PHY_ANALOG BIT(11)
747 #define QCA955X_RESET_HOST_DMA_INT BIT(10)
748 #define QCA955X_RESET_GE0_MAC BIT(9)
749 #define QCA955X_RESET_SGMII BIT(8)
750 #define QCA955X_RESET_PCIE_PHY BIT(7)
751 #define QCA955X_RESET_PCIE BIT(6)
752 #define QCA955X_RESET_USB_HOST BIT(5)
753 #define QCA955X_RESET_USB_PHY BIT(4)
754 #define QCA955X_RESET_USBSUS_OVERRIDE BIT(3)
755 #define QCA955X_RESET_LUT BIT(2)
756 #define QCA955X_RESET_MBOX BIT(1)
757 #define QCA955X_RESET_I2S BIT(0)
759 #define AR933X_BOOTSTRAP_MDIO_GPIO_EN BIT(18)
760 #define AR933X_BOOTSTRAP_DDR2 BIT(13)
761 #define AR933X_BOOTSTRAP_EEPBUSY BIT(4)
762 #define AR933X_BOOTSTRAP_REF_CLK_40 BIT(0)
764 #define AR934X_BOOTSTRAP_SW_OPTION8 BIT(23)
765 #define AR934X_BOOTSTRAP_SW_OPTION7 BIT(22)
766 #define AR934X_BOOTSTRAP_SW_OPTION6 BIT(21)
767 #define AR934X_BOOTSTRAP_SW_OPTION5 BIT(20)
768 #define AR934X_BOOTSTRAP_SW_OPTION4 BIT(19)
769 #define AR934X_BOOTSTRAP_SW_OPTION3 BIT(18)
770 #define AR934X_BOOTSTRAP_SW_OPTION2 BIT(17)
771 #define AR934X_BOOTSTRAP_SW_OPTION1 BIT(16)
772 #define AR934X_BOOTSTRAP_USB_MODE_DEVICE BIT(7)
773 #define AR934X_BOOTSTRAP_PCIE_RC BIT(6)
774 #define AR934X_BOOTSTRAP_EJTAG_MODE BIT(5)
775 #define AR934X_BOOTSTRAP_REF_CLK_40 BIT(4)
776 #define AR934X_BOOTSTRAP_BOOT_FROM_SPI BIT(2)
777 #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
778 #define AR934X_BOOTSTRAP_DDR1 BIT(0)
780 #define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12)
781 #define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11)
782 #define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5)
783 #define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4)
784 #define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
785 #define QCA953X_BOOTSTRAP_DDR1 BIT(0)
787 #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
789 #define QCA956X_BOOTSTRAP_REF_CLK_40 BIT(2)
791 #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
792 #define AR934X_PCIE_WMAC_INT_WMAC_TX BIT(1)
793 #define AR934X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
794 #define AR934X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
795 #define AR934X_PCIE_WMAC_INT_PCIE_RC BIT(4)
796 #define AR934X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
797 #define AR934X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
798 #define AR934X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
799 #define AR934X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
809 #define QCA953X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
810 #define QCA953X_PCIE_WMAC_INT_WMAC_TX BIT(1)
811 #define QCA953X_PCIE_WMAC_INT_WMAC_RXLP BIT(2)
812 #define QCA953X_PCIE_WMAC_INT_WMAC_RXHP BIT(3)
813 #define QCA953X_PCIE_WMAC_INT_PCIE_RC BIT(4)
814 #define QCA953X_PCIE_WMAC_INT_PCIE_RC0 BIT(5)
815 #define QCA953X_PCIE_WMAC_INT_PCIE_RC1 BIT(6)
816 #define QCA953X_PCIE_WMAC_INT_PCIE_RC2 BIT(7)
817 #define QCA953X_PCIE_WMAC_INT_PCIE_RC3 BIT(8)
827 #define QCA955X_EXT_INT_WMAC_MISC BIT(0)
828 #define QCA955X_EXT_INT_WMAC_TX BIT(1)
829 #define QCA955X_EXT_INT_WMAC_RXLP BIT(2)
830 #define QCA955X_EXT_INT_WMAC_RXHP BIT(3)
831 #define QCA955X_EXT_INT_PCIE_RC1 BIT(4)
832 #define QCA955X_EXT_INT_PCIE_RC1_INT0 BIT(5)
833 #define QCA955X_EXT_INT_PCIE_RC1_INT1 BIT(6)
834 #define QCA955X_EXT_INT_PCIE_RC1_INT2 BIT(7)
835 #define QCA955X_EXT_INT_PCIE_RC1_INT3 BIT(8)
836 #define QCA955X_EXT_INT_PCIE_RC2 BIT(12)
837 #define QCA955X_EXT_INT_PCIE_RC2_INT0 BIT(13)
838 #define QCA955X_EXT_INT_PCIE_RC2_INT1 BIT(14)
839 #define QCA955X_EXT_INT_PCIE_RC2_INT2 BIT(15)
840 #define QCA955X_EXT_INT_PCIE_RC2_INT3 BIT(16)
841 #define QCA955X_EXT_INT_USB1 BIT(24)
842 #define QCA955X_EXT_INT_USB2 BIT(28)
858 #define QCA956X_EXT_INT_WMAC_MISC BIT(0)
859 #define QCA956X_EXT_INT_WMAC_TX BIT(1)
860 #define QCA956X_EXT_INT_WMAC_RXLP BIT(2)
861 #define QCA956X_EXT_INT_WMAC_RXHP BIT(3)
862 #define QCA956X_EXT_INT_PCIE_RC1 BIT(4)
863 #define QCA956X_EXT_INT_PCIE_RC1_INT0 BIT(5)
864 #define QCA956X_EXT_INT_PCIE_RC1_INT1 BIT(6)
865 #define QCA956X_EXT_INT_PCIE_RC1_INT2 BIT(7)
866 #define QCA956X_EXT_INT_PCIE_RC1_INT3 BIT(8)
867 #define QCA956X_EXT_INT_PCIE_RC2 BIT(12)
868 #define QCA956X_EXT_INT_PCIE_RC2_INT0 BIT(13)
869 #define QCA956X_EXT_INT_PCIE_RC2_INT1 BIT(14)
870 #define QCA956X_EXT_INT_PCIE_RC2_INT2 BIT(15)
871 #define QCA956X_EXT_INT_PCIE_RC2_INT3 BIT(16)
872 #define QCA956X_EXT_INT_USB1 BIT(24)
873 #define QCA956X_EXT_INT_USB2 BIT(28)
941 #define AR71XX_SPI_FS_GPIO BIT(0)
943 #define AR71XX_SPI_CTRL_RD BIT(6)
946 #define AR71XX_SPI_IOC_DO BIT(0)
947 #define AR71XX_SPI_IOC_CLK BIT(8)
948 #define AR71XX_SPI_IOC_CS(n) BIT(16 + (n))
1005 #define AR71XX_GPIO_FUNC_STEREO_EN BIT(17)
1006 #define AR71XX_GPIO_FUNC_SLIC_EN BIT(16)
1007 #define AR71XX_GPIO_FUNC_SPI_CS2_EN BIT(13)
1008 #define AR71XX_GPIO_FUNC_SPI_CS1_EN BIT(12)
1009 #define AR71XX_GPIO_FUNC_UART_EN BIT(8)
1010 #define AR71XX_GPIO_FUNC_USB_OC_EN BIT(4)
1011 #define AR71XX_GPIO_FUNC_USB_CLK_EN BIT(0)
1013 #define AR724X_GPIO_FUNC_GE0_MII_CLK_EN BIT(19)
1014 #define AR724X_GPIO_FUNC_SPI_EN BIT(18)
1015 #define AR724X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
1016 #define AR724X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
1017 #define AR724X_GPIO_FUNC_CLK_OBS5_EN BIT(12)
1018 #define AR724X_GPIO_FUNC_CLK_OBS4_EN BIT(11)
1019 #define AR724X_GPIO_FUNC_CLK_OBS3_EN BIT(10)
1020 #define AR724X_GPIO_FUNC_CLK_OBS2_EN BIT(9)
1021 #define AR724X_GPIO_FUNC_CLK_OBS1_EN BIT(8)
1022 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
1023 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
1024 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
1025 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
1026 #define AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
1027 #define AR724X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
1028 #define AR724X_GPIO_FUNC_UART_EN BIT(1)
1029 #define AR724X_GPIO_FUNC_JTAG_DISABLE BIT(0)
1031 #define AR913X_GPIO_FUNC_WMAC_LED_EN BIT(22)
1032 #define AR913X_GPIO_FUNC_EXP_PORT_CS_EN BIT(21)
1033 #define AR913X_GPIO_FUNC_I2S_REFCLKEN BIT(20)
1034 #define AR913X_GPIO_FUNC_I2S_MCKEN BIT(19)
1035 #define AR913X_GPIO_FUNC_I2S1_EN BIT(18)
1036 #define AR913X_GPIO_FUNC_I2S0_EN BIT(17)
1037 #define AR913X_GPIO_FUNC_SLIC_EN BIT(16)
1038 #define AR913X_GPIO_FUNC_UART_RTSCTS_EN BIT(9)
1039 #define AR913X_GPIO_FUNC_UART_EN BIT(8)
1040 #define AR913X_GPIO_FUNC_USB_CLK_EN BIT(4)
1042 #define AR933X_GPIO(x) BIT(x)
1043 #define AR933X_GPIO_FUNC_SPDIF2TCK BIT(31)
1044 #define AR933X_GPIO_FUNC_SPDIF_EN BIT(30)
1045 #define AR933X_GPIO_FUNC_I2SO_22_18_EN BIT(29)
1046 #define AR933X_GPIO_FUNC_I2S_MCK_EN BIT(27)
1047 #define AR933X_GPIO_FUNC_I2SO_EN BIT(26)
1048 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED_DUPL BIT(25)
1049 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED_COLL BIT(24)
1050 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED_ACT BIT(23)
1051 #define AR933X_GPIO_FUNC_SPI_EN BIT(18)
1052 #define AR933X_GPIO_FUNC_RES_TRUE BIT(15)
1053 #define AR933X_GPIO_FUNC_SPI_CS_EN2 BIT(14)
1054 #define AR933X_GPIO_FUNC_SPI_CS_EN1 BIT(13)
1055 #define AR933X_GPIO_FUNC_XLNA_EN BIT(12)
1056 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN BIT(7)
1057 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN BIT(6)
1058 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN BIT(5)
1059 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN BIT(4)
1060 #define AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN BIT(3)
1061 #define AR933X_GPIO_FUNC_UART_RTS_CTS_EN BIT(2)
1062 #define AR933X_GPIO_FUNC_UART_EN BIT(1)
1063 #define AR933X_GPIO_FUNC_JTAG_DISABLE BIT(0)
1065 #define AR934X_GPIO_FUNC_CLK_OBS7_EN BIT(9)
1066 #define AR934X_GPIO_FUNC_CLK_OBS6_EN BIT(8)
1067 #define AR934X_GPIO_FUNC_CLK_OBS5_EN BIT(7)
1068 #define AR934X_GPIO_FUNC_CLK_OBS4_EN BIT(6)
1069 #define AR934X_GPIO_FUNC_CLK_OBS3_EN BIT(5)
1070 #define AR934X_GPIO_FUNC_CLK_OBS2_EN BIT(4)
1071 #define AR934X_GPIO_FUNC_CLK_OBS1_EN BIT(3)
1072 #define AR934X_GPIO_FUNC_CLK_OBS0_EN BIT(2)
1073 #define AR934X_GPIO_FUNC_JTAG_DISABLE BIT(1)
1085 #define QCA953X_GPIO(x) BIT(x)
1107 #define AR7241_GPIO_COUNT 20
1139 #define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30)
1169 #define QCA953X_SRIF_DPLL2_LOCAL_PLL BIT(30)
1177 #define QCA953X_SRIF_DPLL2_PWD BIT(22)
1208 #define AR933X_ETH_CFG_RGMII_GE0 BIT(0)
1209 #define AR933X_ETH_CFG_MII_GE0 BIT(1)
1210 #define AR933X_ETH_CFG_GMII_GE0 BIT(2)
1211 #define AR933X_ETH_CFG_MII_GE0_MASTER BIT(3)
1212 #define AR933X_ETH_CFG_MII_GE0_SLAVE BIT(4)
1213 #define AR933X_ETH_CFG_MII_GE0_ERR_EN BIT(5)
1214 #define AR933X_ETH_CFG_SW_PHY_SWAP BIT(7)
1215 #define AR933X_ETH_CFG_SW_PHY_ADDR_SWAP BIT(8)
1216 #define AR933X_ETH_CFG_RMII_GE0 BIT(9)
1218 #define AR933X_ETH_CFG_RMII_GE0_SPD_100 BIT(10)
1225 #define AR934X_ETH_CFG_RGMII_GMAC0 BIT(0)
1226 #define AR934X_ETH_CFG_MII_GMAC0 BIT(1)
1227 #define AR934X_ETH_CFG_GMII_GMAC0 BIT(2)
1228 #define AR934X_ETH_CFG_MII_GMAC0_MASTER BIT(3)
1229 #define AR934X_ETH_CFG_MII_GMAC0_SLAVE BIT(4)
1230 #define AR934X_ETH_CFG_MII_GMAC0_ERR_EN BIT(5)
1231 #define AR934X_ETH_CFG_SW_ONLY_MODE BIT(6)
1232 #define AR934X_ETH_CFG_SW_PHY_SWAP BIT(7)
1233 #define AR934X_ETH_CFG_SW_APB_ACCESS BIT(9)
1234 #define AR934X_ETH_CFG_RMII_GMAC0 BIT(10)
1235 #define AR933X_ETH_CFG_MII_CNTL_SPEED BIT(11)
1236 #define AR934X_ETH_CFG_RMII_GMAC0_MASTER BIT(12)
1237 #define AR933X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
1238 #define AR934X_ETH_CFG_RXD_DELAY BIT(14)
1241 #define AR934X_ETH_CFG_RDV_DELAY BIT(16)
1250 #define QCA953X_ETH_CFG_SW_ONLY_MODE BIT(6)
1251 #define QCA953X_ETH_CFG_SW_PHY_SWAP BIT(7)
1252 #define QCA953X_ETH_CFG_SW_APB_ACCESS BIT(9)
1253 #define QCA953X_ETH_CFG_SW_ACC_MSB_FIRST BIT(13)
1261 #define QCA955X_ETH_CFG_RGMII_EN BIT(0)
1262 #define QCA955X_ETH_CFG_GE0_SGMII BIT(6)