183d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2b3dbf4a5SMacpaul Lin /* 3b3dbf4a5SMacpaul Lin * Faraday FTGMAC100 Ethernet 4b3dbf4a5SMacpaul Lin * 5b3dbf4a5SMacpaul Lin * (C) Copyright 2010 Faraday Technology 6b3dbf4a5SMacpaul Lin * Po-Yu Chuang <ratbert@faraday-tech.com> 7b3dbf4a5SMacpaul Lin * 8b3dbf4a5SMacpaul Lin * (C) Copyright 2010 Andes Technology 9b3dbf4a5SMacpaul Lin * Macpaul Lin <macpaul@andestech.com> 10b3dbf4a5SMacpaul Lin */ 11b3dbf4a5SMacpaul Lin 12b3dbf4a5SMacpaul Lin #ifndef __FTGMAC100_H 13b3dbf4a5SMacpaul Lin #define __FTGMAC100_H 14b3dbf4a5SMacpaul Lin 15b3dbf4a5SMacpaul Lin /* The registers offset table of ftgmac100 */ 16b3dbf4a5SMacpaul Lin struct ftgmac100 { 17b3dbf4a5SMacpaul Lin unsigned int isr; /* 0x00 */ 18b3dbf4a5SMacpaul Lin unsigned int ier; /* 0x04 */ 19b3dbf4a5SMacpaul Lin unsigned int mac_madr; /* 0x08 */ 20b3dbf4a5SMacpaul Lin unsigned int mac_ladr; /* 0x0c */ 21b3dbf4a5SMacpaul Lin unsigned int maht0; /* 0x10 */ 22b3dbf4a5SMacpaul Lin unsigned int maht1; /* 0x14 */ 23b3dbf4a5SMacpaul Lin unsigned int txpd; /* 0x18 */ 24b3dbf4a5SMacpaul Lin unsigned int rxpd; /* 0x1c */ 25b3dbf4a5SMacpaul Lin unsigned int txr_badr; /* 0x20 */ 26b3dbf4a5SMacpaul Lin unsigned int rxr_badr; /* 0x24 */ 27b3dbf4a5SMacpaul Lin unsigned int hptxpd; /* 0x28 */ 28b3dbf4a5SMacpaul Lin unsigned int hptxpd_badr; /* 0x2c */ 29b3dbf4a5SMacpaul Lin unsigned int itc; /* 0x30 */ 30b3dbf4a5SMacpaul Lin unsigned int aptc; /* 0x34 */ 31b3dbf4a5SMacpaul Lin unsigned int dblac; /* 0x38 */ 32b3dbf4a5SMacpaul Lin unsigned int dmafifos; /* 0x3c */ 33b3dbf4a5SMacpaul Lin unsigned int revr; /* 0x40 */ 34b3dbf4a5SMacpaul Lin unsigned int fear; /* 0x44 */ 35b3dbf4a5SMacpaul Lin unsigned int tpafcr; /* 0x48 */ 36b3dbf4a5SMacpaul Lin unsigned int rbsr; /* 0x4c */ 37b3dbf4a5SMacpaul Lin unsigned int maccr; /* 0x50 */ 38b3dbf4a5SMacpaul Lin unsigned int macsr; /* 0x54 */ 39b3dbf4a5SMacpaul Lin unsigned int tm; /* 0x58 */ 40b3dbf4a5SMacpaul Lin unsigned int resv1; /* 0x5c */ /* not defined in spec */ 41b3dbf4a5SMacpaul Lin unsigned int phycr; /* 0x60 */ 42b3dbf4a5SMacpaul Lin unsigned int phydata; /* 0x64 */ 43b3dbf4a5SMacpaul Lin unsigned int fcr; /* 0x68 */ 44b3dbf4a5SMacpaul Lin unsigned int bpr; /* 0x6c */ 45b3dbf4a5SMacpaul Lin unsigned int wolcr; /* 0x70 */ 46b3dbf4a5SMacpaul Lin unsigned int wolsr; /* 0x74 */ 47b3dbf4a5SMacpaul Lin unsigned int wfcrc; /* 0x78 */ 48b3dbf4a5SMacpaul Lin unsigned int resv2; /* 0x7c */ /* not defined in spec */ 49b3dbf4a5SMacpaul Lin unsigned int wfbm1; /* 0x80 */ 50b3dbf4a5SMacpaul Lin unsigned int wfbm2; /* 0x84 */ 51b3dbf4a5SMacpaul Lin unsigned int wfbm3; /* 0x88 */ 52b3dbf4a5SMacpaul Lin unsigned int wfbm4; /* 0x8c */ 53b3dbf4a5SMacpaul Lin unsigned int nptxr_ptr; /* 0x90 */ 54b3dbf4a5SMacpaul Lin unsigned int hptxr_ptr; /* 0x94 */ 55b3dbf4a5SMacpaul Lin unsigned int rxr_ptr; /* 0x98 */ 56b3dbf4a5SMacpaul Lin unsigned int resv3; /* 0x9c */ /* not defined in spec */ 57b3dbf4a5SMacpaul Lin unsigned int tx; /* 0xa0 */ 58b3dbf4a5SMacpaul Lin unsigned int tx_mcol_scol; /* 0xa4 */ 59b3dbf4a5SMacpaul Lin unsigned int tx_ecol_fail; /* 0xa8 */ 60b3dbf4a5SMacpaul Lin unsigned int tx_lcol_und; /* 0xac */ 61b3dbf4a5SMacpaul Lin unsigned int rx; /* 0xb0 */ 62b3dbf4a5SMacpaul Lin unsigned int rx_bc; /* 0xb4 */ 63b3dbf4a5SMacpaul Lin unsigned int rx_mc; /* 0xb8 */ 64b3dbf4a5SMacpaul Lin unsigned int rx_pf_aep; /* 0xbc */ 65b3dbf4a5SMacpaul Lin unsigned int rx_runt; /* 0xc0 */ 66b3dbf4a5SMacpaul Lin unsigned int rx_crcer_ftl; /* 0xc4 */ 67b3dbf4a5SMacpaul Lin unsigned int rx_col_lost; /* 0xc8 */ 68b3dbf4a5SMacpaul Lin }; 69b3dbf4a5SMacpaul Lin 70b3dbf4a5SMacpaul Lin /* 71b3dbf4a5SMacpaul Lin * Interrupt status register & interrupt enable register 72b3dbf4a5SMacpaul Lin */ 73f72b4a3dSCédric Le Goater #define FTGMAC100_INT_RPKT_BUF BIT(0) 74f72b4a3dSCédric Le Goater #define FTGMAC100_INT_RPKT_FIFO BIT(1) 75f72b4a3dSCédric Le Goater #define FTGMAC100_INT_NO_RXBUF BIT(2) 76f72b4a3dSCédric Le Goater #define FTGMAC100_INT_RPKT_LOST BIT(3) 77f72b4a3dSCédric Le Goater #define FTGMAC100_INT_XPKT_ETH BIT(4) 78f72b4a3dSCédric Le Goater #define FTGMAC100_INT_XPKT_FIFO BIT(5) 79f72b4a3dSCédric Le Goater #define FTGMAC100_INT_NO_NPTXBUF BIT(6) 80f72b4a3dSCédric Le Goater #define FTGMAC100_INT_XPKT_LOST BIT(7) 81f72b4a3dSCédric Le Goater #define FTGMAC100_INT_AHB_ERR BIT(8) 82f72b4a3dSCédric Le Goater #define FTGMAC100_INT_PHYSTS_CHG BIT(9) 83f72b4a3dSCédric Le Goater #define FTGMAC100_INT_NO_HPTXBUF BIT(10) 84b3dbf4a5SMacpaul Lin 85b3dbf4a5SMacpaul Lin /* 86b3dbf4a5SMacpaul Lin * Interrupt timer control register 87b3dbf4a5SMacpaul Lin */ 88b3dbf4a5SMacpaul Lin #define FTGMAC100_ITC_RXINT_CNT(x) (((x) & 0xf) << 0) 89b3dbf4a5SMacpaul Lin #define FTGMAC100_ITC_RXINT_THR(x) (((x) & 0x7) << 4) 90f72b4a3dSCédric Le Goater #define FTGMAC100_ITC_RXINT_TIME_SEL BIT(7) 91b3dbf4a5SMacpaul Lin #define FTGMAC100_ITC_TXINT_CNT(x) (((x) & 0xf) << 8) 92b3dbf4a5SMacpaul Lin #define FTGMAC100_ITC_TXINT_THR(x) (((x) & 0x7) << 12) 93f72b4a3dSCédric Le Goater #define FTGMAC100_ITC_TXINT_TIME_SEL BIT(15) 94b3dbf4a5SMacpaul Lin 95b3dbf4a5SMacpaul Lin /* 96b3dbf4a5SMacpaul Lin * Automatic polling timer control register 97b3dbf4a5SMacpaul Lin */ 98b3dbf4a5SMacpaul Lin #define FTGMAC100_APTC_RXPOLL_CNT(x) (((x) & 0xf) << 0) 99f72b4a3dSCédric Le Goater #define FTGMAC100_APTC_RXPOLL_TIME_SEL BIT(4) 100b3dbf4a5SMacpaul Lin #define FTGMAC100_APTC_TXPOLL_CNT(x) (((x) & 0xf) << 8) 101f72b4a3dSCédric Le Goater #define FTGMAC100_APTC_TXPOLL_TIME_SEL BIT(12) 102b3dbf4a5SMacpaul Lin 103b3dbf4a5SMacpaul Lin /* 104b3dbf4a5SMacpaul Lin * DMA burst length and arbitration control register 105b3dbf4a5SMacpaul Lin */ 106b3dbf4a5SMacpaul Lin #define FTGMAC100_DBLAC_RXFIFO_LTHR(x) (((x) & 0x7) << 0) 107b3dbf4a5SMacpaul Lin #define FTGMAC100_DBLAC_RXFIFO_HTHR(x) (((x) & 0x7) << 3) 108f72b4a3dSCédric Le Goater #define FTGMAC100_DBLAC_RX_THR_EN BIT(6) 109b3dbf4a5SMacpaul Lin #define FTGMAC100_DBLAC_RXBURST_SIZE(x) (((x) & 0x3) << 8) 110b3dbf4a5SMacpaul Lin #define FTGMAC100_DBLAC_TXBURST_SIZE(x) (((x) & 0x3) << 10) 111b3dbf4a5SMacpaul Lin #define FTGMAC100_DBLAC_RXDES_SIZE(x) (((x) & 0xf) << 12) 112b3dbf4a5SMacpaul Lin #define FTGMAC100_DBLAC_TXDES_SIZE(x) (((x) & 0xf) << 16) 113b3dbf4a5SMacpaul Lin #define FTGMAC100_DBLAC_IFG_CNT(x) (((x) & 0x7) << 20) 114f72b4a3dSCédric Le Goater #define FTGMAC100_DBLAC_IFG_INC BIT(23) 115b3dbf4a5SMacpaul Lin 116b3dbf4a5SMacpaul Lin /* 117b3dbf4a5SMacpaul Lin * DMA FIFO status register 118b3dbf4a5SMacpaul Lin */ 119b3dbf4a5SMacpaul Lin #define FTGMAC100_DMAFIFOS_RXDMA1_SM(dmafifos) ((dmafifos) & 0xf) 120b3dbf4a5SMacpaul Lin #define FTGMAC100_DMAFIFOS_RXDMA2_SM(dmafifos) (((dmafifos) >> 4) & 0xf) 121b3dbf4a5SMacpaul Lin #define FTGMAC100_DMAFIFOS_RXDMA3_SM(dmafifos) (((dmafifos) >> 8) & 0x7) 122b3dbf4a5SMacpaul Lin #define FTGMAC100_DMAFIFOS_TXDMA1_SM(dmafifos) (((dmafifos) >> 12) & 0xf) 123b3dbf4a5SMacpaul Lin #define FTGMAC100_DMAFIFOS_TXDMA2_SM(dmafifos) (((dmafifos) >> 16) & 0x3) 124b3dbf4a5SMacpaul Lin #define FTGMAC100_DMAFIFOS_TXDMA3_SM(dmafifos) (((dmafifos) >> 18) & 0xf) 125f72b4a3dSCédric Le Goater #define FTGMAC100_DMAFIFOS_RXFIFO_EMPTY BIT(26) 126f72b4a3dSCédric Le Goater #define FTGMAC100_DMAFIFOS_TXFIFO_EMPTY BIT(27) 127f72b4a3dSCédric Le Goater #define FTGMAC100_DMAFIFOS_RXDMA_GRANT BIT(28) 128f72b4a3dSCédric Le Goater #define FTGMAC100_DMAFIFOS_TXDMA_GRANT BIT(29) 129f72b4a3dSCédric Le Goater #define FTGMAC100_DMAFIFOS_RXDMA_REQ BIT(30) 130f72b4a3dSCédric Le Goater #define FTGMAC100_DMAFIFOS_TXDMA_REQ BIT(31) 131b3dbf4a5SMacpaul Lin 132b3dbf4a5SMacpaul Lin /* 133b3dbf4a5SMacpaul Lin * Receive buffer size register 134b3dbf4a5SMacpaul Lin */ 135b3dbf4a5SMacpaul Lin #define FTGMAC100_RBSR_SIZE(x) ((x) & 0x3fff) 136b3dbf4a5SMacpaul Lin 137b3dbf4a5SMacpaul Lin /* 138b3dbf4a5SMacpaul Lin * MAC control register 139b3dbf4a5SMacpaul Lin */ 140f72b4a3dSCédric Le Goater #define FTGMAC100_MACCR_TXDMA_EN BIT(0) 141f72b4a3dSCédric Le Goater #define FTGMAC100_MACCR_RXDMA_EN BIT(1) 142f72b4a3dSCédric Le Goater #define FTGMAC100_MACCR_TXMAC_EN BIT(2) 143f72b4a3dSCédric Le Goater #define FTGMAC100_MACCR_RXMAC_EN BIT(3) 144f72b4a3dSCédric Le Goater #define FTGMAC100_MACCR_RM_VLAN BIT(4) 145f72b4a3dSCédric Le Goater #define FTGMAC100_MACCR_HPTXR_EN BIT(5) 146f72b4a3dSCédric Le Goater #define FTGMAC100_MACCR_LOOP_EN BIT(6) 147f72b4a3dSCédric Le Goater #define FTGMAC100_MACCR_ENRX_IN_HALFTX BIT(7) 148f72b4a3dSCédric Le Goater #define FTGMAC100_MACCR_FULLDUP BIT(8) 149f72b4a3dSCédric Le Goater #define FTGMAC100_MACCR_GIGA_MODE BIT(9) 150f72b4a3dSCédric Le Goater #define FTGMAC100_MACCR_CRC_APD BIT(10) 151f72b4a3dSCédric Le Goater #define FTGMAC100_MACCR_RX_RUNT BIT(12) 152f72b4a3dSCédric Le Goater #define FTGMAC100_MACCR_JUMBO_LF BIT(13) 153f72b4a3dSCédric Le Goater #define FTGMAC100_MACCR_RX_ALL BIT(14) 154f72b4a3dSCédric Le Goater #define FTGMAC100_MACCR_HT_MULTI_EN BIT(15) 155f72b4a3dSCédric Le Goater #define FTGMAC100_MACCR_RX_MULTIPKT BIT(16) 156f72b4a3dSCédric Le Goater #define FTGMAC100_MACCR_RX_BROADPKT BIT(17) 157f72b4a3dSCédric Le Goater #define FTGMAC100_MACCR_DISCARD_CRCERR BIT(18) 158f72b4a3dSCédric Le Goater #define FTGMAC100_MACCR_FAST_MODE BIT(19) 159f72b4a3dSCédric Le Goater #define FTGMAC100_MACCR_SW_RST BIT(31) 160b3dbf4a5SMacpaul Lin 161b3dbf4a5SMacpaul Lin /* 162b3dbf4a5SMacpaul Lin * PHY control register 163b3dbf4a5SMacpaul Lin */ 164b3dbf4a5SMacpaul Lin #define FTGMAC100_PHYCR_MDC_CYCTHR_MASK 0x3f 165b3dbf4a5SMacpaul Lin #define FTGMAC100_PHYCR_MDC_CYCTHR(x) ((x) & 0x3f) 166b3dbf4a5SMacpaul Lin #define FTGMAC100_PHYCR_PHYAD(x) (((x) & 0x1f) << 16) 167b3dbf4a5SMacpaul Lin #define FTGMAC100_PHYCR_REGAD(x) (((x) & 0x1f) << 21) 168f72b4a3dSCédric Le Goater #define FTGMAC100_PHYCR_MIIRD BIT(26) 169f72b4a3dSCédric Le Goater #define FTGMAC100_PHYCR_MIIWR BIT(27) 170b3dbf4a5SMacpaul Lin 171b3dbf4a5SMacpaul Lin /* 172b3dbf4a5SMacpaul Lin * PHY data register 173b3dbf4a5SMacpaul Lin */ 174b3dbf4a5SMacpaul Lin #define FTGMAC100_PHYDATA_MIIWDATA(x) ((x) & 0xffff) 175b3dbf4a5SMacpaul Lin #define FTGMAC100_PHYDATA_MIIRDATA(phydata) (((phydata) >> 16) & 0xffff) 176b3dbf4a5SMacpaul Lin 177b3dbf4a5SMacpaul Lin /* 178b3dbf4a5SMacpaul Lin * Transmit descriptor, aligned to 16 bytes 179b3dbf4a5SMacpaul Lin */ 180*813df3e2SChia-Wei, Wang 181*813df3e2SChia-Wei, Wang #ifndef CONFIG_SYS_DCACHE_OFF 182*813df3e2SChia-Wei, Wang struct ftgmac100_txdes { 183*813df3e2SChia-Wei, Wang unsigned int txdes0; 184*813df3e2SChia-Wei, Wang unsigned int txdes1; 185*813df3e2SChia-Wei, Wang unsigned int txdes2; /* not used by HW */ 186*813df3e2SChia-Wei, Wang unsigned int txdes3; /* TXBUF_BADR */ 187*813df3e2SChia-Wei, Wang } __aligned(CONFIG_SYS_CACHELINE_SIZE); 188*813df3e2SChia-Wei, Wang #else 189b3dbf4a5SMacpaul Lin struct ftgmac100_txdes { 190b3dbf4a5SMacpaul Lin unsigned int txdes0; 191b3dbf4a5SMacpaul Lin unsigned int txdes1; 192b3dbf4a5SMacpaul Lin unsigned int txdes2; /* not used by HW */ 193b3dbf4a5SMacpaul Lin unsigned int txdes3; /* TXBUF_BADR */ 1943bd79635SCédric Le Goater } __aligned(16); 195*813df3e2SChia-Wei, Wang #endif 196b3dbf4a5SMacpaul Lin 197b3dbf4a5SMacpaul Lin #define FTGMAC100_TXDES0_TXBUF_SIZE(x) ((x) & 0x3fff) 198f72b4a3dSCédric Le Goater #define FTGMAC100_TXDES0_EDOTR BIT(15) 199f72b4a3dSCédric Le Goater #define FTGMAC100_TXDES0_CRC_ERR BIT(19) 200f72b4a3dSCédric Le Goater #define FTGMAC100_TXDES0_LTS BIT(28) 201f72b4a3dSCédric Le Goater #define FTGMAC100_TXDES0_FTS BIT(29) 202f72b4a3dSCédric Le Goater #define FTGMAC100_TXDES0_TXDMA_OWN BIT(31) 203b3dbf4a5SMacpaul Lin 204b3dbf4a5SMacpaul Lin #define FTGMAC100_TXDES1_VLANTAG_CI(x) ((x) & 0xffff) 205f72b4a3dSCédric Le Goater #define FTGMAC100_TXDES1_INS_VLANTAG BIT(16) 206f72b4a3dSCédric Le Goater #define FTGMAC100_TXDES1_TCP_CHKSUM BIT(17) 207f72b4a3dSCédric Le Goater #define FTGMAC100_TXDES1_UDP_CHKSUM BIT(18) 208f72b4a3dSCédric Le Goater #define FTGMAC100_TXDES1_IP_CHKSUM BIT(19) 209f72b4a3dSCédric Le Goater #define FTGMAC100_TXDES1_LLC BIT(22) 210f72b4a3dSCédric Le Goater #define FTGMAC100_TXDES1_TX2FIC BIT(30) 211f72b4a3dSCédric Le Goater #define FTGMAC100_TXDES1_TXIC BIT(31) 212b3dbf4a5SMacpaul Lin 213b3dbf4a5SMacpaul Lin /* 214b3dbf4a5SMacpaul Lin * Receive descriptor, aligned to 16 bytes 215b3dbf4a5SMacpaul Lin */ 216*813df3e2SChia-Wei, Wang #ifndef CONFIG_SYS_DCACHE_OFF 217*813df3e2SChia-Wei, Wang struct ftgmac100_rxdes { 218*813df3e2SChia-Wei, Wang unsigned int rxdes0; 219*813df3e2SChia-Wei, Wang unsigned int rxdes1; 220*813df3e2SChia-Wei, Wang unsigned int rxdes2; /* not used by HW */ 221*813df3e2SChia-Wei, Wang unsigned int rxdes3; /* RXBUF_BADR */ 222*813df3e2SChia-Wei, Wang } __aligned(CONFIG_SYS_CACHELINE_SIZE); 223*813df3e2SChia-Wei, Wang #else 224b3dbf4a5SMacpaul Lin struct ftgmac100_rxdes { 225b3dbf4a5SMacpaul Lin unsigned int rxdes0; 226b3dbf4a5SMacpaul Lin unsigned int rxdes1; 227b3dbf4a5SMacpaul Lin unsigned int rxdes2; /* not used by HW */ 228b3dbf4a5SMacpaul Lin unsigned int rxdes3; /* RXBUF_BADR */ 2293bd79635SCédric Le Goater } __aligned(16); 230*813df3e2SChia-Wei, Wang #endif 231b3dbf4a5SMacpaul Lin 232b3dbf4a5SMacpaul Lin #define FTGMAC100_RXDES0_VDBC(x) ((x) & 0x3fff) 233f72b4a3dSCédric Le Goater #define FTGMAC100_RXDES0_EDORR BIT(15) 234f72b4a3dSCédric Le Goater #define FTGMAC100_RXDES0_MULTICAST BIT(16) 235f72b4a3dSCédric Le Goater #define FTGMAC100_RXDES0_BROADCAST BIT(17) 236f72b4a3dSCédric Le Goater #define FTGMAC100_RXDES0_RX_ERR BIT(18) 237f72b4a3dSCédric Le Goater #define FTGMAC100_RXDES0_CRC_ERR BIT(19) 238f72b4a3dSCédric Le Goater #define FTGMAC100_RXDES0_FTL BIT(20) 239f72b4a3dSCédric Le Goater #define FTGMAC100_RXDES0_RUNT BIT(21) 240f72b4a3dSCédric Le Goater #define FTGMAC100_RXDES0_RX_ODD_NB BIT(22) 241f72b4a3dSCédric Le Goater #define FTGMAC100_RXDES0_FIFO_FULL BIT(23) 242f72b4a3dSCédric Le Goater #define FTGMAC100_RXDES0_PAUSE_OPCODE BIT(24) 243f72b4a3dSCédric Le Goater #define FTGMAC100_RXDES0_PAUSE_FRAME BIT(25) 244f72b4a3dSCédric Le Goater #define FTGMAC100_RXDES0_LRS BIT(28) 245f72b4a3dSCédric Le Goater #define FTGMAC100_RXDES0_FRS BIT(29) 246f72b4a3dSCédric Le Goater #define FTGMAC100_RXDES0_RXPKT_RDY BIT(31) 247b3dbf4a5SMacpaul Lin 248b3dbf4a5SMacpaul Lin #define FTGMAC100_RXDES1_VLANTAG_CI 0xffff 249b3dbf4a5SMacpaul Lin #define FTGMAC100_RXDES1_PROT_MASK (0x3 << 20) 250b3dbf4a5SMacpaul Lin #define FTGMAC100_RXDES1_PROT_NONIP (0x0 << 20) 251b3dbf4a5SMacpaul Lin #define FTGMAC100_RXDES1_PROT_IP (0x1 << 20) 252b3dbf4a5SMacpaul Lin #define FTGMAC100_RXDES1_PROT_TCPIP (0x2 << 20) 253b3dbf4a5SMacpaul Lin #define FTGMAC100_RXDES1_PROT_UDPIP (0x3 << 20) 254f72b4a3dSCédric Le Goater #define FTGMAC100_RXDES1_LLC BIT(22) 255f72b4a3dSCédric Le Goater #define FTGMAC100_RXDES1_DF BIT(23) 256f72b4a3dSCédric Le Goater #define FTGMAC100_RXDES1_VLANTAG_AVAIL BIT(24) 257f72b4a3dSCédric Le Goater #define FTGMAC100_RXDES1_TCP_CHKSUM_ERR BIT(25) 258f72b4a3dSCédric Le Goater #define FTGMAC100_RXDES1_UDP_CHKSUM_ERR BIT(26) 259f72b4a3dSCédric Le Goater #define FTGMAC100_RXDES1_IP_CHKSUM_ERR BIT(27) 260b3dbf4a5SMacpaul Lin 261b3dbf4a5SMacpaul Lin #endif /* __FTGMAC100_H */ 262