1*3bed4220SNeil Armstrong /* SPDX-License-Identifier: GPL-2.0 */ 2*3bed4220SNeil Armstrong /* 3*3bed4220SNeil Armstrong * Copyright (C) 2016 BayLibre, SAS 4*3bed4220SNeil Armstrong * Author: Neil Armstrong <narmstrong@baylibre.com> 5*3bed4220SNeil Armstrong * Copyright (C) 2015 Amlogic, Inc. All rights reserved. 6*3bed4220SNeil Armstrong */ 7*3bed4220SNeil Armstrong 8*3bed4220SNeil Armstrong #ifndef __MESON_DW_HDMI_H 9*3bed4220SNeil Armstrong #define __MESON_DW_HDMI_H 10*3bed4220SNeil Armstrong 11*3bed4220SNeil Armstrong /* 12*3bed4220SNeil Armstrong * Bit 7 RW Reserved. Default 1. 13*3bed4220SNeil Armstrong * Bit 6 RW Reserved. Default 1. 14*3bed4220SNeil Armstrong * Bit 5 RW Reserved. Default 1. 15*3bed4220SNeil Armstrong * Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset. 16*3bed4220SNeil Armstrong * Default 1. 17*3bed4220SNeil Armstrong * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset; 18*3bed4220SNeil Armstrong * 0=Release from reset. 19*3bed4220SNeil Armstrong * Default 1. 20*3bed4220SNeil Armstrong * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset. 21*3bed4220SNeil Armstrong * Default 1. 22*3bed4220SNeil Armstrong * Bit 1 RW sw_reset_rnd: random number interface to HDCP. 1=Apply reset; 23*3bed4220SNeil Armstrong * 0=Release from reset. Default 1. 24*3bed4220SNeil Armstrong * Bit 0 RW sw_reset_core: connects to IP's ~irstz. 1=Apply reset; 25*3bed4220SNeil Armstrong * 0=Release from reset. Default 1. 26*3bed4220SNeil Armstrong */ 27*3bed4220SNeil Armstrong #define HDMITX_TOP_SW_RESET (0x000) 28*3bed4220SNeil Armstrong 29*3bed4220SNeil Armstrong /* 30*3bed4220SNeil Armstrong * Bit 12 RW i2s_ws_inv:1=Invert i2s_ws; 0=No invert. Default 0. 31*3bed4220SNeil Armstrong * Bit 11 RW i2s_clk_inv: 1=Invert i2s_clk; 0=No invert. Default 0. 32*3bed4220SNeil Armstrong * Bit 10 RW spdif_clk_inv: 1=Invert spdif_clk; 0=No invert. Default 0. 33*3bed4220SNeil Armstrong * Bit 9 RW tmds_clk_inv: 1=Invert tmds_clk; 0=No invert. Default 0. 34*3bed4220SNeil Armstrong * Bit 8 RW pixel_clk_inv: 1=Invert pixel_clk; 0=No invert. Default 0. 35*3bed4220SNeil Armstrong * Bit 4 RW cec_clk_en: 1=enable cec_clk; 0=disable. Default 0. 36*3bed4220SNeil Armstrong * Bit 3 RW i2s_clk_en: 1=enable i2s_clk; 0=disable. Default 0. 37*3bed4220SNeil Armstrong * Bit 2 RW spdif_clk_en: 1=enable spdif_clk; 0=disable. Default 0. 38*3bed4220SNeil Armstrong * Bit 1 RW tmds_clk_en: 1=enable tmds_clk; 0=disable. Default 0. 39*3bed4220SNeil Armstrong * Bit 0 RW pixel_clk_en: 1=enable pixel_clk; 0=disable. Default 0. 40*3bed4220SNeil Armstrong */ 41*3bed4220SNeil Armstrong #define HDMITX_TOP_CLK_CNTL (0x001) 42*3bed4220SNeil Armstrong 43*3bed4220SNeil Armstrong /* 44*3bed4220SNeil Armstrong * Bit 11: 0 RW hpd_valid_width: filter out width <= M*1024. Default 0. 45*3bed4220SNeil Armstrong * Bit 15:12 RW hpd_glitch_width: filter out glitch <= N. Default 0. 46*3bed4220SNeil Armstrong */ 47*3bed4220SNeil Armstrong #define HDMITX_TOP_HPD_FILTER (0x002) 48*3bed4220SNeil Armstrong 49*3bed4220SNeil Armstrong /* 50*3bed4220SNeil Armstrong * intr_maskn: MASK_N, one bit per interrupt source. 51*3bed4220SNeil Armstrong * 1=Enable interrupt source; 0=Disable interrupt source. Default 0. 52*3bed4220SNeil Armstrong * [ 4] hdcp22_rndnum_err 53*3bed4220SNeil Armstrong * [ 3] nonce_rfrsh_rise 54*3bed4220SNeil Armstrong * [ 2] hpd_fall_intr 55*3bed4220SNeil Armstrong * [ 1] hpd_rise_intr 56*3bed4220SNeil Armstrong * [ 0] core_intr 57*3bed4220SNeil Armstrong */ 58*3bed4220SNeil Armstrong #define HDMITX_TOP_INTR_MASKN (0x003) 59*3bed4220SNeil Armstrong 60*3bed4220SNeil Armstrong /* 61*3bed4220SNeil Armstrong * Bit 30: 0 RW intr_stat: For each bit, write 1 to manually set the interrupt 62*3bed4220SNeil Armstrong * bit, read back the interrupt status. 63*3bed4220SNeil Armstrong * Bit 31 R IP interrupt status 64*3bed4220SNeil Armstrong * Bit 2 RW hpd_fall 65*3bed4220SNeil Armstrong * Bit 1 RW hpd_rise 66*3bed4220SNeil Armstrong * Bit 0 RW IP interrupt 67*3bed4220SNeil Armstrong */ 68*3bed4220SNeil Armstrong #define HDMITX_TOP_INTR_STAT (0x004) 69*3bed4220SNeil Armstrong 70*3bed4220SNeil Armstrong /* 71*3bed4220SNeil Armstrong * [4] hdcp22_rndnum_err 72*3bed4220SNeil Armstrong * [3] nonce_rfrsh_rise 73*3bed4220SNeil Armstrong * [2] hpd_fall 74*3bed4220SNeil Armstrong * [1] hpd_rise 75*3bed4220SNeil Armstrong * [0] core_intr_rise 76*3bed4220SNeil Armstrong */ 77*3bed4220SNeil Armstrong #define HDMITX_TOP_INTR_STAT_CLR (0x005) 78*3bed4220SNeil Armstrong 79*3bed4220SNeil Armstrong #define HDMITX_TOP_INTR_CORE BIT(0) 80*3bed4220SNeil Armstrong #define HDMITX_TOP_INTR_HPD_RISE BIT(1) 81*3bed4220SNeil Armstrong #define HDMITX_TOP_INTR_HPD_FALL BIT(2) 82*3bed4220SNeil Armstrong 83*3bed4220SNeil Armstrong /* Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data; 84*3bed4220SNeil Armstrong * 3'b010=Output PRBS data; 3'b100=Output shift pattern. Default 0. 85*3bed4220SNeil Armstrong * Bit 11: 9 RW shift_pttn_repeat: 0=New pattern every clk cycle; 1=New pattern 86*3bed4220SNeil Armstrong * every 2 clk cycles; ...; 7=New pattern every 8 clk cycles. Default 0. 87*3bed4220SNeil Armstrong * Bit 8 RW shift_pttn_en: 1= Enable shift pattern generator; 0=Disable. 88*3bed4220SNeil Armstrong * Default 0. 89*3bed4220SNeil Armstrong * Bit 4: 3 RW prbs_pttn_mode: 0=PRBS11; 1=PRBS15; 2=PRBS7; 3=PRBS31. Default 0. 90*3bed4220SNeil Armstrong * Bit 2: 1 RW prbs_pttn_width: 0=idle; 1=output 8-bit pattern; 91*3bed4220SNeil Armstrong * 2=Output 1-bit pattern; 3=output 10-bit pattern. Default 0. 92*3bed4220SNeil Armstrong * Bit 0 RW prbs_pttn_en: 1=Enable PRBS generator; 0=Disable. Default 0. 93*3bed4220SNeil Armstrong */ 94*3bed4220SNeil Armstrong #define HDMITX_TOP_BIST_CNTL (0x006) 95*3bed4220SNeil Armstrong 96*3bed4220SNeil Armstrong /* Bit 29:20 RW shift_pttn_data[59:50]. Default 0. */ 97*3bed4220SNeil Armstrong /* Bit 19:10 RW shift_pttn_data[69:60]. Default 0. */ 98*3bed4220SNeil Armstrong /* Bit 9: 0 RW shift_pttn_data[79:70]. Default 0. */ 99*3bed4220SNeil Armstrong #define HDMITX_TOP_SHIFT_PTTN_012 (0x007) 100*3bed4220SNeil Armstrong 101*3bed4220SNeil Armstrong /* Bit 29:20 RW shift_pttn_data[29:20]. Default 0. */ 102*3bed4220SNeil Armstrong /* Bit 19:10 RW shift_pttn_data[39:30]. Default 0. */ 103*3bed4220SNeil Armstrong /* Bit 9: 0 RW shift_pttn_data[49:40]. Default 0. */ 104*3bed4220SNeil Armstrong #define HDMITX_TOP_SHIFT_PTTN_345 (0x008) 105*3bed4220SNeil Armstrong 106*3bed4220SNeil Armstrong /* Bit 19:10 RW shift_pttn_data[ 9: 0]. Default 0. */ 107*3bed4220SNeil Armstrong /* Bit 9: 0 RW shift_pttn_data[19:10]. Default 0. */ 108*3bed4220SNeil Armstrong #define HDMITX_TOP_SHIFT_PTTN_67 (0x009) 109*3bed4220SNeil Armstrong 110*3bed4220SNeil Armstrong /* Bit 25:16 RW tmds_clk_pttn[19:10]. Default 0. */ 111*3bed4220SNeil Armstrong /* Bit 9: 0 RW tmds_clk_pttn[ 9: 0]. Default 0. */ 112*3bed4220SNeil Armstrong #define HDMITX_TOP_TMDS_CLK_PTTN_01 (0x00A) 113*3bed4220SNeil Armstrong 114*3bed4220SNeil Armstrong /* Bit 25:16 RW tmds_clk_pttn[39:30]. Default 0. */ 115*3bed4220SNeil Armstrong /* Bit 9: 0 RW tmds_clk_pttn[29:20]. Default 0. */ 116*3bed4220SNeil Armstrong #define HDMITX_TOP_TMDS_CLK_PTTN_23 (0x00B) 117*3bed4220SNeil Armstrong 118*3bed4220SNeil Armstrong /* Bit 1 RW shift_tmds_clk_pttn:1=Enable shifting clk pattern, 119*3bed4220SNeil Armstrong * used when TMDS CLK rate = TMDS character rate /4. Default 0. 120*3bed4220SNeil Armstrong * Bit 0 R Reserved. Default 0. 121*3bed4220SNeil Armstrong * [ 1] shift_tmds_clk_pttn 122*3bed4220SNeil Armstrong * [ 0] load_tmds_clk_pttn 123*3bed4220SNeil Armstrong */ 124*3bed4220SNeil Armstrong #define HDMITX_TOP_TMDS_CLK_PTTN_CNTL (0x00C) 125*3bed4220SNeil Armstrong 126*3bed4220SNeil Armstrong /* Bit 0 RW revocmem_wr_fail: Read back 1 to indicate Host write REVOC MEM 127*3bed4220SNeil Armstrong * failure, write 1 to clear the failure flag. Default 0. 128*3bed4220SNeil Armstrong */ 129*3bed4220SNeil Armstrong #define HDMITX_TOP_REVOCMEM_STAT (0x00D) 130*3bed4220SNeil Armstrong 131*3bed4220SNeil Armstrong /* Bit 0 R filtered HPD status. */ 132*3bed4220SNeil Armstrong #define HDMITX_TOP_STAT0 (0x00E) 133*3bed4220SNeil Armstrong 134*3bed4220SNeil Armstrong #endif /* __MESON_DW_HDMI_H */ 135