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/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dnand_ids.c28 LEGACY_ID_NAND("NAND 1MiB 5V 8-bit", 0x6e, 1, SZ_4K, SP_OPTIONS),
29 LEGACY_ID_NAND("NAND 2MiB 5V 8-bit", 0x64, 2, SZ_4K, SP_OPTIONS),
30 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xe8, 1, SZ_4K, SP_OPTIONS),
31 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xec, 1, SZ_4K, SP_OPTIONS),
32 LEGACY_ID_NAND("NAND 2MiB 3,3V 8-bit", 0xea, 2, SZ_4K, SP_OPTIONS),
33 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS),
35 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xe6, 8, SZ_8K, SP_OPTIONS),
42 {"TC58NVG0S3E 1G 3.3V 8-bit",
46 {"TC58NVG2S0F 4G 3.3V 8-bit",
49 {"TC58NVG2S0H 4G 3.3V 8-bit",
[all …]
/openbmc/linux/drivers/mtd/nand/raw/
H A Dnand_ids.c1 // SPDX-License-Identifier: GPL-2.0-only
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
41 {"TC58NVG5D2 32G 3.3V 8-bit",
44 {"TC58NVG6D2 64G 3.3V 8-bit",
47 {"SDTNQGAMA 64G 3.3V 8-bit",
50 {"SDTNRGAMA 64G 3.3V 8-bit",
53 {"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
[all …]
/openbmc/linux/drivers/media/platform/ti/omap3isp/
H A Dispreg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * TI OMAP3 ISP - Registers definitions
48 #define ISPCCP2_SYSCONFIG_SOFT_RESET BIT(1)
58 #define ISPCCP2_SYSSTATUS_RESET_DONE BIT(0)
61 #define ISPCCP2_LC01_IRQSTATUS_LC0_FS_IRQ BIT(11)
62 #define ISPCCP2_LC01_IRQSTATUS_LC0_LE_IRQ BIT(10)
63 #define ISPCCP2_LC01_IRQSTATUS_LC0_LS_IRQ BIT(9)
64 #define ISPCCP2_LC01_IRQSTATUS_LC0_FE_IRQ BIT(8)
65 #define ISPCCP2_LC01_IRQSTATUS_LC0_COUNT_IRQ BIT(7)
66 #define ISPCCP2_LC01_IRQSTATUS_LC0_FIFO_OVF_IRQ BIT(5)
[all …]
/openbmc/linux/drivers/gpu/drm/mediatek/
H A Dmtk_dpi_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
10 #define EN BIT(0)
13 #define RST BIT(0)
16 #define INT_VSYNC_EN BIT(0)
17 #define INT_VDE_EN BIT(1)
18 #define INT_UNDERFLOW_EN BIT(2)
21 #define INT_VSYNC_STA BIT(0)
22 #define INT_VDE_STA BIT(1)
23 #define INT_UNDERFLOW_STA BIT(2)
26 #define BG_ENABLE BIT(0)
[all …]
/openbmc/linux/drivers/staging/sm750fb/
H A Dddk750_reg.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #define DE_STATE1_DE_ABORT BIT(0)
10 #define DE_STATE2_DE_FIFO_EMPTY BIT(3)
11 #define DE_STATE2_DE_STATUS_BUSY BIT(2)
12 #define DE_STATE2_DE_MEM_FIFO_EMPTY BIT(1)
20 #define SYSTEM_CTRL_PCI_BURST BIT(29)
21 #define SYSTEM_CTRL_PCI_MASTER BIT(25)
22 #define SYSTEM_CTRL_LATENCY_TIMER_OFF BIT(24)
23 #define SYSTEM_CTRL_DE_FIFO_EMPTY BIT(23)
24 #define SYSTEM_CTRL_DE_STATUS_BUSY BIT(22)
[all …]
H A Dsm750_accel.h1 /* SPDX-License-Identifier: GPL-2.0 */
25 #define DE_SOURCE_WRAP BIT(31)
26 #define DE_SOURCE_X_K1_SHIFT 16
27 #define DE_SOURCE_X_K1_MASK (0x3fff << 16)
28 #define DE_SOURCE_X_K1_MONO_MASK (0x1f << 16)
32 #define DE_DESTINATION_WRAP BIT(31)
33 #define DE_DESTINATION_X_SHIFT 16
34 #define DE_DESTINATION_X_MASK (0x1fff << 16)
38 #define DE_DIMENSION_X_SHIFT 16
39 #define DE_DIMENSION_X_MASK (0x1fff << 16)
[all …]
/openbmc/linux/drivers/staging/media/sunxi/sun6i-isp/
H A Dsun6i_isp_reg.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2021-2022 Bootlin
20 #define SUN6I_ISP_FE_CFG_EN BIT(0)
22 #define SUN6I_ISP_FE_CFG_SRC1_MODE(v) (((v) << 16) & GENMASK(17, 16))
25 #define SUN6I_ISP_FE_CTRL_SCAP_EN BIT(0)
26 #define SUN6I_ISP_FE_CTRL_VCAP_EN BIT(1)
27 #define SUN6I_ISP_FE_CTRL_PARA_READY BIT(2)
28 #define SUN6I_ISP_FE_CTRL_LUT_UPDATE BIT(3)
29 #define SUN6I_ISP_FE_CTRL_LENS_UPDATE BIT(4)
30 #define SUN6I_ISP_FE_CTRL_GAMMA_UPDATE BIT(5)
[all …]
/openbmc/linux/include/soc/mscc/
H A Docelot_dev.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
11 #define DEV_CLOCK_CFG_MAC_TX_RST BIT(7)
12 #define DEV_CLOCK_CFG_MAC_RX_RST BIT(6)
13 #define DEV_CLOCK_CFG_PCS_TX_RST BIT(5)
14 #define DEV_CLOCK_CFG_PCS_RX_RST BIT(4)
15 #define DEV_CLOCK_CFG_PORT_RST BIT(3)
16 #define DEV_CLOCK_CFG_PHY_RST BIT(2)
20 #define DEV_PORT_MISC_FWD_ERROR_ENA BIT(4)
21 #define DEV_PORT_MISC_FWD_PAUSE_ENA BIT(3)
22 #define DEV_PORT_MISC_FWD_CTRL_ENA BIT(2)
[all …]
/openbmc/linux/drivers/net/ethernet/mediatek/
H A Dmtk_wed_regs.h1 // SPDX-License-Identifier: GPL-2.0-only
7 #define MTK_WFDMA_DESC_CTRL_TO_HOST BIT(8)
10 #define MTK_WDMA_DESC_CTRL_LAST_SEG1 BIT(15)
11 #define MTK_WDMA_DESC_CTRL_BURST BIT(16)
12 #define MTK_WDMA_DESC_CTRL_LEN0 GENMASK(29, 16)
13 #define MTK_WDMA_DESC_CTRL_LAST_SEG0 BIT(30)
14 #define MTK_WDMA_DESC_CTRL_DMA_DONE BIT(31)
26 #define MTK_WED_RESET_TX_BM BIT(0)
27 #define MTK_WED_RESET_RX_BM BIT(1)
28 #define MTK_WED_RESET_TX_FREE_AGENT BIT(4)
[all …]
H A Dmtk_ppe_regs.h1 // SPDX-License-Identifier: GPL-2.0-only
8 #define MTK_PPE_GLO_CFG_EN BIT(0)
9 #define MTK_PPE_GLO_CFG_TSID_EN BIT(1)
10 #define MTK_PPE_GLO_CFG_IP4_L4_CS_DROP BIT(2)
11 #define MTK_PPE_GLO_CFG_IP4_CS_DROP BIT(3)
12 #define MTK_PPE_GLO_CFG_TTL0_DROP BIT(4)
13 #define MTK_PPE_GLO_CFG_PPE_BSWAP BIT(5)
14 #define MTK_PPE_GLO_CFG_PSE_HASH_OFS BIT(6)
15 #define MTK_PPE_GLO_CFG_MCAST_TB_EN BIT(7)
16 #define MTK_PPE_GLO_CFG_FLOW_DROP_KA BIT(8)
[all …]
/openbmc/linux/drivers/gpu/drm/mxsfb/
H A Dlcdif_regs.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
39 #define CTRL_SFTRST BIT(31)
40 #define CTRL_CLKGATE BIT(30)
41 #define CTRL_BYPASS_COUNT BIT(19)
42 #define CTRL_VSYNC_MODE BIT(18)
43 #define CTRL_DOTCLK_MODE BIT(17)
44 #define CTRL_DATA_SELECT BIT(16)
54 #define CTRL_MASTER BIT(5)
55 #define CTRL_DF16 BIT(3)
56 #define CTRL_DF18 BIT(2)
[all …]
/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwxgmac2.h1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
28 #define XGMAC_CONFIG_JD BIT(16)
29 #define XGMAC_CONFIG_TE BIT(0)
32 #define XGMAC_CONFIG_ARPEN BIT(31)
33 #define XGMAC_CONFIG_GPSL GENMASK(29, 16)
34 #define XGMAC_CONFIG_GPSL_SHIFT 16
38 #define XGMAC_CONFIG_S2KP BIT(11)
39 #define XGMAC_CONFIG_LM BIT(10)
40 #define XGMAC_CONFIG_IPC BIT(9)
41 #define XGMAC_CONFIG_JE BIT(8)
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/
H A Dmt76_connac2_mac.h1 /* SPDX-License-Identifier: ISC */
40 #define MT_TX_FREE_MSDU_ID GENMASK(30, 16)
41 #define MT_TX_FREE_PAIR BIT(31)
47 #define MT_TXD0_ETH_TYPE_OFFSET GENMASK(22, 16)
50 #define MT_TXD1_LONG_FORMAT BIT(31)
51 #define MT_TXD1_TGID BIT(30)
53 #define MT_TXD1_AMSDU BIT(23)
56 #define MT_TXD1_HDR_FORMAT GENMASK(17, 16)
58 #define MT_TXD1_ETH_802_3 BIT(15)
59 #define MT_TXD1_VTA BIT(10)
[all …]
H A Dmt76_connac3_mac.h1 /* SPDX-License-Identifier: ISC */
25 #define MT_RXD0_PKT_FLAG GENMASK(19, 16)
28 #define MT_RXD0_MESH BIT(18)
29 #define MT_RXD0_MHCP BIT(19)
30 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
31 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
32 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
34 #define MT_RXD0_SW_PKT_TYPE_MASK GENMASK(31, 16)
40 #define MT_RXD1_NORMAL_GROUP_1 BIT(16)
41 #define MT_RXD1_NORMAL_GROUP_2 BIT(17)
[all …]
/openbmc/linux/drivers/media/platform/nxp/imx8-isi/
H A Dimx8-isi-regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2019-2020 NXP
14 #define CHNL_CTRL_CHNL_EN BIT(31)
15 #define CHNL_CTRL_CLK_EN BIT(30)
16 #define CHNL_CTRL_CHNL_BYPASS BIT(29)
21 #define CHNL_CTRL_SW_RST BIT(24)
22 #define CHNL_CTRL_BLANK_PXL(n) ((n) << 16)
23 #define CHNL_CTRL_BLANK_PXL_MASK GENMASK(23, 16)
27 #define CHNL_CTRL_SRC_TYPE_MASK BIT(4)
86 #define CHNL_IMG_CTRL_GBL_ALPHA_VAL(n) ((n) << 16)
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dmac.h1 /* SPDX-License-Identifier: ISC */
11 #define MT_RXD0_PKT_FLAG GENMASK(19, 16)
14 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
25 #define MT_RXD1_MID_AMSDU_FRAME BIT(1)
[all …]
/openbmc/linux/drivers/net/ethernet/marvell/
H A Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
131 /* B0_CTST 16 bit Control/Status register */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
138 CS_BUS_SLOT_SZ = 1<<8, /* Slot Size 0/1 = 32/64 bit slot */
142 CS_STOP_MAST = 1<<4, /* Command Bit to stop the master */
148 /* B0_LED 8 Bit LED register */
149 /* Bit 7.. 2: reserved */
153 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
[all …]
/openbmc/linux/drivers/media/platform/renesas/vsp1/
H A Dvsp1_regs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * vsp1_regs.h -- R-Car VSP1 Registers Definitions
13 /* -----------------------------------------------------------------------------
18 #define VI6_CMD_UPDHDR BIT(4)
19 #define VI6_CMD_STRCMD BIT(0)
28 #define VI6_SRESET_SRTS(n) BIT(n)
31 #define VI6_STATUS_FLD_STD(n) BIT((n) + 28)
32 #define VI6_STATUS_SYS_ACT(n) BIT((n) + 8)
35 #define VI6_WPF_IRQ_ENB_UNDE BIT(16)
36 #define VI6_WPF_IRQ_ENB_DFEE BIT(1)
[all …]
/openbmc/u-boot/drivers/serial/
H A Dserial_sh.h2 * Copy and modify from linux/drivers/serial/sh-sci.h
26 # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
27 # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
38 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
39 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
41 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
52 # define SCIF_ORER 0x0200 /* overrun error bit */
54 # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
55 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
56 # define SCIF_ORER 0x0001 /* overrun error bit */
[all …]
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7603/
H A Dregs.h1 /* SPDX-License-Identifier: ISC */
28 #define MT_INT_RX_DONE(_n) BIT(_n)
31 #define MT_INT_TX_DONE(_n) BIT((_n) + 4)
33 #define MT_INT_RX_COHERENT BIT(20)
34 #define MT_INT_TX_COHERENT BIT(21)
35 #define MT_INT_MAC_IRQ3 BIT(27)
37 #define MT_INT_MCU_CMD BIT(30)
40 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
41 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
42 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
[all …]
/openbmc/u-boot/drivers/pinctrl/rockchip/
H A Dpinctrl-rk3328.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include "pinctrl-rockchip.h"
19 .bit = 8,
25 .bit = 0,
31 .bit = 14,
43 .route_val = BIT(16) | BIT(16 + 1),
50 .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
52 /* gmac-m1_rxd0 */
57 .route_val = BIT(16 + 2) | BIT(2),
59 /* gmac-m1-optimized_rxd3 */
[all …]
H A Dpinctrl-rk322x.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include "pinctrl-rockchip.h"
16 /* pwm0-0 */
21 .route_val = BIT(16),
23 /* pwm0-1 */
28 .route_val = BIT(16) | BIT(0),
30 /* pwm1-0 */
35 .route_val = BIT(16 + 1),
37 /* pwm1-1 */
42 .route_val = BIT(16 + 1) | BIT(1),
[all …]
/openbmc/linux/drivers/gpu/drm/vc4/
H A Dvc4_regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2014-2015 Broadcom
27 ('D' << 16))
33 # define V3D_IDENT1_NSEM_MASK VC4_MASK(23, 16)
34 # define V3D_IDENT1_NSEM_SHIFT 16
47 # define V3D_L2CACTL_L2CCLR BIT(2)
48 # define V3D_L2CACTL_L2CDIS BIT(1)
49 # define V3D_L2CACTL_L2CENA BIT(0)
54 # define V3D_SLCACTL_T0CC_MASK VC4_MASK(19, 16)
55 # define V3D_SLCACTL_T0CC_SHIFT 16
[all …]
/openbmc/linux/drivers/clk/stm32/
H A Dstm32mp13_rcc.h1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
3 * Copyright (C) 2020, STMicroelectronics - All Rights Reserved
225 #define RCC_SECCFGR_APB3DIVSEC 16
238 #define RCC_MP_SREQSETR_STPREQ_P0 BIT(0)
241 #define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0)
244 #define RCC_MP_APRSTCR_RDCTLEN BIT(0)
257 #define RCC_MP_GRSTCSETR_MPSYSRST BIT(0)
258 #define RCC_MP_GRSTCSETR_MPUP0RST BIT(4)
261 #define RCC_BR_RSTSCLRR_PORRSTF BIT(0)
262 #define RCC_BR_RSTSCLRR_BORRSTF BIT(1)
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dclock_manager_arria10.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2016-2017 Intel Corporation
124 #define CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK BIT(6)
125 #define CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK BIT(7)
126 #define CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK BIT(8)
127 #define CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK BIT(9)
128 #define CLKMGR_CLKMGR_STAT_BOOTCLKSRC_SET_MSK BIT(17)
129 #define CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK BIT(0)
130 #define CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK BIT(1)
131 #define CLKMGR_MAINPLL_VCO0_EN_SET_MSK BIT(2)
[all …]

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