1*cf21f328SLaurent Pinchart /* SPDX-License-Identifier: GPL-2.0 */ 2*cf21f328SLaurent Pinchart /* 3*cf21f328SLaurent Pinchart * Copyright 2019-2020 NXP 4*cf21f328SLaurent Pinchart */ 5*cf21f328SLaurent Pinchart 6*cf21f328SLaurent Pinchart #ifndef __IMX8_ISI_REGS_H__ 7*cf21f328SLaurent Pinchart #define __IMX8_ISI_REGS_H__ 8*cf21f328SLaurent Pinchart 9*cf21f328SLaurent Pinchart #include <linux/bits.h> 10*cf21f328SLaurent Pinchart 11*cf21f328SLaurent Pinchart /* ISI Registers Define */ 12*cf21f328SLaurent Pinchart /* Channel Control Register */ 13*cf21f328SLaurent Pinchart #define CHNL_CTRL 0x0000 14*cf21f328SLaurent Pinchart #define CHNL_CTRL_CHNL_EN BIT(31) 15*cf21f328SLaurent Pinchart #define CHNL_CTRL_CLK_EN BIT(30) 16*cf21f328SLaurent Pinchart #define CHNL_CTRL_CHNL_BYPASS BIT(29) 17*cf21f328SLaurent Pinchart #define CHNL_CTRL_CHAIN_BUF(n) ((n) << 25) 18*cf21f328SLaurent Pinchart #define CHNL_CTRL_CHAIN_BUF_MASK GENMASK(26, 25) 19*cf21f328SLaurent Pinchart #define CHNL_CTRL_CHAIN_BUF_NO_CHAIN 0 20*cf21f328SLaurent Pinchart #define CHNL_CTRL_CHAIN_BUF_2_CHAIN 1 21*cf21f328SLaurent Pinchart #define CHNL_CTRL_SW_RST BIT(24) 22*cf21f328SLaurent Pinchart #define CHNL_CTRL_BLANK_PXL(n) ((n) << 16) 23*cf21f328SLaurent Pinchart #define CHNL_CTRL_BLANK_PXL_MASK GENMASK(23, 16) 24*cf21f328SLaurent Pinchart #define CHNL_CTRL_MIPI_VC_ID(n) ((n) << 6) 25*cf21f328SLaurent Pinchart #define CHNL_CTRL_MIPI_VC_ID_MASK GENMASK(7, 6) 26*cf21f328SLaurent Pinchart #define CHNL_CTRL_SRC_TYPE(n) ((n) << 4) 27*cf21f328SLaurent Pinchart #define CHNL_CTRL_SRC_TYPE_MASK BIT(4) 28*cf21f328SLaurent Pinchart #define CHNL_CTRL_SRC_TYPE_DEVICE 0 29*cf21f328SLaurent Pinchart #define CHNL_CTRL_SRC_TYPE_MEMORY 1 30*cf21f328SLaurent Pinchart #define CHNL_CTRL_SRC_INPUT(n) ((n) << 0) 31*cf21f328SLaurent Pinchart #define CHNL_CTRL_SRC_INPUT_MASK GENMASK(2, 0) 32*cf21f328SLaurent Pinchart 33*cf21f328SLaurent Pinchart /* Channel Image Control Register */ 34*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL 0x0004 35*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT(n) ((n) << 24) 36*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_MASK GENMASK(29, 24) 37*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_RGBA8888 0x00 38*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_ABGR8888 0x01 39*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_ARGB8888 0x02 40*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_RGBX888 0x03 41*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_XBGR888 0x04 42*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_XRGB888 0x05 43*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_RGB888P 0x06 44*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_BGR888P 0x07 45*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_A2BGR10 0x08 46*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_A2RGB10 0x09 47*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_RGB565 0x0a 48*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_RAW8 0x0b 49*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_RAW10 0x0c 50*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_RAW10P 0x0d 51*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_RAW12 0x0e 52*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_RAW16 0x0f 53*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV444_1P8P 0x10 54*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV444_2P8P 0x11 55*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV444_3P8P 0x12 56*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV444_1P8 0x13 57*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV444_1P10 0x14 58*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV444_2P10 0x15 59*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV444_3P10 0x16 60*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV444_1P10P 0x18 61*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV444_2P10P 0x19 62*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV444_3P10P 0x1a 63*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV444_1P12 0x1c 64*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV444_2P12 0x1d 65*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV444_3P12 0x1e 66*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV422_1P8P 0x20 67*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV422_2P8P 0x21 68*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV422_3P8P 0x22 69*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV422_1P10 0x24 70*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV422_2P10 0x25 71*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV422_3P10 0x26 72*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV422_1P10P 0x28 73*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV422_2P10P 0x29 74*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV422_3P10P 0x2a 75*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV422_1P12 0x2c 76*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV422_2P12 0x2d 77*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV422_3P12 0x2e 78*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV420_2P8P 0x31 79*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV420_3P8P 0x32 80*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV420_2P10 0x35 81*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV420_3P10 0x36 82*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV420_2P10P 0x39 83*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV420_3P10P 0x3a 84*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV420_2P12 0x3d 85*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_FORMAT_YUV420_3P12 0x3e 86*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_GBL_ALPHA_VAL(n) ((n) << 16) 87*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK GENMASK(23, 16) 88*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_GBL_ALPHA_EN BIT(15) 89*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_DEINT(n) ((n) << 12) 90*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_DEINT_MASK GENMASK(14, 12) 91*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_DEINT_WEAVE_ODD_EVEN 2 92*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_DEINT_WEAVE_EVEN_ODD 3 93*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_DEINT_BLEND_ODD_EVEN 4 94*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_DEINT_BLEND_EVEN_ODD 5 95*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_DEINT_LDOUBLE_ODD_EVEN 6 96*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_DEINT_LDOUBLE_EVEN_ODD 7 97*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_DEC_X(n) ((n) << 10) 98*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_DEC_X_MASK GENMASK(11, 10) 99*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_DEC_Y(n) ((n) << 8) 100*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_DEC_Y_MASK GENMASK(9, 8) 101*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_CROP_EN BIT(7) 102*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_VFLIP_EN BIT(6) 103*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_HFLIP_EN BIT(5) 104*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_YCBCR_MODE BIT(3) 105*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_CSC_MODE(n) ((n) << 1) 106*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_CSC_MODE_MASK GENMASK(2, 1) 107*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_CSC_MODE_YUV2RGB 0 108*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_CSC_MODE_YCBCR2RGB 1 109*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_CSC_MODE_RGB2YUV 2 110*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_CSC_MODE_RGB2YCBCR 3 111*cf21f328SLaurent Pinchart #define CHNL_IMG_CTRL_CSC_BYPASS BIT(0) 112*cf21f328SLaurent Pinchart 113*cf21f328SLaurent Pinchart /* Channel Output Buffer Control Register */ 114*cf21f328SLaurent Pinchart #define CHNL_OUT_BUF_CTRL 0x0008 115*cf21f328SLaurent Pinchart #define CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR BIT(15) 116*cf21f328SLaurent Pinchart #define CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR BIT(14) 117*cf21f328SLaurent Pinchart #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V(n) ((n) << 6) 118*cf21f328SLaurent Pinchart #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_MASK GENMASK(7, 6) 119*cf21f328SLaurent Pinchart #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_NO_PANIC 0 120*cf21f328SLaurent Pinchart #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_PANIC_25 1 121*cf21f328SLaurent Pinchart #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_PANIC_50 2 122*cf21f328SLaurent Pinchart #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_PANIC_75 3 123*cf21f328SLaurent Pinchart #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U(n) ((n) << 3) 124*cf21f328SLaurent Pinchart #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_MASK GENMASK(4, 3) 125*cf21f328SLaurent Pinchart #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_NO_PANIC 0 126*cf21f328SLaurent Pinchart #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_PANIC_25 1 127*cf21f328SLaurent Pinchart #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_PANIC_50 2 128*cf21f328SLaurent Pinchart #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_PANIC_75 3 129*cf21f328SLaurent Pinchart #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y(n) ((n) << 0) 130*cf21f328SLaurent Pinchart #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_MASK GENMASK(1, 0) 131*cf21f328SLaurent Pinchart #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_NO_PANIC 0 132*cf21f328SLaurent Pinchart #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_PANIC_25 1 133*cf21f328SLaurent Pinchart #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_PANIC_50 2 134*cf21f328SLaurent Pinchart #define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_PANIC_75 3 135*cf21f328SLaurent Pinchart 136*cf21f328SLaurent Pinchart /* Channel Image Configuration */ 137*cf21f328SLaurent Pinchart #define CHNL_IMG_CFG 0x000c 138*cf21f328SLaurent Pinchart #define CHNL_IMG_CFG_HEIGHT(n) ((n) << 16) 139*cf21f328SLaurent Pinchart #define CHNL_IMG_CFG_HEIGHT_MASK GENMASK(28, 16) 140*cf21f328SLaurent Pinchart #define CHNL_IMG_CFG_WIDTH(n) ((n) << 0) 141*cf21f328SLaurent Pinchart #define CHNL_IMG_CFG_WIDTH_MASK GENMASK(12, 0) 142*cf21f328SLaurent Pinchart 143*cf21f328SLaurent Pinchart /* Channel Interrupt Enable Register */ 144*cf21f328SLaurent Pinchart #define CHNL_IER 0x0010 145*cf21f328SLaurent Pinchart #define CHNL_IER_MEM_RD_DONE_EN BIT(31) 146*cf21f328SLaurent Pinchart #define CHNL_IER_LINE_RCVD_EN BIT(30) 147*cf21f328SLaurent Pinchart #define CHNL_IER_FRM_RCVD_EN BIT(29) 148*cf21f328SLaurent Pinchart #define CHNL_IER_AXI_WR_ERR_V_EN BIT(28) 149*cf21f328SLaurent Pinchart #define CHNL_IER_AXI_WR_ERR_U_EN BIT(27) 150*cf21f328SLaurent Pinchart #define CHNL_IER_AXI_WR_ERR_Y_EN BIT(26) 151*cf21f328SLaurent Pinchart #define CHNL_IER_AXI_RD_ERR_EN BIT(25) 152*cf21f328SLaurent Pinchart 153*cf21f328SLaurent Pinchart /* Channel Status Register */ 154*cf21f328SLaurent Pinchart #define CHNL_STS 0x0014 155*cf21f328SLaurent Pinchart #define CHNL_STS_MEM_RD_DONE BIT(31) 156*cf21f328SLaurent Pinchart #define CHNL_STS_LINE_STRD BIT(30) 157*cf21f328SLaurent Pinchart #define CHNL_STS_FRM_STRD BIT(29) 158*cf21f328SLaurent Pinchart #define CHNL_STS_AXI_WR_ERR_V BIT(28) 159*cf21f328SLaurent Pinchart #define CHNL_STS_AXI_WR_ERR_U BIT(27) 160*cf21f328SLaurent Pinchart #define CHNL_STS_AXI_WR_ERR_Y BIT(26) 161*cf21f328SLaurent Pinchart #define CHNL_STS_AXI_RD_ERR BIT(25) 162*cf21f328SLaurent Pinchart #define CHNL_STS_OFLW_PANIC_V_BUF BIT(24) 163*cf21f328SLaurent Pinchart #define CHNL_STS_EXCS_OFLW_V_BUF BIT(23) 164*cf21f328SLaurent Pinchart #define CHNL_STS_OFLW_V_BUF BIT(22) 165*cf21f328SLaurent Pinchart #define CHNL_STS_OFLW_PANIC_U_BUF BIT(21) 166*cf21f328SLaurent Pinchart #define CHNL_STS_EXCS_OFLW_U_BUF BIT(20) 167*cf21f328SLaurent Pinchart #define CHNL_STS_OFLW_U_BUF BIT(19) 168*cf21f328SLaurent Pinchart #define CHNL_STS_OFLW_PANIC_Y_BUF BIT(18) 169*cf21f328SLaurent Pinchart #define CHNL_STS_EXCS_OFLW_Y_BUF BIT(17) 170*cf21f328SLaurent Pinchart #define CHNL_STS_OFLW_Y_BUF BIT(16) 171*cf21f328SLaurent Pinchart #define CHNL_STS_EARLY_VSYNC_ERR BIT(15) 172*cf21f328SLaurent Pinchart #define CHNL_STS_LATE_VSYNC_ERR BIT(14) 173*cf21f328SLaurent Pinchart #define CHNL_STS_MEM_RD_OFLOW BIT(10) 174*cf21f328SLaurent Pinchart #define CHNL_STS_BUF2_ACTIVE BIT(9) 175*cf21f328SLaurent Pinchart #define CHNL_STS_BUF1_ACTIVE BIT(8) 176*cf21f328SLaurent Pinchart #define CHNL_STS_OFLW_BYTES(n) ((n) << 0) 177*cf21f328SLaurent Pinchart #define CHNL_STS_OFLW_BYTES_MASK GENMASK(7, 0) 178*cf21f328SLaurent Pinchart 179*cf21f328SLaurent Pinchart /* Channel Scale Factor Register */ 180*cf21f328SLaurent Pinchart #define CHNL_SCALE_FACTOR 0x0018 181*cf21f328SLaurent Pinchart #define CHNL_SCALE_FACTOR_Y_SCALE(n) ((n) << 16) 182*cf21f328SLaurent Pinchart #define CHNL_SCALE_FACTOR_Y_SCALE_MASK GENMASK(29, 16) 183*cf21f328SLaurent Pinchart #define CHNL_SCALE_FACTOR_X_SCALE(n) ((n) << 0) 184*cf21f328SLaurent Pinchart #define CHNL_SCALE_FACTOR_X_SCALE_MASK GENMASK(13, 0) 185*cf21f328SLaurent Pinchart 186*cf21f328SLaurent Pinchart /* Channel Scale Offset Register */ 187*cf21f328SLaurent Pinchart #define CHNL_SCALE_OFFSET 0x001c 188*cf21f328SLaurent Pinchart #define CHNL_SCALE_OFFSET_Y_SCALE(n) ((n) << 16) 189*cf21f328SLaurent Pinchart #define CHNL_SCALE_OFFSET_Y_SCALE_MASK GENMASK(27, 16) 190*cf21f328SLaurent Pinchart #define CHNL_SCALE_OFFSET_X_SCALE(n) ((n) << 0) 191*cf21f328SLaurent Pinchart #define CHNL_SCALE_OFFSET_X_SCALE_MASK GENMASK(11, 0) 192*cf21f328SLaurent Pinchart 193*cf21f328SLaurent Pinchart /* Channel Crop Upper Left Corner Coordinate Register */ 194*cf21f328SLaurent Pinchart #define CHNL_CROP_ULC 0x0020 195*cf21f328SLaurent Pinchart #define CHNL_CROP_ULC_X(n) ((n) << 16) 196*cf21f328SLaurent Pinchart #define CHNL_CROP_ULC_X_MASK GENMASK(27, 16) 197*cf21f328SLaurent Pinchart #define CHNL_CROP_ULC_Y(n) ((n) << 0) 198*cf21f328SLaurent Pinchart #define CHNL_CROP_ULC_Y_MASK GENMASK(11, 0) 199*cf21f328SLaurent Pinchart 200*cf21f328SLaurent Pinchart /* Channel Crop Lower Right Corner Coordinate Register */ 201*cf21f328SLaurent Pinchart #define CHNL_CROP_LRC 0x0024 202*cf21f328SLaurent Pinchart #define CHNL_CROP_LRC_X(n) ((n) << 16) 203*cf21f328SLaurent Pinchart #define CHNL_CROP_LRC_X_MASK GENMASK(27, 16) 204*cf21f328SLaurent Pinchart #define CHNL_CROP_LRC_Y(n) ((n) << 0) 205*cf21f328SLaurent Pinchart #define CHNL_CROP_LRC_Y_MASK GENMASK(11, 0) 206*cf21f328SLaurent Pinchart 207*cf21f328SLaurent Pinchart /* Channel Color Space Conversion Coefficient Register 0 */ 208*cf21f328SLaurent Pinchart #define CHNL_CSC_COEFF0 0x0028 209*cf21f328SLaurent Pinchart #define CHNL_CSC_COEFF0_A2(n) ((n) << 16) 210*cf21f328SLaurent Pinchart #define CHNL_CSC_COEFF0_A2_MASK GENMASK(26, 16) 211*cf21f328SLaurent Pinchart #define CHNL_CSC_COEFF0_A1(n) ((n) << 0) 212*cf21f328SLaurent Pinchart #define CHNL_CSC_COEFF0_A1_MASK GENMASK(10, 0) 213*cf21f328SLaurent Pinchart 214*cf21f328SLaurent Pinchart /* Channel Color Space Conversion Coefficient Register 1 */ 215*cf21f328SLaurent Pinchart #define CHNL_CSC_COEFF1 0x002c 216*cf21f328SLaurent Pinchart #define CHNL_CSC_COEFF1_B1(n) ((n) << 16) 217*cf21f328SLaurent Pinchart #define CHNL_CSC_COEFF1_B1_MASK GENMASK(26, 16) 218*cf21f328SLaurent Pinchart #define CHNL_CSC_COEFF1_A3(n) ((n) << 0) 219*cf21f328SLaurent Pinchart #define CHNL_CSC_COEFF1_A3_MASK GENMASK(10, 0) 220*cf21f328SLaurent Pinchart 221*cf21f328SLaurent Pinchart /* Channel Color Space Conversion Coefficient Register 2 */ 222*cf21f328SLaurent Pinchart #define CHNL_CSC_COEFF2 0x0030 223*cf21f328SLaurent Pinchart #define CHNL_CSC_COEFF2_B3(n) ((n) << 16) 224*cf21f328SLaurent Pinchart #define CHNL_CSC_COEFF2_B3_MASK GENMASK(26, 16) 225*cf21f328SLaurent Pinchart #define CHNL_CSC_COEFF2_B2(n) ((n) << 0) 226*cf21f328SLaurent Pinchart #define CHNL_CSC_COEFF2_B2_MASK GENMASK(10, 0) 227*cf21f328SLaurent Pinchart 228*cf21f328SLaurent Pinchart /* Channel Color Space Conversion Coefficient Register 3 */ 229*cf21f328SLaurent Pinchart #define CHNL_CSC_COEFF3 0x0034 230*cf21f328SLaurent Pinchart #define CHNL_CSC_COEFF3_C2(n) ((n) << 16) 231*cf21f328SLaurent Pinchart #define CHNL_CSC_COEFF3_C2_MASK GENMASK(26, 16) 232*cf21f328SLaurent Pinchart #define CHNL_CSC_COEFF3_C1(n) ((n) << 0) 233*cf21f328SLaurent Pinchart #define CHNL_CSC_COEFF3_C1_MASK GENMASK(10, 0) 234*cf21f328SLaurent Pinchart 235*cf21f328SLaurent Pinchart /* Channel Color Space Conversion Coefficient Register 4 */ 236*cf21f328SLaurent Pinchart #define CHNL_CSC_COEFF4 0x0038 237*cf21f328SLaurent Pinchart #define CHNL_CSC_COEFF4_D1(n) ((n) << 16) 238*cf21f328SLaurent Pinchart #define CHNL_CSC_COEFF4_D1_MASK GENMASK(24, 16) 239*cf21f328SLaurent Pinchart #define CHNL_CSC_COEFF4_C3(n) ((n) << 0) 240*cf21f328SLaurent Pinchart #define CHNL_CSC_COEFF4_C3_MASK GENMASK(10, 0) 241*cf21f328SLaurent Pinchart 242*cf21f328SLaurent Pinchart /* Channel Color Space Conversion Coefficient Register 5 */ 243*cf21f328SLaurent Pinchart #define CHNL_CSC_COEFF5 0x003c 244*cf21f328SLaurent Pinchart #define CHNL_CSC_COEFF5_D3(n) ((n) << 16) 245*cf21f328SLaurent Pinchart #define CHNL_CSC_COEFF5_D3_MASK GENMASK(24, 16) 246*cf21f328SLaurent Pinchart #define CHNL_CSC_COEFF5_D2(n) ((n) << 0) 247*cf21f328SLaurent Pinchart #define CHNL_CSC_COEFF5_D2_MASK GENMASK(8, 0) 248*cf21f328SLaurent Pinchart 249*cf21f328SLaurent Pinchart /* Channel Alpha Value Register for ROI 0 */ 250*cf21f328SLaurent Pinchart #define CHNL_ROI_0_ALPHA 0x0040 251*cf21f328SLaurent Pinchart #define CHNL_ROI_0_ALPHA_VAL(n) ((n) << 24) 252*cf21f328SLaurent Pinchart #define CHNL_ROI_0_ALPHA_MASK GENMASK(31, 24) 253*cf21f328SLaurent Pinchart #define CHNL_ROI_0_ALPHA_EN BIT(16) 254*cf21f328SLaurent Pinchart 255*cf21f328SLaurent Pinchart /* Channel Upper Left Coordinate Register for ROI 0 */ 256*cf21f328SLaurent Pinchart #define CHNL_ROI_0_ULC 0x0044 257*cf21f328SLaurent Pinchart #define CHNL_ROI_0_ULC_X(n) ((n) << 16) 258*cf21f328SLaurent Pinchart #define CHNL_ROI_0_ULC_X_MASK GENMASK(27, 16) 259*cf21f328SLaurent Pinchart #define CHNL_ROI_0_ULC_Y(n) ((n) << 0) 260*cf21f328SLaurent Pinchart #define CHNL_ROI_0_ULC_Y_MASK GENMASK(11, 0) 261*cf21f328SLaurent Pinchart 262*cf21f328SLaurent Pinchart /* Channel Lower Right Coordinate Register for ROI 0 */ 263*cf21f328SLaurent Pinchart #define CHNL_ROI_0_LRC 0x0048 264*cf21f328SLaurent Pinchart #define CHNL_ROI_0_LRC_X(n) ((n) << 16) 265*cf21f328SLaurent Pinchart #define CHNL_ROI_0_LRC_X_MASK GENMASK(27, 16) 266*cf21f328SLaurent Pinchart #define CHNL_ROI_0_LRC_Y(n) ((n) << 0) 267*cf21f328SLaurent Pinchart #define CHNL_ROI_0_LRC_Y_MASK GENMASK(11, 0) 268*cf21f328SLaurent Pinchart 269*cf21f328SLaurent Pinchart /* Channel Alpha Value Register for ROI 1 */ 270*cf21f328SLaurent Pinchart #define CHNL_ROI_1_ALPHA 0x004c 271*cf21f328SLaurent Pinchart #define CHNL_ROI_1_ALPHA_VAL(n) ((n) << 24) 272*cf21f328SLaurent Pinchart #define CHNL_ROI_1_ALPHA_MASK GENMASK(31, 24) 273*cf21f328SLaurent Pinchart #define CHNL_ROI_1_ALPHA_EN BIT(16) 274*cf21f328SLaurent Pinchart 275*cf21f328SLaurent Pinchart /* Channel Upper Left Coordinate Register for ROI 1 */ 276*cf21f328SLaurent Pinchart #define CHNL_ROI_1_ULC 0x0050 277*cf21f328SLaurent Pinchart #define CHNL_ROI_1_ULC_X(n) ((n) << 16) 278*cf21f328SLaurent Pinchart #define CHNL_ROI_1_ULC_X_MASK GENMASK(27, 16) 279*cf21f328SLaurent Pinchart #define CHNL_ROI_1_ULC_Y(n) ((n) << 0) 280*cf21f328SLaurent Pinchart #define CHNL_ROI_1_ULC_Y_MASK GENMASK(11, 0) 281*cf21f328SLaurent Pinchart 282*cf21f328SLaurent Pinchart /* Channel Lower Right Coordinate Register for ROI 1 */ 283*cf21f328SLaurent Pinchart #define CHNL_ROI_1_LRC 0x0054 284*cf21f328SLaurent Pinchart #define CHNL_ROI_1_LRC_X(n) ((n) << 16) 285*cf21f328SLaurent Pinchart #define CHNL_ROI_1_LRC_X_MASK GENMASK(27, 16) 286*cf21f328SLaurent Pinchart #define CHNL_ROI_1_LRC_Y(n) ((n) << 0) 287*cf21f328SLaurent Pinchart #define CHNL_ROI_1_LRC_Y_MASK GENMASK(11, 0) 288*cf21f328SLaurent Pinchart 289*cf21f328SLaurent Pinchart /* Channel Alpha Value Register for ROI 2 */ 290*cf21f328SLaurent Pinchart #define CHNL_ROI_2_ALPHA 0x0058 291*cf21f328SLaurent Pinchart #define CHNL_ROI_2_ALPHA_VAL(n) ((n) << 24) 292*cf21f328SLaurent Pinchart #define CHNL_ROI_2_ALPHA_MASK GENMASK(31, 24) 293*cf21f328SLaurent Pinchart #define CHNL_ROI_2_ALPHA_EN BIT(16) 294*cf21f328SLaurent Pinchart 295*cf21f328SLaurent Pinchart /* Channel Upper Left Coordinate Register for ROI 2 */ 296*cf21f328SLaurent Pinchart #define CHNL_ROI_2_ULC 0x005c 297*cf21f328SLaurent Pinchart #define CHNL_ROI_2_ULC_X(n) ((n) << 16) 298*cf21f328SLaurent Pinchart #define CHNL_ROI_2_ULC_X_MASK GENMASK(27, 16) 299*cf21f328SLaurent Pinchart #define CHNL_ROI_2_ULC_Y(n) ((n) << 0) 300*cf21f328SLaurent Pinchart #define CHNL_ROI_2_ULC_Y_MASK GENMASK(11, 0) 301*cf21f328SLaurent Pinchart 302*cf21f328SLaurent Pinchart /* Channel Lower Right Coordinate Register for ROI 2 */ 303*cf21f328SLaurent Pinchart #define CHNL_ROI_2_LRC 0x0060 304*cf21f328SLaurent Pinchart #define CHNL_ROI_2_LRC_X(n) ((n) << 16) 305*cf21f328SLaurent Pinchart #define CHNL_ROI_2_LRC_X_MASK GENMASK(27, 16) 306*cf21f328SLaurent Pinchart #define CHNL_ROI_2_LRC_Y(n) ((n) << 0) 307*cf21f328SLaurent Pinchart #define CHNL_ROI_2_LRC_Y_MASK GENMASK(11, 0) 308*cf21f328SLaurent Pinchart 309*cf21f328SLaurent Pinchart /* Channel Alpha Value Register for ROI 3 */ 310*cf21f328SLaurent Pinchart #define CHNL_ROI_3_ALPHA 0x0064 311*cf21f328SLaurent Pinchart #define CHNL_ROI_3_ALPHA_VAL(n) ((n) << 24) 312*cf21f328SLaurent Pinchart #define CHNL_ROI_3_ALPHA_MASK GENMASK(31, 24) 313*cf21f328SLaurent Pinchart #define CHNL_ROI_3_ALPHA_EN BIT(16) 314*cf21f328SLaurent Pinchart 315*cf21f328SLaurent Pinchart /* Channel Upper Left Coordinate Register for ROI 3 */ 316*cf21f328SLaurent Pinchart #define CHNL_ROI_3_ULC 0x0068 317*cf21f328SLaurent Pinchart #define CHNL_ROI_3_ULC_X(n) ((n) << 16) 318*cf21f328SLaurent Pinchart #define CHNL_ROI_3_ULC_X_MASK GENMASK(27, 16) 319*cf21f328SLaurent Pinchart #define CHNL_ROI_3_ULC_Y(n) ((n) << 0) 320*cf21f328SLaurent Pinchart #define CHNL_ROI_3_ULC_Y_MASK GENMASK(11, 0) 321*cf21f328SLaurent Pinchart 322*cf21f328SLaurent Pinchart /* Channel Lower Right Coordinate Register for ROI 3 */ 323*cf21f328SLaurent Pinchart #define CHNL_ROI_3_LRC 0x006c 324*cf21f328SLaurent Pinchart #define CHNL_ROI_3_LRC_X(n) ((n) << 16) 325*cf21f328SLaurent Pinchart #define CHNL_ROI_3_LRC_X_MASK GENMASK(27, 16) 326*cf21f328SLaurent Pinchart #define CHNL_ROI_3_LRC_Y(n) ((n) << 0) 327*cf21f328SLaurent Pinchart #define CHNL_ROI_3_LRC_Y_MASK GENMASK(11, 0) 328*cf21f328SLaurent Pinchart /* Channel RGB or Luma (Y) Output Buffer 1 Address */ 329*cf21f328SLaurent Pinchart #define CHNL_OUT_BUF1_ADDR_Y 0x0070 330*cf21f328SLaurent Pinchart 331*cf21f328SLaurent Pinchart /* Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address */ 332*cf21f328SLaurent Pinchart #define CHNL_OUT_BUF1_ADDR_U 0x0074 333*cf21f328SLaurent Pinchart 334*cf21f328SLaurent Pinchart /* Channel Chroma (V/Cr) Output Buffer 1 Address */ 335*cf21f328SLaurent Pinchart #define CHNL_OUT_BUF1_ADDR_V 0x0078 336*cf21f328SLaurent Pinchart 337*cf21f328SLaurent Pinchart /* Channel Output Buffer Pitch */ 338*cf21f328SLaurent Pinchart #define CHNL_OUT_BUF_PITCH 0x007c 339*cf21f328SLaurent Pinchart #define CHNL_OUT_BUF_PITCH_LINE_PITCH(n) ((n) << 0) 340*cf21f328SLaurent Pinchart #define CHNL_OUT_BUF_PITCH_LINE_PITCH_MASK GENMASK(15, 0) 341*cf21f328SLaurent Pinchart 342*cf21f328SLaurent Pinchart /* Channel Input Buffer Address */ 343*cf21f328SLaurent Pinchart #define CHNL_IN_BUF_ADDR 0x0080 344*cf21f328SLaurent Pinchart 345*cf21f328SLaurent Pinchart /* Channel Input Buffer Pitch */ 346*cf21f328SLaurent Pinchart #define CHNL_IN_BUF_PITCH 0x0084 347*cf21f328SLaurent Pinchart #define CHNL_IN_BUF_PITCH_FRM_PITCH(n) ((n) << 16) 348*cf21f328SLaurent Pinchart #define CHNL_IN_BUF_PITCH_FRM_PITCH_MASK GENMASK(31, 16) 349*cf21f328SLaurent Pinchart #define CHNL_IN_BUF_PITCH_LINE_PITCH(n) ((n) << 0) 350*cf21f328SLaurent Pinchart #define CHNL_IN_BUF_PITCH_LINE_PITCH_MASK GENMASK(15, 0) 351*cf21f328SLaurent Pinchart 352*cf21f328SLaurent Pinchart /* Channel Memory Read Control */ 353*cf21f328SLaurent Pinchart #define CHNL_MEM_RD_CTRL 0x0088 354*cf21f328SLaurent Pinchart #define CHNL_MEM_RD_CTRL_IMG_TYPE(n) ((n) << 28) 355*cf21f328SLaurent Pinchart #define CHNL_MEM_RD_CTRL_IMG_TYPE_MASK GENMASK(31, 28) 356*cf21f328SLaurent Pinchart #define CHNL_MEM_RD_CTRL_IMG_TYPE_BGR8P 0x00 357*cf21f328SLaurent Pinchart #define CHNL_MEM_RD_CTRL_IMG_TYPE_RGB8P 0x01 358*cf21f328SLaurent Pinchart #define CHNL_MEM_RD_CTRL_IMG_TYPE_XRGB8 0x02 359*cf21f328SLaurent Pinchart #define CHNL_MEM_RD_CTRL_IMG_TYPE_RGBX8 0x03 360*cf21f328SLaurent Pinchart #define CHNL_MEM_RD_CTRL_IMG_TYPE_XBGR8 0x04 361*cf21f328SLaurent Pinchart #define CHNL_MEM_RD_CTRL_IMG_TYPE_RGB565 0x05 362*cf21f328SLaurent Pinchart #define CHNL_MEM_RD_CTRL_IMG_TYPE_A2BGR10 0x06 363*cf21f328SLaurent Pinchart #define CHNL_MEM_RD_CTRL_IMG_TYPE_A2RGB10 0x07 364*cf21f328SLaurent Pinchart #define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV444_1P8P 0x08 365*cf21f328SLaurent Pinchart #define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV444_1P10 0x09 366*cf21f328SLaurent Pinchart #define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV444_1P10P 0x0a 367*cf21f328SLaurent Pinchart #define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV444_1P12 0x0b 368*cf21f328SLaurent Pinchart #define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV444_1P8 0x0c 369*cf21f328SLaurent Pinchart #define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV422_1P8P 0x0d 370*cf21f328SLaurent Pinchart #define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV422_1P10 0x0e 371*cf21f328SLaurent Pinchart #define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV422_1P12 0x0f 372*cf21f328SLaurent Pinchart #define CHNL_MEM_RD_CTRL_READ_MEM BIT(0) 373*cf21f328SLaurent Pinchart 374*cf21f328SLaurent Pinchart /* Channel RGB or Luma (Y) Output Buffer 2 Address */ 375*cf21f328SLaurent Pinchart #define CHNL_OUT_BUF2_ADDR_Y 0x008c 376*cf21f328SLaurent Pinchart 377*cf21f328SLaurent Pinchart /* Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address */ 378*cf21f328SLaurent Pinchart #define CHNL_OUT_BUF2_ADDR_U 0x0090 379*cf21f328SLaurent Pinchart 380*cf21f328SLaurent Pinchart /* Channel Chroma (V/Cr) Output Buffer 2 Address */ 381*cf21f328SLaurent Pinchart #define CHNL_OUT_BUF2_ADDR_V 0x0094 382*cf21f328SLaurent Pinchart 383*cf21f328SLaurent Pinchart /* Channel scale image config */ 384*cf21f328SLaurent Pinchart #define CHNL_SCL_IMG_CFG 0x0098 385*cf21f328SLaurent Pinchart #define CHNL_SCL_IMG_CFG_HEIGHT(n) ((n) << 16) 386*cf21f328SLaurent Pinchart #define CHNL_SCL_IMG_CFG_HEIGHT_MASK GENMASK(28, 16) 387*cf21f328SLaurent Pinchart #define CHNL_SCL_IMG_CFG_WIDTH(n) ((n) << 0) 388*cf21f328SLaurent Pinchart #define CHNL_SCL_IMG_CFG_WIDTH_MASK GENMASK(12, 0) 389*cf21f328SLaurent Pinchart 390*cf21f328SLaurent Pinchart /* Channel Flow Control Register */ 391*cf21f328SLaurent Pinchart #define CHNL_FLOW_CTRL 0x009c 392*cf21f328SLaurent Pinchart #define CHNL_FLOW_CTRL_FC_DENOM_MASK GENMASK(7, 0) 393*cf21f328SLaurent Pinchart #define CHNL_FLOW_CTRL_FC_DENOM(n) ((n) << 0) 394*cf21f328SLaurent Pinchart #define CHNL_FLOW_CTRL_FC_NUMER_MASK GENMASK(23, 16) 395*cf21f328SLaurent Pinchart #define CHNL_FLOW_CTRL_FC_NUMER(n) ((n) << 0) 396*cf21f328SLaurent Pinchart 397*cf21f328SLaurent Pinchart /* Channel Output Y-Buffer 1 Extended Address Bits */ 398*cf21f328SLaurent Pinchart #define CHNL_Y_BUF1_XTND_ADDR 0x00a0 399*cf21f328SLaurent Pinchart 400*cf21f328SLaurent Pinchart /* Channel Output U-Buffer 1 Extended Address Bits */ 401*cf21f328SLaurent Pinchart #define CHNL_U_BUF1_XTND_ADDR 0x00a4 402*cf21f328SLaurent Pinchart 403*cf21f328SLaurent Pinchart /* Channel Output V-Buffer 1 Extended Address Bits */ 404*cf21f328SLaurent Pinchart #define CHNL_V_BUF1_XTND_ADDR 0x00a8 405*cf21f328SLaurent Pinchart 406*cf21f328SLaurent Pinchart /* Channel Output Y-Buffer 2 Extended Address Bits */ 407*cf21f328SLaurent Pinchart #define CHNL_Y_BUF2_XTND_ADDR 0x00ac 408*cf21f328SLaurent Pinchart 409*cf21f328SLaurent Pinchart /* Channel Output U-Buffer 2 Extended Address Bits */ 410*cf21f328SLaurent Pinchart #define CHNL_U_BUF2_XTND_ADDR 0x00b0 411*cf21f328SLaurent Pinchart 412*cf21f328SLaurent Pinchart /* Channel Output V-Buffer 2 Extended Address Bits */ 413*cf21f328SLaurent Pinchart #define CHNL_V_BUF2_XTND_ADDR 0x00b4 414*cf21f328SLaurent Pinchart 415*cf21f328SLaurent Pinchart /* Channel Input Buffer Extended Address Bits */ 416*cf21f328SLaurent Pinchart #define CHNL_IN_BUF_XTND_ADDR 0x00b8 417*cf21f328SLaurent Pinchart 418*cf21f328SLaurent Pinchart #endif /* __IMX8_ISI_REGS_H__ */ 419