Lines Matching +full:16 +full:- +full:bit
1 // SPDX-License-Identifier: GPL-2.0-only
7 #define MTK_WFDMA_DESC_CTRL_TO_HOST BIT(8)
10 #define MTK_WDMA_DESC_CTRL_LAST_SEG1 BIT(15)
11 #define MTK_WDMA_DESC_CTRL_BURST BIT(16)
12 #define MTK_WDMA_DESC_CTRL_LEN0 GENMASK(29, 16)
13 #define MTK_WDMA_DESC_CTRL_LAST_SEG0 BIT(30)
14 #define MTK_WDMA_DESC_CTRL_DMA_DONE BIT(31)
26 #define MTK_WED_RESET_TX_BM BIT(0)
27 #define MTK_WED_RESET_RX_BM BIT(1)
28 #define MTK_WED_RESET_TX_FREE_AGENT BIT(4)
29 #define MTK_WED_RESET_WPDMA_TX_DRV BIT(8)
30 #define MTK_WED_RESET_WPDMA_RX_DRV BIT(9)
31 #define MTK_WED_RESET_WPDMA_RX_D_DRV BIT(10)
32 #define MTK_WED_RESET_WPDMA_INT_AGENT BIT(11)
33 #define MTK_WED_RESET_WED_TX_DMA BIT(12)
34 #define MTK_WED_RESET_WED_RX_DMA BIT(13)
35 #define MTK_WED_RESET_WDMA_TX_DRV BIT(16)
36 #define MTK_WED_RESET_WDMA_RX_DRV BIT(17)
37 #define MTK_WED_RESET_WDMA_INT_AGENT BIT(19)
38 #define MTK_WED_RESET_RX_RRO_QM BIT(20)
39 #define MTK_WED_RESET_RX_ROUTE_QM BIT(21)
40 #define MTK_WED_RESET_WED BIT(31)
43 #define MTK_WED_CTRL_WPDMA_INT_AGENT_EN BIT(0)
44 #define MTK_WED_CTRL_WPDMA_INT_AGENT_BUSY BIT(1)
45 #define MTK_WED_CTRL_WDMA_INT_AGENT_EN BIT(2)
46 #define MTK_WED_CTRL_WDMA_INT_AGENT_BUSY BIT(3)
47 #define MTK_WED_CTRL_WED_TX_BM_EN BIT(8)
48 #define MTK_WED_CTRL_WED_TX_BM_BUSY BIT(9)
49 #define MTK_WED_CTRL_WED_TX_FREE_AGENT_EN BIT(10)
50 #define MTK_WED_CTRL_WED_TX_FREE_AGENT_BUSY BIT(11)
51 #define MTK_WED_CTRL_WED_RX_BM_EN BIT(12)
52 #define MTK_WED_CTRL_WED_RX_BM_BUSY BIT(13)
53 #define MTK_WED_CTRL_RX_RRO_QM_EN BIT(14)
54 #define MTK_WED_CTRL_RX_RRO_QM_BUSY BIT(15)
55 #define MTK_WED_CTRL_RX_ROUTE_QM_EN BIT(16)
56 #define MTK_WED_CTRL_RX_ROUTE_QM_BUSY BIT(17)
57 #define MTK_WED_CTRL_FINAL_DIDX_READ BIT(24)
58 #define MTK_WED_CTRL_ETH_DMAD_FMT BIT(25)
59 #define MTK_WED_CTRL_MIB_READ_CLEAR BIT(28)
62 #define MTK_WED_EXT_INT_STATUS_TF_LEN_ERR BIT(0)
63 #define MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD BIT(1)
64 #define MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID BIT(4)
65 #define MTK_WED_EXT_INT_STATUS_TX_FBUF_LO_TH BIT(8)
66 #define MTK_WED_EXT_INT_STATUS_TX_FBUF_HI_TH BIT(9)
67 #define MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH BIT(10) /* wed v2 */
68 #define MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH BIT(11) /* wed v2 */
69 #define MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR BIT(16)
70 #define MTK_WED_EXT_INT_STATUS_RX_DRV_W_RESP_ERR BIT(17)
71 #define MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT BIT(18)
72 #define MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN BIT(19)
73 #define MTK_WED_EXT_INT_STATUS_RX_DRV_BM_DMAD_COHERENT BIT(20)
74 #define MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR BIT(21)
75 #define MTK_WED_EXT_INT_STATUS_TX_DMA_R_RESP_ERR BIT(22)
76 #define MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR BIT(23)
77 #define MTK_WED_EXT_INT_STATUS_RX_DRV_DMA_RECYCLE BIT(24)
78 #define MTK_WED_EXT_INT_STATUS_RX_DRV_GET_BM_DMAD_SKIP BIT(25)
79 #define MTK_WED_EXT_INT_STATUS_WPDMA_RX_D_DRV_ERR BIT(26)
80 #define MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY BIT(27)
98 #define MTK_WED_TX_BM_CTRL_RSV_GRP_NUM GENMASK(22, 16)
99 #define MTK_WED_TX_BM_CTRL_PAUSE BIT(28)
106 #define MTK_WED_TX_BM_TKID_END GENMASK(31, 16)
112 #define MTK_WED_TX_BM_INTF_TKFIFO_FDEP GENMASK(23, 16)
113 #define MTK_WED_TX_BM_INTF_TKID_VALID BIT(28)
114 #define MTK_WED_TX_BM_INTF_TKID_READ BIT(29)
119 #define MTK_WED_TX_BM_DYN_THR_HI GENMASK(22, 16)
120 #define MTK_WED_TX_BM_DYN_THR_HI_V2 GENMASK(24, 16)
124 #define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM GENMASK(22, 16)
125 #define MTK_WED_TX_TKID_CTRL_PAUSE BIT(28)
129 #define MTK_WED_TX_TKID_DYN_THR_HI GENMASK(22, 16)
133 #define MTK_WED_WPDMA_WRITE_TXP GENMASK(31, 16)
135 #define MTK_WED_TXDP_DW9_OVERWR BIT(9)
142 #define MTK_WED_GLO_CFG_TX_DMA_EN BIT(0)
143 #define MTK_WED_GLO_CFG_TX_DMA_BUSY BIT(1)
144 #define MTK_WED_GLO_CFG_RX_DMA_EN BIT(2)
145 #define MTK_WED_GLO_CFG_RX_DMA_BUSY BIT(3)
147 #define MTK_WED_GLO_CFG_TX_WB_DDONE BIT(6)
148 #define MTK_WED_GLO_CFG_BIG_ENDIAN BIT(7)
149 #define MTK_WED_GLO_CFG_DIS_BT_SIZE_ALIGN BIT(8)
150 #define MTK_WED_GLO_CFG_TX_BT_SIZE_LO BIT(9)
152 #define MTK_WED_GLO_CFG_FIFO_LITTLE_ENDIAN BIT(12)
155 #define MTK_WED_GLO_CFG_SW_RESET BIT(24)
156 #define MTK_WED_GLO_CFG_FIRST_TOKEN_ONLY BIT(26)
157 #define MTK_WED_GLO_CFG_OMIT_RX_INFO BIT(27)
158 #define MTK_WED_GLO_CFG_OMIT_TX_INFO BIT(28)
159 #define MTK_WED_GLO_CFG_BYTE_SWAP BIT(29)
160 #define MTK_WED_GLO_CFG_RX_2B_OFFSET BIT(31)
164 #define MTK_WED_RESET_IDX_RX GENMASK(17, 16)
178 #define MTK_WED_WPDMA_INT_TRIGGER_RX_DONE BIT(1)
182 #define MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN BIT(0)
183 #define MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY BIT(1)
184 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN BIT(2)
185 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_BUSY BIT(3)
187 #define MTK_WED_WPDMA_GLO_CFG_TX_WB_DDONE BIT(6)
188 #define MTK_WED_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7)
189 #define MTK_WED_WPDMA_GLO_CFG_DIS_BT_SIZE_ALIGN BIT(8)
190 #define MTK_WED_WPDMA_GLO_CFG_TX_BT_SIZE_LO BIT(9)
192 #define MTK_WED_WPDMA_GLO_CFG_FIFO_LITTLE_ENDIAN BIT(12)
195 #define MTK_WED_WPDMA_GLO_CFG_SW_RESET BIT(24)
196 #define MTK_WED_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY BIT(26)
197 #define MTK_WED_WPDMA_GLO_CFG_OMIT_RX_INFO BIT(27)
198 #define MTK_WED_WPDMA_GLO_CFG_OMIT_TX_INFO BIT(28)
199 #define MTK_WED_WPDMA_GLO_CFG_BYTE_SWAP BIT(29)
200 #define MTK_WED_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31)
203 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC BIT(4)
204 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_PKT_PROC BIT(5)
205 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC BIT(6)
206 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_CRX_SYNC BIT(7)
207 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_VER GENMASK(18, 16)
208 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNSUPPORT_FMT BIT(19)
209 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UEVENT_PKT_FMT_CHK BIT(20)
210 #define MTK_WED_WPDMA_GLO_CFG_RX_DDONE2_WR BIT(21)
211 #define MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP BIT(24)
212 #define MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV BIT(28)
216 #define MTK_WED_WPDMA_RESET_IDX_RX GENMASK(17, 16)
219 #define MTK_WED_WPDMA_CTRL_SDL1_FIXED BIT(31)
222 #define MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV BIT(21)
223 #define MTK_WED_WPDMA_INT_CTRL_SIG_SRC BIT(22)
224 #define MTK_WED_WPDMA_INT_CTRL_SRC_SEL GENMASK(17, 16)
229 #define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN BIT(0)
230 #define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_CLR BIT(1)
232 #define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_EN BIT(8)
233 #define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_CLR BIT(9)
237 #define MTK_WED_WPDMA_INT_CTRL_RX0_EN BIT(0)
238 #define MTK_WED_WPDMA_INT_CTRL_RX0_CLR BIT(1)
240 #define MTK_WED_WPDMA_INT_CTRL_RX1_EN BIT(8)
241 #define MTK_WED_WPDMA_INT_CTRL_RX1_CLR BIT(9)
245 #define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_EN BIT(0)
246 #define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_CLR BIT(1)
255 #define MTK_WED_PCIE_INT_TRIGGER_STATUS BIT(16)
258 #define MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA BIT(20)
259 #define MTK_WED_PCIE_INT_CTRL_SRC_SEL GENMASK(17, 16)
277 #define MTK_WED_WPDMA_RX_D_RX_DRV_EN BIT(0)
278 #define MTK_WED_WPDMA_RX_D_RX_DRV_BUSY BIT(1)
279 #define MTK_WED_WPDMA_RX_D_FSM_RETURN_IDLE BIT(3)
280 #define MTK_WED_WPDMA_RX_D_RST_INIT_COMPLETE BIT(4)
285 #define MTK_WED_WPDMA_RX_D_RST_CRX_IDX GENMASK(17, 16)
303 #define MTK_WED_WDMA_GLO_CFG_TX_DRV_EN BIT(0)
304 #define MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK BIT(1)
305 #define MTK_WED_WDMA_GLO_CFG_RX_DRV_EN BIT(2)
306 #define MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY BIT(3)
308 #define MTK_WED_WDMA_GLO_CFG_TX_WB_DDONE BIT(6)
309 #define MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE BIT(13)
310 #define MTK_WED_WDMA_GLO_CFG_WCOMPLETE_SEL BIT(16)
311 #define MTK_WED_WDMA_GLO_CFG_INIT_PHASE_RXDMA_BYPASS BIT(17)
312 #define MTK_WED_WDMA_GLO_CFG_INIT_PHASE_BYPASS BIT(18)
313 #define MTK_WED_WDMA_GLO_CFG_FSM_RETURN_IDLE BIT(19)
314 #define MTK_WED_WDMA_GLO_CFG_WAIT_COHERENT BIT(20)
315 #define MTK_WED_WDMA_GLO_CFG_AXI_W_AFTER_AW BIT(21)
316 #define MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY_SINGLE_W BIT(22)
317 #define MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY BIT(23)
318 #define MTK_WED_WDMA_GLO_CFG_DYNAMIC_SKIP_DMAD_PREP BIT(24)
319 #define MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE BIT(25)
320 #define MTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE BIT(26)
321 #define MTK_WED_WDMA_GLO_CFG_RXDRV_CLKGATE_BYPASS BIT(30)
324 #define MTK_WED_WDMA_RESET_IDX_RX GENMASK(17, 16)
328 #define MTK_WED_WDMA_INT_CLR_RX_DONE GENMASK(17, 16)
331 #define MTK_WED_WDMA_INT_TRIGGER_RX_DONE GENMASK(17, 16)
334 #define MTK_WED_WDMA_INT_CTRL_POLL_SRC_SEL GENMASK(17, 16)
341 #define MTK_WED_WDMA_OFST0_GLO_CFG GENMASK(31, 16)
343 #define MTK_WED_WDMA_OFST1_RX_CTRL GENMASK(31, 16)
355 #define MTK_WED_RX_BM_INIT_SW_TAIL BIT(16)
360 #define MTK_WED_RX_BM_DYN_ALLOC_TH_H GENMASK(31, 16)
372 #define MTK_WDMA_GLO_CFG_TX_DMA_EN BIT(0)
373 #define MTK_WDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
374 #define MTK_WDMA_GLO_CFG_RX_DMA_EN BIT(2)
375 #define MTK_WDMA_GLO_CFG_RX_DMA_BUSY BIT(3)
376 #define MTK_WDMA_GLO_CFG_RX_INFO3_PRERES BIT(26)
377 #define MTK_WDMA_GLO_CFG_RX_INFO2_PRERES BIT(27)
378 #define MTK_WDMA_GLO_CFG_RX_INFO1_PRERES BIT(28)
382 #define MTK_WDMA_RESET_IDX_RX GENMASK(17, 16)
388 #define MTK_WDMA_INT_MASK_RX_DONE GENMASK(17, 16)
389 #define MTK_WDMA_INT_MASK_TX_DELAY BIT(28)
390 #define MTK_WDMA_INT_MASK_TX_COHERENT BIT(29)
391 #define MTK_WDMA_INT_MASK_RX_DELAY BIT(30)
392 #define MTK_WDMA_INT_MASK_RX_COHERENT BIT(31)
398 #define MTK_PCIE_MIRROR_MAP_EN BIT(0)
399 #define MTK_PCIE_MIRROR_MAP_WED_ID BIT(1)
405 #define MTK_WED_RTQM_BUSY BIT(1)
406 #define MTK_WED_RTQM_Q_RST BIT(2)
407 #define MTK_WED_RTQM_Q_DBG_BYPASS BIT(5)
420 #define MTK_WED_RROQM_RST_IDX_MIOD BIT(0)
421 #define MTK_WED_RROQM_RST_IDX_FDBK BIT(4)
442 #define MTK_WED_RROQM_MIOD_ENTRY_DW GENMASK(22, 16)
458 #define MTK_WED_RX_BM_PTR_HEAD GENMASK(32, 16)