1c8846e10SFelix Fietkau /* SPDX-License-Identifier: ISC */ 2c8846e10SFelix Fietkau 3c8846e10SFelix Fietkau #ifndef __MT7603_REGS_H 4c8846e10SFelix Fietkau #define __MT7603_REGS_H 5c8846e10SFelix Fietkau 6c8846e10SFelix Fietkau #define MT_HW_REV 0x1000 7c8846e10SFelix Fietkau #define MT_HW_CHIPID 0x1008 8c8846e10SFelix Fietkau #define MT_TOP_MISC2 0x1134 9c8846e10SFelix Fietkau 10c8846e10SFelix Fietkau #define MT_MCU_BASE 0x2000 11c8846e10SFelix Fietkau #define MT_MCU(ofs) (MT_MCU_BASE + (ofs)) 12c8846e10SFelix Fietkau 13c8846e10SFelix Fietkau #define MT_MCU_PCIE_REMAP_1 MT_MCU(0x500) 14c8846e10SFelix Fietkau #define MT_MCU_PCIE_REMAP_1_OFFSET GENMASK(17, 0) 15c8846e10SFelix Fietkau #define MT_MCU_PCIE_REMAP_1_BASE GENMASK(31, 18) 16c8846e10SFelix Fietkau 17c8846e10SFelix Fietkau #define MT_MCU_PCIE_REMAP_2 MT_MCU(0x504) 18c8846e10SFelix Fietkau #define MT_MCU_PCIE_REMAP_2_OFFSET GENMASK(18, 0) 19c8846e10SFelix Fietkau #define MT_MCU_PCIE_REMAP_2_BASE GENMASK(31, 19) 20c8846e10SFelix Fietkau 21c8846e10SFelix Fietkau #define MT_HIF_BASE 0x4000 22c8846e10SFelix Fietkau #define MT_HIF(ofs) (MT_HIF_BASE + (ofs)) 23c8846e10SFelix Fietkau 24c8846e10SFelix Fietkau #define MT_INT_SOURCE_CSR MT_HIF(0x200) 25c8846e10SFelix Fietkau #define MT_INT_MASK_CSR MT_HIF(0x204) 26c8846e10SFelix Fietkau #define MT_DELAY_INT_CFG MT_HIF(0x210) 27c8846e10SFelix Fietkau 28c8846e10SFelix Fietkau #define MT_INT_RX_DONE(_n) BIT(_n) 29c8846e10SFelix Fietkau #define MT_INT_RX_DONE_ALL GENMASK(1, 0) 30c8846e10SFelix Fietkau #define MT_INT_TX_DONE_ALL GENMASK(19, 4) 31c8846e10SFelix Fietkau #define MT_INT_TX_DONE(_n) BIT((_n) + 4) 32c8846e10SFelix Fietkau 33c8846e10SFelix Fietkau #define MT_INT_RX_COHERENT BIT(20) 34c8846e10SFelix Fietkau #define MT_INT_TX_COHERENT BIT(21) 35c8846e10SFelix Fietkau #define MT_INT_MAC_IRQ3 BIT(27) 36c8846e10SFelix Fietkau 37c8846e10SFelix Fietkau #define MT_INT_MCU_CMD BIT(30) 38c8846e10SFelix Fietkau 39c8846e10SFelix Fietkau #define MT_WPDMA_GLO_CFG MT_HIF(0x208) 40c8846e10SFelix Fietkau #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0) 41c8846e10SFelix Fietkau #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1) 42c8846e10SFelix Fietkau #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2) 43c8846e10SFelix Fietkau #define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3) 44c8846e10SFelix Fietkau #define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4) 45c8846e10SFelix Fietkau #define MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE BIT(6) 46c8846e10SFelix Fietkau #define MT_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7) 47c8846e10SFelix Fietkau #define MT_WPDMA_GLO_CFG_HDR_SEG_LEN GENMASK(15, 8) 48c8846e10SFelix Fietkau #define MT_WPDMA_GLO_CFG_SW_RESET BIT(24) 49c8846e10SFelix Fietkau #define MT_WPDMA_GLO_CFG_FORCE_TX_EOF BIT(25) 50c8846e10SFelix Fietkau #define MT_WPDMA_GLO_CFG_CLK_GATE_DIS BIT(30) 51c8846e10SFelix Fietkau #define MT_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31) 52c8846e10SFelix Fietkau 53c8846e10SFelix Fietkau #define MT_WPDMA_RST_IDX MT_HIF(0x20c) 54c8846e10SFelix Fietkau 55c8846e10SFelix Fietkau #define MT_WPDMA_DEBUG MT_HIF(0x244) 56c8846e10SFelix Fietkau #define MT_WPDMA_DEBUG_VALUE GENMASK(17, 0) 57c8846e10SFelix Fietkau #define MT_WPDMA_DEBUG_SEL BIT(27) 58c8846e10SFelix Fietkau #define MT_WPDMA_DEBUG_IDX GENMASK(31, 28) 59c8846e10SFelix Fietkau 60c8846e10SFelix Fietkau #define MT_TX_RING_BASE MT_HIF(0x300) 61c8846e10SFelix Fietkau #define MT_RX_RING_BASE MT_HIF(0x400) 62c8846e10SFelix Fietkau 63c8846e10SFelix Fietkau #define MT_TXTIME_THRESH_BASE MT_HIF(0x500) 64c8846e10SFelix Fietkau #define MT_TXTIME_THRESH(n) (MT_TXTIME_THRESH_BASE + ((n) * 4)) 65c8846e10SFelix Fietkau 66c8846e10SFelix Fietkau #define MT_PAGE_COUNT_BASE MT_HIF(0x540) 67c8846e10SFelix Fietkau #define MT_PAGE_COUNT(n) (MT_PAGE_COUNT_BASE + ((n) * 4)) 68c8846e10SFelix Fietkau 69c8846e10SFelix Fietkau #define MT_SCH_1 MT_HIF(0x588) 70c8846e10SFelix Fietkau #define MT_SCH_2 MT_HIF(0x58c) 71c8846e10SFelix Fietkau #define MT_SCH_3 MT_HIF(0x590) 72c8846e10SFelix Fietkau 73c8846e10SFelix Fietkau #define MT_SCH_4 MT_HIF(0x594) 74c8846e10SFelix Fietkau #define MT_SCH_4_FORCE_QID GENMASK(4, 0) 75c8846e10SFelix Fietkau #define MT_SCH_4_BYPASS BIT(5) 76c8846e10SFelix Fietkau #define MT_SCH_4_RESET BIT(8) 77c8846e10SFelix Fietkau 78c8846e10SFelix Fietkau #define MT_GROUP_THRESH_BASE MT_HIF(0x598) 79c8846e10SFelix Fietkau #define MT_GROUP_THRESH(n) (MT_GROUP_THRESH_BASE + ((n) * 4)) 80c8846e10SFelix Fietkau 81c8846e10SFelix Fietkau #define MT_QUEUE_PRIORITY_1 MT_HIF(0x580) 82c8846e10SFelix Fietkau #define MT_QUEUE_PRIORITY_2 MT_HIF(0x584) 83c8846e10SFelix Fietkau 84c8846e10SFelix Fietkau #define MT_BMAP_0 MT_HIF(0x5b0) 85c8846e10SFelix Fietkau #define MT_BMAP_1 MT_HIF(0x5b4) 86c8846e10SFelix Fietkau #define MT_BMAP_2 MT_HIF(0x5b8) 87c8846e10SFelix Fietkau 88c8846e10SFelix Fietkau #define MT_HIGH_PRIORITY_1 MT_HIF(0x5bc) 89c8846e10SFelix Fietkau #define MT_HIGH_PRIORITY_2 MT_HIF(0x5c0) 90c8846e10SFelix Fietkau 91c8846e10SFelix Fietkau #define MT_PRIORITY_MASK MT_HIF(0x5c4) 92c8846e10SFelix Fietkau 93c8846e10SFelix Fietkau #define MT_RSV_MAX_THRESH MT_HIF(0x5c8) 94c8846e10SFelix Fietkau 95c8846e10SFelix Fietkau #define MT_PSE_BASE 0x8000 96c8846e10SFelix Fietkau #define MT_PSE(ofs) (MT_PSE_BASE + (ofs)) 97c8846e10SFelix Fietkau 98c8846e10SFelix Fietkau #define MT_MCU_DEBUG_RESET MT_PSE(0x16c) 99c8846e10SFelix Fietkau #define MT_MCU_DEBUG_RESET_PSE BIT(0) 100c8846e10SFelix Fietkau #define MT_MCU_DEBUG_RESET_PSE_S BIT(1) 101c8846e10SFelix Fietkau #define MT_MCU_DEBUG_RESET_QUEUES GENMASK(6, 2) 102c8846e10SFelix Fietkau 103c8846e10SFelix Fietkau #define MT_PSE_FC_P0 MT_PSE(0x120) 104c8846e10SFelix Fietkau #define MT_PSE_FC_P0_MIN_RESERVE GENMASK(11, 0) 105c8846e10SFelix Fietkau #define MT_PSE_FC_P0_MAX_QUOTA GENMASK(27, 16) 106c8846e10SFelix Fietkau 107c8846e10SFelix Fietkau #define MT_PSE_FRP MT_PSE(0x138) 108c8846e10SFelix Fietkau #define MT_PSE_FRP_P0 GENMASK(2, 0) 109c8846e10SFelix Fietkau #define MT_PSE_FRP_P1 GENMASK(5, 3) 110c8846e10SFelix Fietkau #define MT_PSE_FRP_P2_RQ0 GENMASK(8, 6) 111c8846e10SFelix Fietkau #define MT_PSE_FRP_P2_RQ1 GENMASK(11, 9) 112c8846e10SFelix Fietkau #define MT_PSE_FRP_P2_RQ2 GENMASK(14, 12) 113c8846e10SFelix Fietkau 114c8846e10SFelix Fietkau #define MT_FC_RSV_COUNT_0 MT_PSE(0x13c) 115c8846e10SFelix Fietkau #define MT_FC_RSV_COUNT_0_P0 GENMASK(11, 0) 116c8846e10SFelix Fietkau #define MT_FC_RSV_COUNT_0_P1 GENMASK(27, 16) 117c8846e10SFelix Fietkau 118c8846e10SFelix Fietkau #define MT_FC_SP2_Q0Q1 MT_PSE(0x14c) 119c8846e10SFelix Fietkau #define MT_FC_SP2_Q0Q1_SRC_COUNT_Q0 GENMASK(11, 0) 120c8846e10SFelix Fietkau #define MT_FC_SP2_Q0Q1_SRC_COUNT_Q1 GENMASK(27, 16) 121c8846e10SFelix Fietkau 122c8846e10SFelix Fietkau #define MT_PSE_FW_SHARED MT_PSE(0x17c) 123c8846e10SFelix Fietkau 124c8846e10SFelix Fietkau #define MT_PSE_RTA MT_PSE(0x194) 125c8846e10SFelix Fietkau #define MT_PSE_RTA_QUEUE_ID GENMASK(4, 0) 126c8846e10SFelix Fietkau #define MT_PSE_RTA_PORT_ID GENMASK(6, 5) 127c8846e10SFelix Fietkau #define MT_PSE_RTA_REDIRECT_EN BIT(7) 128c8846e10SFelix Fietkau #define MT_PSE_RTA_TAG_ID GENMASK(15, 8) 129c8846e10SFelix Fietkau #define MT_PSE_RTA_WRITE BIT(16) 130c8846e10SFelix Fietkau #define MT_PSE_RTA_BUSY BIT(31) 131c8846e10SFelix Fietkau 132c8846e10SFelix Fietkau #define MT_WF_PHY_BASE 0x10000 133c8846e10SFelix Fietkau #define MT_WF_PHY_OFFSET 0x1000 134c8846e10SFelix Fietkau #define MT_WF_PHY(ofs) (MT_WF_PHY_BASE + (ofs)) 135c8846e10SFelix Fietkau 136c8846e10SFelix Fietkau #define MT_AGC_BASE MT_WF_PHY(0x500) 137c8846e10SFelix Fietkau #define MT_AGC(n) (MT_AGC_BASE + ((n) * 4)) 138c8846e10SFelix Fietkau 139c8846e10SFelix Fietkau #define MT_AGC1_BASE MT_WF_PHY(0x1500) 140c8846e10SFelix Fietkau #define MT_AGC1(n) (MT_AGC1_BASE + ((n) * 4)) 141c8846e10SFelix Fietkau 142c8846e10SFelix Fietkau #define MT_AGC_41_RSSI_0 GENMASK(23, 16) 143c8846e10SFelix Fietkau #define MT_AGC_41_RSSI_1 GENMASK(7, 0) 144c8846e10SFelix Fietkau 145c8846e10SFelix Fietkau #define MT_RXTD_BASE MT_WF_PHY(0x600) 146c8846e10SFelix Fietkau #define MT_RXTD(n) (MT_RXTD_BASE + ((n) * 4)) 147c8846e10SFelix Fietkau 148c8846e10SFelix Fietkau #define MT_RXTD_6_ACI_TH GENMASK(4, 0) 149c8846e10SFelix Fietkau #define MT_RXTD_6_CCAED_TH GENMASK(14, 8) 150c8846e10SFelix Fietkau 151c8846e10SFelix Fietkau #define MT_RXTD_8_LOWER_SIGNAL GENMASK(5, 0) 152c8846e10SFelix Fietkau 153c8846e10SFelix Fietkau #define MT_RXTD_13_ACI_TH_EN BIT(0) 154c8846e10SFelix Fietkau 155c8846e10SFelix Fietkau #define MT_WF_PHY_CR_TSSI_BASE MT_WF_PHY(0xd00) 156c8846e10SFelix Fietkau #define MT_WF_PHY_CR_TSSI(phy, n) (MT_WF_PHY_CR_TSSI_BASE + \ 157c8846e10SFelix Fietkau ((phy) * MT_WF_PHY_OFFSET) + \ 158c8846e10SFelix Fietkau ((n) * 4)) 159c8846e10SFelix Fietkau 160c8846e10SFelix Fietkau #define MT_PHYCTRL_BASE MT_WF_PHY(0x4100) 161c8846e10SFelix Fietkau #define MT_PHYCTRL(n) (MT_PHYCTRL_BASE + ((n) * 4)) 162c8846e10SFelix Fietkau 163c8846e10SFelix Fietkau #define MT_PHYCTRL_2_STATUS_RESET BIT(6) 164c8846e10SFelix Fietkau #define MT_PHYCTRL_2_STATUS_EN BIT(7) 165c8846e10SFelix Fietkau 166c8846e10SFelix Fietkau #define MT_PHYCTRL_STAT_PD MT_PHYCTRL(3) 167c8846e10SFelix Fietkau #define MT_PHYCTRL_STAT_PD_OFDM GENMASK(31, 16) 168c8846e10SFelix Fietkau #define MT_PHYCTRL_STAT_PD_CCK GENMASK(15, 0) 169c8846e10SFelix Fietkau 170c8846e10SFelix Fietkau #define MT_PHYCTRL_STAT_MDRDY MT_PHYCTRL(8) 171c8846e10SFelix Fietkau #define MT_PHYCTRL_STAT_MDRDY_OFDM GENMASK(31, 16) 172c8846e10SFelix Fietkau #define MT_PHYCTRL_STAT_MDRDY_CCK GENMASK(15, 0) 173c8846e10SFelix Fietkau 174c8846e10SFelix Fietkau #define MT_WF_AGG_BASE 0x21200 175c8846e10SFelix Fietkau #define MT_WF_AGG(ofs) (MT_WF_AGG_BASE + (ofs)) 176c8846e10SFelix Fietkau 177c8846e10SFelix Fietkau #define MT_AGG_ARCR MT_WF_AGG(0x010) 178c8846e10SFelix Fietkau #define MT_AGG_ARCR_INIT_RATE1 BIT(0) 179c8846e10SFelix Fietkau #define MT_AGG_ARCR_FB_SGI_DISABLE BIT(1) 180c8846e10SFelix Fietkau #define MT_AGG_ARCR_RATE8_DOWN_WRAP BIT(2) 181c8846e10SFelix Fietkau #define MT_AGG_ARCR_RTS_RATE_THR GENMASK(12, 8) 182c8846e10SFelix Fietkau #define MT_AGG_ARCR_RATE_DOWN_RATIO GENMASK(17, 16) 183c8846e10SFelix Fietkau #define MT_AGG_ARCR_RATE_DOWN_RATIO_EN BIT(19) 184c8846e10SFelix Fietkau #define MT_AGG_ARCR_RATE_UP_EXTRA_TH GENMASK(22, 20) 185c8846e10SFelix Fietkau #define MT_AGG_ARCR_SPE_DIS_TH GENMASK(27, 24) 186c8846e10SFelix Fietkau 187c8846e10SFelix Fietkau #define MT_AGG_ARUCR MT_WF_AGG(0x014) 188c8846e10SFelix Fietkau #define MT_AGG_ARDCR MT_WF_AGG(0x018) 189c8846e10SFelix Fietkau #define MT_AGG_ARxCR_LIMIT_SHIFT(_n) (4 * (_n)) 190c8846e10SFelix Fietkau #define MT_AGG_ARxCR_LIMIT(_n) GENMASK(2 + \ 191c8846e10SFelix Fietkau MT_AGG_ARxCR_LIMIT_SHIFT(_n), \ 192c8846e10SFelix Fietkau MT_AGG_ARxCR_LIMIT_SHIFT(_n)) 193c8846e10SFelix Fietkau 194c8846e10SFelix Fietkau #define MT_AGG_LIMIT MT_WF_AGG(0x040) 195c8846e10SFelix Fietkau #define MT_AGG_LIMIT_1 MT_WF_AGG(0x044) 196c8846e10SFelix Fietkau #define MT_AGG_LIMIT_AC(_n) GENMASK(((_n) + 1) * 8 - 1, (_n) * 8) 197c8846e10SFelix Fietkau 198c8846e10SFelix Fietkau #define MT_AGG_BA_SIZE_LIMIT_0 MT_WF_AGG(0x048) 199c8846e10SFelix Fietkau #define MT_AGG_BA_SIZE_LIMIT_1 MT_WF_AGG(0x04c) 200c8846e10SFelix Fietkau #define MT_AGG_BA_SIZE_LIMIT_SHIFT 8 201c8846e10SFelix Fietkau 202c8846e10SFelix Fietkau #define MT_AGG_PCR MT_WF_AGG(0x050) 203c8846e10SFelix Fietkau #define MT_AGG_PCR_MM BIT(16) 204c8846e10SFelix Fietkau #define MT_AGG_PCR_GF BIT(17) 205c8846e10SFelix Fietkau #define MT_AGG_PCR_BW40 BIT(18) 206c8846e10SFelix Fietkau #define MT_AGG_PCR_RIFS BIT(19) 207c8846e10SFelix Fietkau #define MT_AGG_PCR_BW80 BIT(20) 208c8846e10SFelix Fietkau #define MT_AGG_PCR_BW160 BIT(21) 209c8846e10SFelix Fietkau #define MT_AGG_PCR_ERP BIT(22) 210c8846e10SFelix Fietkau 211c8846e10SFelix Fietkau #define MT_AGG_PCR_RTS MT_WF_AGG(0x054) 212c8846e10SFelix Fietkau #define MT_AGG_PCR_RTS_THR GENMASK(19, 0) 213c8846e10SFelix Fietkau #define MT_AGG_PCR_RTS_PKT_THR GENMASK(31, 25) 214c8846e10SFelix Fietkau 2155a8d4678SLorenzo Bianconi #define MT_AGG_ASRCR MT_WF_AGG(0x060) 2165a8d4678SLorenzo Bianconi #define MT_AGG_ASRCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(5, 0)) 2175a8d4678SLorenzo Bianconi 218c8846e10SFelix Fietkau #define MT_AGG_CONTROL MT_WF_AGG(0x070) 219c8846e10SFelix Fietkau #define MT_AGG_CONTROL_NO_BA_RULE BIT(0) 220c8846e10SFelix Fietkau #define MT_AGG_CONTROL_NO_BA_AR_RULE BIT(1) 221c8846e10SFelix Fietkau #define MT_AGG_CONTROL_CFEND_SPE_EN BIT(3) 222c8846e10SFelix Fietkau #define MT_AGG_CONTROL_CFEND_RATE GENMASK(15, 4) 223c8846e10SFelix Fietkau #define MT_AGG_CONTROL_BAR_SPE_EN BIT(19) 224c8846e10SFelix Fietkau #define MT_AGG_CONTROL_BAR_RATE GENMASK(31, 20) 225c8846e10SFelix Fietkau 226c8846e10SFelix Fietkau #define MT_AGG_TMP MT_WF_AGG(0x0d8) 227c8846e10SFelix Fietkau 228c8846e10SFelix Fietkau #define MT_AGG_BWCR MT_WF_AGG(0x0ec) 229c8846e10SFelix Fietkau #define MT_AGG_BWCR_BW GENMASK(3, 2) 230c8846e10SFelix Fietkau 231c8846e10SFelix Fietkau #define MT_AGG_RETRY_CONTROL MT_WF_AGG(0x0f4) 232c8846e10SFelix Fietkau #define MT_AGG_RETRY_CONTROL_RTS_LIMIT GENMASK(11, 7) 233c8846e10SFelix Fietkau #define MT_AGG_RETRY_CONTROL_BAR_LIMIT GENMASK(15, 12) 234c8846e10SFelix Fietkau 235c8846e10SFelix Fietkau #define MT_WF_DMA_BASE 0x21c00 236c8846e10SFelix Fietkau #define MT_WF_DMA(ofs) (MT_WF_DMA_BASE + (ofs)) 237c8846e10SFelix Fietkau 238c8846e10SFelix Fietkau #define MT_DMA_DCR0 MT_WF_DMA(0x000) 2390f66947bSFelix Fietkau #define MT_DMA_DCR0_MAX_RX_LEN GENMASK(15, 0) 2400f66947bSFelix Fietkau #define MT_DMA_DCR0_DAMSDU BIT(16) 2410f66947bSFelix Fietkau #define MT_DMA_DCR0_RX_VEC_DROP BIT(17) 2420f66947bSFelix Fietkau 243c8846e10SFelix Fietkau #define MT_DMA_DCR1 MT_WF_DMA(0x004) 244c8846e10SFelix Fietkau 245c8846e10SFelix Fietkau #define MT_DMA_FQCR0 MT_WF_DMA(0x008) 246c8846e10SFelix Fietkau #define MT_DMA_FQCR0_TARGET_WCID GENMASK(7, 0) 247c8846e10SFelix Fietkau #define MT_DMA_FQCR0_TARGET_BSS GENMASK(13, 8) 248c8846e10SFelix Fietkau #define MT_DMA_FQCR0_TARGET_QID GENMASK(20, 16) 249c8846e10SFelix Fietkau #define MT_DMA_FQCR0_DEST_PORT_ID GENMASK(23, 22) 250c8846e10SFelix Fietkau #define MT_DMA_FQCR0_DEST_QUEUE_ID GENMASK(28, 24) 251c8846e10SFelix Fietkau #define MT_DMA_FQCR0_MODE BIT(29) 252c8846e10SFelix Fietkau #define MT_DMA_FQCR0_STATUS BIT(30) 253c8846e10SFelix Fietkau #define MT_DMA_FQCR0_BUSY BIT(31) 254c8846e10SFelix Fietkau 255c8846e10SFelix Fietkau #define MT_DMA_RCFR0 MT_WF_DMA(0x070) 256c8846e10SFelix Fietkau #define MT_DMA_VCFR0 MT_WF_DMA(0x07c) 257c8846e10SFelix Fietkau 258c8846e10SFelix Fietkau #define MT_DMA_TCFR0 MT_WF_DMA(0x080) 259c8846e10SFelix Fietkau #define MT_DMA_TCFR1 MT_WF_DMA(0x084) 260c8846e10SFelix Fietkau #define MT_DMA_TCFR_TXS_AGGR_TIMEOUT GENMASK(27, 16) 261c8846e10SFelix Fietkau #define MT_DMA_TCFR_TXS_QUEUE BIT(14) 262c8846e10SFelix Fietkau #define MT_DMA_TCFR_TXS_AGGR_COUNT GENMASK(12, 8) 263c8846e10SFelix Fietkau #define MT_DMA_TCFR_TXS_BIT_MAP GENMASK(6, 0) 264c8846e10SFelix Fietkau 265c8846e10SFelix Fietkau #define MT_DMA_TMCFR0 MT_WF_DMA(0x088) 266c8846e10SFelix Fietkau 267c8846e10SFelix Fietkau #define MT_WF_ARB_BASE 0x21400 268c8846e10SFelix Fietkau #define MT_WF_ARB(ofs) (MT_WF_ARB_BASE + (ofs)) 269c8846e10SFelix Fietkau 270c8846e10SFelix Fietkau #define MT_WMM_AIFSN MT_WF_ARB(0x020) 271c8846e10SFelix Fietkau #define MT_WMM_AIFSN_MASK GENMASK(3, 0) 272c8846e10SFelix Fietkau #define MT_WMM_AIFSN_SHIFT(_n) ((_n) * 4) 273c8846e10SFelix Fietkau 274c8846e10SFelix Fietkau #define MT_WMM_CWMAX_BASE MT_WF_ARB(0x028) 275c8846e10SFelix Fietkau #define MT_WMM_CWMAX(_n) (MT_WMM_CWMAX_BASE + (((_n) / 2) << 2)) 276c8846e10SFelix Fietkau #define MT_WMM_CWMAX_SHIFT(_n) (((_n) & 1) * 16) 277c8846e10SFelix Fietkau #define MT_WMM_CWMAX_MASK GENMASK(15, 0) 278c8846e10SFelix Fietkau 279c8846e10SFelix Fietkau #define MT_WMM_CWMIN MT_WF_ARB(0x040) 280c8846e10SFelix Fietkau #define MT_WMM_CWMIN_MASK GENMASK(7, 0) 281c8846e10SFelix Fietkau #define MT_WMM_CWMIN_SHIFT(_n) ((_n) * 8) 282c8846e10SFelix Fietkau 283c8846e10SFelix Fietkau #define MT_WF_ARB_RQCR MT_WF_ARB(0x070) 284c8846e10SFelix Fietkau #define MT_WF_ARB_RQCR_RX_START BIT(0) 285c8846e10SFelix Fietkau #define MT_WF_ARB_RQCR_RXV_START BIT(4) 286c8846e10SFelix Fietkau #define MT_WF_ARB_RQCR_RXV_R_EN BIT(7) 287c8846e10SFelix Fietkau #define MT_WF_ARB_RQCR_RXV_T_EN BIT(8) 288c8846e10SFelix Fietkau 289c8846e10SFelix Fietkau #define MT_ARB_SCR MT_WF_ARB(0x080) 290c8846e10SFelix Fietkau #define MT_ARB_SCR_BCNQ_OPMODE_MASK GENMASK(1, 0) 291c8846e10SFelix Fietkau #define MT_ARB_SCR_BCNQ_OPMODE_SHIFT(n) ((n) * 2) 292c8846e10SFelix Fietkau #define MT_ARB_SCR_TX_DISABLE BIT(8) 293c8846e10SFelix Fietkau #define MT_ARB_SCR_RX_DISABLE BIT(9) 294c8846e10SFelix Fietkau #define MT_ARB_SCR_BCNQ_EMPTY_SKIP BIT(28) 295c8846e10SFelix Fietkau #define MT_ARB_SCR_TTTT_BTIM_PRIO BIT(29) 296c8846e10SFelix Fietkau #define MT_ARB_SCR_TBTT_BCN_PRIO BIT(30) 297c8846e10SFelix Fietkau #define MT_ARB_SCR_TBTT_BCAST_PRIO BIT(31) 298c8846e10SFelix Fietkau 299c8846e10SFelix Fietkau enum { 300c8846e10SFelix Fietkau MT_BCNQ_OPMODE_STA = 0, 301c8846e10SFelix Fietkau MT_BCNQ_OPMODE_AP = 1, 302c8846e10SFelix Fietkau MT_BCNQ_OPMODE_ADHOC = 2, 303c8846e10SFelix Fietkau }; 304c8846e10SFelix Fietkau 305c8846e10SFelix Fietkau #define MT_WF_ARB_TX_START_0 MT_WF_ARB(0x100) 306c8846e10SFelix Fietkau #define MT_WF_ARB_TX_START_1 MT_WF_ARB(0x104) 307c8846e10SFelix Fietkau #define MT_WF_ARB_TX_FLUSH_0 MT_WF_ARB(0x108) 308c8846e10SFelix Fietkau #define MT_WF_ARB_TX_FLUSH_1 MT_WF_ARB(0x10c) 309c8846e10SFelix Fietkau #define MT_WF_ARB_TX_STOP_0 MT_WF_ARB(0x110) 310c8846e10SFelix Fietkau #define MT_WF_ARB_TX_STOP_1 MT_WF_ARB(0x114) 311c8846e10SFelix Fietkau 312fe0ea395SFelix Fietkau #define MT_WF_ARB_TX_FLUSH_AC0 BIT(0) 313fe0ea395SFelix Fietkau #define MT_WF_ARB_TX_FLUSH_AC1 BIT(5) 314fe0ea395SFelix Fietkau #define MT_WF_ARB_TX_FLUSH_AC2 BIT(10) 315fe0ea395SFelix Fietkau #define MT_WF_ARB_TX_FLUSH_AC3 BIT(16) 316fe0ea395SFelix Fietkau #define MT_WF_ARB_TX_FLUSH_AC4 BIT(21) 317fe0ea395SFelix Fietkau #define MT_WF_ARB_TX_FLUSH_AC5 BIT(26) 318fe0ea395SFelix Fietkau 319c8846e10SFelix Fietkau #define MT_WF_ARB_BCN_START MT_WF_ARB(0x118) 320c8846e10SFelix Fietkau #define MT_WF_ARB_BCN_START_BSSn(n) BIT(0 + (n)) 321c8846e10SFelix Fietkau #define MT_WF_ARB_BCN_START_T_PRE_TTTT BIT(10) 322c8846e10SFelix Fietkau #define MT_WF_ARB_BCN_START_T_TTTT BIT(11) 323c8846e10SFelix Fietkau #define MT_WF_ARB_BCN_START_T_PRE_TBTT BIT(12) 324c8846e10SFelix Fietkau #define MT_WF_ARB_BCN_START_T_TBTT BIT(13) 325c8846e10SFelix Fietkau #define MT_WF_ARB_BCN_START_T_SLOT_IDLE BIT(14) 326c8846e10SFelix Fietkau #define MT_WF_ARB_BCN_START_T_TX_START BIT(15) 327c8846e10SFelix Fietkau #define MT_WF_ARB_BCN_START_BSS0n(n) BIT((n) ? 16 + ((n) - 1) : 0) 328c8846e10SFelix Fietkau 329c8846e10SFelix Fietkau #define MT_WF_ARB_BCN_FLUSH MT_WF_ARB(0x11c) 330c8846e10SFelix Fietkau #define MT_WF_ARB_BCN_FLUSH_BSSn(n) BIT(0 + (n)) 331c8846e10SFelix Fietkau #define MT_WF_ARB_BCN_FLUSH_BSS0n(n) BIT((n) ? 16 + ((n) - 1) : 0) 332c8846e10SFelix Fietkau 333c8846e10SFelix Fietkau #define MT_WF_ARB_CAB_START MT_WF_ARB(0x120) 334c8846e10SFelix Fietkau #define MT_WF_ARB_CAB_START_BSSn(n) BIT(0 + (n)) 335c8846e10SFelix Fietkau #define MT_WF_ARB_CAB_START_BSS0n(n) BIT((n) ? 16 + ((n) - 1) : 0) 336c8846e10SFelix Fietkau 337c8846e10SFelix Fietkau #define MT_WF_ARB_CAB_FLUSH MT_WF_ARB(0x124) 338c8846e10SFelix Fietkau #define MT_WF_ARB_CAB_FLUSH_BSSn(n) BIT(0 + (n)) 339c8846e10SFelix Fietkau #define MT_WF_ARB_CAB_FLUSH_BSS0n(n) BIT((n) ? 16 + ((n) - 1) : 0) 340c8846e10SFelix Fietkau 341c8846e10SFelix Fietkau #define MT_WF_ARB_CAB_COUNT(n) MT_WF_ARB(0x128 + (n) * 4) 342c8846e10SFelix Fietkau #define MT_WF_ARB_CAB_COUNT_SHIFT 4 343c8846e10SFelix Fietkau #define MT_WF_ARB_CAB_COUNT_MASK GENMASK(3, 0) 344c8846e10SFelix Fietkau #define MT_WF_ARB_CAB_COUNT_B0_REG(n) MT_WF_ARB_CAB_COUNT(((n) > 12 ? 2 : \ 345c8846e10SFelix Fietkau ((n) > 4 ? 1 : 0))) 346c8846e10SFelix Fietkau #define MT_WF_ARB_CAB_COUNT_B0_SHIFT(n) (((n) > 12 ? (n) - 12 : \ 347c8846e10SFelix Fietkau ((n) > 4 ? (n) - 4 : \ 348c8846e10SFelix Fietkau (n) ? (n) + 3 : 0)) * 4) 349c8846e10SFelix Fietkau 350c8846e10SFelix Fietkau #define MT_TX_ABORT MT_WF_ARB(0x134) 351c8846e10SFelix Fietkau #define MT_TX_ABORT_EN BIT(0) 352c8846e10SFelix Fietkau #define MT_TX_ABORT_WCID GENMASK(15, 8) 353c8846e10SFelix Fietkau 354c8846e10SFelix Fietkau #define MT_WF_TMAC_BASE 0x21600 355c8846e10SFelix Fietkau #define MT_WF_TMAC(ofs) (MT_WF_TMAC_BASE + (ofs)) 356c8846e10SFelix Fietkau 357c8846e10SFelix Fietkau #define MT_TMAC_TCR MT_WF_TMAC(0x000) 358c8846e10SFelix Fietkau #define MT_TMAC_TCR_BLINK_SEL GENMASK(7, 6) 359c8846e10SFelix Fietkau #define MT_TMAC_TCR_PRE_RTS_GUARD GENMASK(11, 8) 360c8846e10SFelix Fietkau #define MT_TMAC_TCR_PRE_RTS_SEC_IDLE GENMASK(13, 12) 361c8846e10SFelix Fietkau #define MT_TMAC_TCR_RTS_SIGTA BIT(14) 362c8846e10SFelix Fietkau #define MT_TMAC_TCR_LDPC_OFS BIT(15) 363c8846e10SFelix Fietkau #define MT_TMAC_TCR_TX_STREAMS GENMASK(17, 16) 364c8846e10SFelix Fietkau #define MT_TMAC_TCR_SCH_IDLE_SEL GENMASK(19, 18) 365c8846e10SFelix Fietkau #define MT_TMAC_TCR_SCH_DET_PER_IOD BIT(20) 366c8846e10SFelix Fietkau #define MT_TMAC_TCR_DCH_DET_DISABLE BIT(21) 367c8846e10SFelix Fietkau #define MT_TMAC_TCR_TX_RIFS BIT(22) 368c8846e10SFelix Fietkau #define MT_TMAC_TCR_RX_RIFS_MODE BIT(23) 369c8846e10SFelix Fietkau #define MT_TMAC_TCR_TXOP_TBTT_CTL BIT(24) 370c8846e10SFelix Fietkau #define MT_TMAC_TCR_TBTT_TX_STOP_CTL BIT(25) 371c8846e10SFelix Fietkau #define MT_TMAC_TCR_TXOP_BURST_STOP BIT(26) 372c8846e10SFelix Fietkau #define MT_TMAC_TCR_RDG_RA_MODE BIT(27) 373c8846e10SFelix Fietkau #define MT_TMAC_TCR_RDG_RESP BIT(29) 374c8846e10SFelix Fietkau #define MT_TMAC_TCR_RDG_NO_PENDING BIT(30) 375c8846e10SFelix Fietkau #define MT_TMAC_TCR_SMOOTHING BIT(31) 376c8846e10SFelix Fietkau 377c8846e10SFelix Fietkau #define MT_WMM_TXOP_BASE MT_WF_TMAC(0x010) 378c8846e10SFelix Fietkau #define MT_WMM_TXOP(_n) (MT_WMM_TXOP_BASE + \ 379c8846e10SFelix Fietkau ((((_n) / 2) ^ 0x1) << 2)) 380c8846e10SFelix Fietkau #define MT_WMM_TXOP_SHIFT(_n) (((_n) & 1) * 16) 381c8846e10SFelix Fietkau #define MT_WMM_TXOP_MASK GENMASK(15, 0) 382c8846e10SFelix Fietkau 383c8846e10SFelix Fietkau #define MT_TIMEOUT_CCK MT_WF_TMAC(0x090) 384c8846e10SFelix Fietkau #define MT_TIMEOUT_OFDM MT_WF_TMAC(0x094) 385c8846e10SFelix Fietkau #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0) 386c8846e10SFelix Fietkau #define MT_TIMEOUT_VAL_CCA GENMASK(31, 16) 387c8846e10SFelix Fietkau 388c8846e10SFelix Fietkau #define MT_TXREQ MT_WF_TMAC(0x09c) 389c8846e10SFelix Fietkau #define MT_TXREQ_CCA_SRC_SEL GENMASK(31, 30) 390c8846e10SFelix Fietkau 391c8846e10SFelix Fietkau #define MT_RXREQ MT_WF_TMAC(0x0a0) 392c8846e10SFelix Fietkau #define MT_RXREQ_DELAY GENMASK(8, 0) 393c8846e10SFelix Fietkau 394c8846e10SFelix Fietkau #define MT_IFS MT_WF_TMAC(0x0a4) 395c8846e10SFelix Fietkau #define MT_IFS_EIFS GENMASK(8, 0) 396c8846e10SFelix Fietkau #define MT_IFS_RIFS GENMASK(14, 10) 397c8846e10SFelix Fietkau #define MT_IFS_SIFS GENMASK(22, 16) 398c8846e10SFelix Fietkau #define MT_IFS_SLOT GENMASK(30, 24) 399c8846e10SFelix Fietkau 400c8846e10SFelix Fietkau #define MT_TMAC_PCR MT_WF_TMAC(0x0b4) 401c8846e10SFelix Fietkau #define MT_TMAC_PCR_RATE GENMASK(8, 0) 402c8846e10SFelix Fietkau #define MT_TMAC_PCR_RATE_FIXED BIT(15) 403c8846e10SFelix Fietkau #define MT_TMAC_PCR_ANT_ID GENMASK(21, 16) 404c8846e10SFelix Fietkau #define MT_TMAC_PCR_ANT_ID_SEL BIT(22) 405c8846e10SFelix Fietkau #define MT_TMAC_PCR_SPE_EN BIT(23) 406c8846e10SFelix Fietkau #define MT_TMAC_PCR_ANT_PRI GENMASK(26, 24) 407c8846e10SFelix Fietkau #define MT_TMAC_PCR_ANT_PRI_SEL GENMASK(27) 408c8846e10SFelix Fietkau 409c8846e10SFelix Fietkau #define MT_WF_RMAC_BASE 0x21800 410c8846e10SFelix Fietkau #define MT_WF_RMAC(ofs) (MT_WF_RMAC_BASE + (ofs)) 411c8846e10SFelix Fietkau 412c8846e10SFelix Fietkau #define MT_WF_RFCR MT_WF_RMAC(0x000) 413c8846e10SFelix Fietkau #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0) 414c8846e10SFelix Fietkau #define MT_WF_RFCR_DROP_FCSFAIL BIT(1) 415c8846e10SFelix Fietkau #define MT_WF_RFCR_DROP_VERSION BIT(3) 416c8846e10SFelix Fietkau #define MT_WF_RFCR_DROP_PROBEREQ BIT(4) 417c8846e10SFelix Fietkau #define MT_WF_RFCR_DROP_MCAST BIT(5) 418c8846e10SFelix Fietkau #define MT_WF_RFCR_DROP_BCAST BIT(6) 419c8846e10SFelix Fietkau #define MT_WF_RFCR_DROP_MCAST_FILTERED BIT(7) 420c8846e10SFelix Fietkau #define MT_WF_RFCR_DROP_A3_MAC BIT(8) 421c8846e10SFelix Fietkau #define MT_WF_RFCR_DROP_A3_BSSID BIT(9) 422c8846e10SFelix Fietkau #define MT_WF_RFCR_DROP_A2_BSSID BIT(10) 423c8846e10SFelix Fietkau #define MT_WF_RFCR_DROP_OTHER_BEACON BIT(11) 424c8846e10SFelix Fietkau #define MT_WF_RFCR_DROP_FRAME_REPORT BIT(12) 425c8846e10SFelix Fietkau #define MT_WF_RFCR_DROP_CTL_RSV BIT(13) 426c8846e10SFelix Fietkau #define MT_WF_RFCR_DROP_CTS BIT(14) 427c8846e10SFelix Fietkau #define MT_WF_RFCR_DROP_RTS BIT(15) 428c8846e10SFelix Fietkau #define MT_WF_RFCR_DROP_DUPLICATE BIT(16) 429c8846e10SFelix Fietkau #define MT_WF_RFCR_DROP_OTHER_BSS BIT(17) 430c8846e10SFelix Fietkau #define MT_WF_RFCR_DROP_OTHER_UC BIT(18) 431c8846e10SFelix Fietkau #define MT_WF_RFCR_DROP_OTHER_TIM BIT(19) 432c8846e10SFelix Fietkau #define MT_WF_RFCR_DROP_NDPA BIT(20) 433c8846e10SFelix Fietkau #define MT_WF_RFCR_DROP_UNWANTED_CTL BIT(21) 434c8846e10SFelix Fietkau 435c8846e10SFelix Fietkau #define MT_BSSID0(idx) MT_WF_RMAC(0x004 + (idx) * 8) 436c8846e10SFelix Fietkau #define MT_BSSID1(idx) MT_WF_RMAC(0x008 + (idx) * 8) 437c8846e10SFelix Fietkau #define MT_BSSID1_VALID BIT(16) 438c8846e10SFelix Fietkau 439c8846e10SFelix Fietkau #define MT_MAC_ADDR0(idx) MT_WF_RMAC(0x024 + (idx) * 8) 440c8846e10SFelix Fietkau #define MT_MAC_ADDR1(idx) MT_WF_RMAC(0x028 + (idx) * 8) 441c8846e10SFelix Fietkau #define MT_MAC_ADDR1_ADDR GENMASK(15, 0) 442c8846e10SFelix Fietkau #define MT_MAC_ADDR1_VALID BIT(16) 443c8846e10SFelix Fietkau 444c8846e10SFelix Fietkau #define MT_BA_CONTROL_0 MT_WF_RMAC(0x068) 445c8846e10SFelix Fietkau #define MT_BA_CONTROL_1 MT_WF_RMAC(0x06c) 446c8846e10SFelix Fietkau #define MT_BA_CONTROL_1_ADDR GENMASK(15, 0) 447c8846e10SFelix Fietkau #define MT_BA_CONTROL_1_TID GENMASK(19, 16) 448c8846e10SFelix Fietkau #define MT_BA_CONTROL_1_IGNORE_TID BIT(20) 449c8846e10SFelix Fietkau #define MT_BA_CONTROL_1_IGNORE_ALL BIT(21) 450c8846e10SFelix Fietkau #define MT_BA_CONTROL_1_RESET BIT(22) 451c8846e10SFelix Fietkau 452c8846e10SFelix Fietkau #define MT_WF_RMACDR MT_WF_RMAC(0x078) 453c8846e10SFelix Fietkau #define MT_WF_RMACDR_TSF_PROBERSP_DIS BIT(0) 454c8846e10SFelix Fietkau #define MT_WF_RMACDR_TSF_TIM BIT(4) 455c8846e10SFelix Fietkau #define MT_WF_RMACDR_MBSSID_MASK GENMASK(25, 24) 456c8846e10SFelix Fietkau #define MT_WF_RMACDR_CHECK_HTC_BY_RATE BIT(26) 457c8846e10SFelix Fietkau #define MT_WF_RMACDR_MAXLEN_20BIT BIT(30) 458c8846e10SFelix Fietkau 459c8846e10SFelix Fietkau #define MT_WF_RMAC_RMCR MT_WF_RMAC(0x080) 460c8846e10SFelix Fietkau #define MT_WF_RMAC_RMCR_SMPS_MODE GENMASK(21, 20) 461c8846e10SFelix Fietkau #define MT_WF_RMAC_RMCR_RX_STREAMS GENMASK(24, 22) 462c8846e10SFelix Fietkau #define MT_WF_RMAC_RMCR_SMPS_RTS BIT(25) 463c8846e10SFelix Fietkau 464c8846e10SFelix Fietkau #define MT_WF_RMAC_CH_FREQ MT_WF_RMAC(0x090) 465c8846e10SFelix Fietkau #define MT_WF_RMAC_MAXMINLEN MT_WF_RMAC(0x098) 466c8846e10SFelix Fietkau #define MT_WF_RFCR1 MT_WF_RMAC(0x0a4) 467c8846e10SFelix Fietkau #define MT_WF_RMAC_TMR_PA MT_WF_RMAC(0x0e0) 468c8846e10SFelix Fietkau 469c8846e10SFelix Fietkau #define MT_WF_SEC_BASE 0x21a00 470c8846e10SFelix Fietkau #define MT_WF_SEC(ofs) (MT_WF_SEC_BASE + (ofs)) 471c8846e10SFelix Fietkau 472*8caa9dd3SFelix Fietkau #define MT_WF_CFG_OFF_BASE 0x21e00 473*8caa9dd3SFelix Fietkau #define MT_WF_CFG_OFF(ofs) (MT_WF_CFG_OFF_BASE + (ofs)) 474*8caa9dd3SFelix Fietkau #define MT_WF_CFG_OFF_WOCCR MT_WF_CFG_OFF(0x004) 475*8caa9dd3SFelix Fietkau #define MT_WF_CFG_OFF_WOCCR_TMAC_GC_DIS BIT(4) 476*8caa9dd3SFelix Fietkau 477c8846e10SFelix Fietkau #define MT_SEC_SCR MT_WF_SEC(0x004) 478c8846e10SFelix Fietkau #define MT_SEC_SCR_MASK_ORDER GENMASK(1, 0) 479c8846e10SFelix Fietkau 480c8846e10SFelix Fietkau #define MT_WTBL_OFF_BASE 0x23000 481c8846e10SFelix Fietkau #define MT_WTBL_OFF(n) (MT_WTBL_OFF_BASE + (n)) 482c8846e10SFelix Fietkau 483c8846e10SFelix Fietkau #define MT_WTBL_UPDATE MT_WTBL_OFF(0x000) 484c8846e10SFelix Fietkau #define MT_WTBL_UPDATE_WLAN_IDX GENMASK(7, 0) 485c8846e10SFelix Fietkau #define MT_WTBL_UPDATE_WTBL2 BIT(11) 486c8846e10SFelix Fietkau #define MT_WTBL_UPDATE_ADM_COUNT_CLEAR BIT(12) 487c8846e10SFelix Fietkau #define MT_WTBL_UPDATE_RATE_UPDATE BIT(13) 488c8846e10SFelix Fietkau #define MT_WTBL_UPDATE_TX_COUNT_CLEAR BIT(14) 489c8846e10SFelix Fietkau #define MT_WTBL_UPDATE_RX_COUNT_CLEAR BIT(15) 490c8846e10SFelix Fietkau #define MT_WTBL_UPDATE_BUSY BIT(16) 491c8846e10SFelix Fietkau 492c8846e10SFelix Fietkau #define MT_WTBL_RMVTCR MT_WTBL_OFF(0x008) 493c8846e10SFelix Fietkau #define MT_WTBL_RMVTCR_RX_MV_MODE BIT(23) 494c8846e10SFelix Fietkau 495c8846e10SFelix Fietkau #define MT_LPON_BASE 0x24000 496c8846e10SFelix Fietkau #define MT_LPON(n) (MT_LPON_BASE + (n)) 497c8846e10SFelix Fietkau 498c5211e99SFelix Fietkau #define MT_LPON_T0CR MT_LPON(0x010) 499c5211e99SFelix Fietkau #define MT_LPON_T0CR_MODE GENMASK(1, 0) 500c5211e99SFelix Fietkau 501c5211e99SFelix Fietkau #define MT_LPON_UTTR0 MT_LPON(0x018) 502c5211e99SFelix Fietkau #define MT_LPON_UTTR1 MT_LPON(0x01c) 503c5211e99SFelix Fietkau 504c8846e10SFelix Fietkau #define MT_LPON_BTEIR MT_LPON(0x020) 505c8846e10SFelix Fietkau #define MT_LPON_BTEIR_MBSS_MODE GENMASK(31, 29) 506c8846e10SFelix Fietkau 507c8846e10SFelix Fietkau #define MT_PRE_TBTT MT_LPON(0x030) 508c8846e10SFelix Fietkau #define MT_PRE_TBTT_MASK GENMASK(7, 0) 509c8846e10SFelix Fietkau #define MT_PRE_TBTT_SHIFT 8 510c8846e10SFelix Fietkau 511c8846e10SFelix Fietkau #define MT_TBTT MT_LPON(0x034) 512c8846e10SFelix Fietkau #define MT_TBTT_PERIOD GENMASK(15, 0) 513c8846e10SFelix Fietkau #define MT_TBTT_DTIM_PERIOD GENMASK(23, 16) 514c8846e10SFelix Fietkau #define MT_TBTT_TBTT_WAKE_PERIOD GENMASK(27, 24) 515c8846e10SFelix Fietkau #define MT_TBTT_DTIM_WAKE_PERIOD GENMASK(30, 28) 516c8846e10SFelix Fietkau #define MT_TBTT_CAL_ENABLE BIT(31) 517c8846e10SFelix Fietkau 518c8846e10SFelix Fietkau #define MT_TBTT_TIMER_CFG MT_LPON(0x05c) 519c8846e10SFelix Fietkau 520c8846e10SFelix Fietkau #define MT_LPON_SBTOR(n) MT_LPON(0x0a0) 521c8846e10SFelix Fietkau #define MT_LPON_SBTOR_SUB_BSS_EN BIT(29) 522c8846e10SFelix Fietkau #define MT_LPON_SBTOR_TIME_OFFSET GENMASK(19, 0) 523c8846e10SFelix Fietkau 524c8846e10SFelix Fietkau #define MT_INT_WAKEUP_BASE 0x24400 525c8846e10SFelix Fietkau #define MT_INT_WAKEUP(n) (MT_INT_WAKEUP_BASE + (n)) 526c8846e10SFelix Fietkau 527c8846e10SFelix Fietkau #define MT_HW_INT_STATUS(n) MT_INT_WAKEUP(0x3c + (n) * 8) 528c8846e10SFelix Fietkau #define MT_HW_INT_MASK(n) MT_INT_WAKEUP(0x40 + (n) * 8) 529c8846e10SFelix Fietkau 530c8846e10SFelix Fietkau #define MT_HW_INT3_TBTT0 BIT(15) 531c8846e10SFelix Fietkau #define MT_HW_INT3_PRE_TBTT0 BIT(31) 532c8846e10SFelix Fietkau 533c8846e10SFelix Fietkau #define MT_WTBL1_BASE 0x28000 534c8846e10SFelix Fietkau 535c8846e10SFelix Fietkau #define MT_WTBL_ON_BASE (MT_WTBL1_BASE + 0x2000) 536c8846e10SFelix Fietkau #define MT_WTBL_ON(_n) (MT_WTBL_ON_BASE + (_n)) 537c8846e10SFelix Fietkau 538c8846e10SFelix Fietkau #define MT_WTBL_RIUCR0 MT_WTBL_ON(0x200) 539c8846e10SFelix Fietkau 540c8846e10SFelix Fietkau #define MT_WTBL_RIUCR1 MT_WTBL_ON(0x204) 541c8846e10SFelix Fietkau #define MT_WTBL_RIUCR1_RATE0 GENMASK(11, 0) 542c8846e10SFelix Fietkau #define MT_WTBL_RIUCR1_RATE1 GENMASK(23, 12) 543c8846e10SFelix Fietkau #define MT_WTBL_RIUCR1_RATE2_LO GENMASK(31, 24) 544c8846e10SFelix Fietkau 545c8846e10SFelix Fietkau #define MT_WTBL_RIUCR2 MT_WTBL_ON(0x208) 546c8846e10SFelix Fietkau #define MT_WTBL_RIUCR2_RATE2_HI GENMASK(3, 0) 547c8846e10SFelix Fietkau #define MT_WTBL_RIUCR2_RATE3 GENMASK(15, 4) 548c8846e10SFelix Fietkau #define MT_WTBL_RIUCR2_RATE4 GENMASK(27, 16) 549c8846e10SFelix Fietkau #define MT_WTBL_RIUCR2_RATE5_LO GENMASK(31, 28) 550c8846e10SFelix Fietkau 551c8846e10SFelix Fietkau #define MT_WTBL_RIUCR3 MT_WTBL_ON(0x20c) 552c8846e10SFelix Fietkau #define MT_WTBL_RIUCR3_RATE5_HI GENMASK(7, 0) 553c8846e10SFelix Fietkau #define MT_WTBL_RIUCR3_RATE6 GENMASK(19, 8) 554c8846e10SFelix Fietkau #define MT_WTBL_RIUCR3_RATE7 GENMASK(31, 20) 555c8846e10SFelix Fietkau 556c8846e10SFelix Fietkau #define MT_MIB_BASE 0x2c000 557c8846e10SFelix Fietkau #define MT_MIB(_n) (MT_MIB_BASE + (_n)) 558c8846e10SFelix Fietkau 559c8846e10SFelix Fietkau #define MT_MIB_CTL MT_MIB(0x00) 560c8846e10SFelix Fietkau #define MT_MIB_CTL_PSCCA_TIME GENMASK(13, 11) 561c8846e10SFelix Fietkau #define MT_MIB_CTL_CCA_NAV_TX GENMASK(16, 14) 562c8846e10SFelix Fietkau #define MT_MIB_CTL_ED_TIME GENMASK(30, 28) 563c8846e10SFelix Fietkau #define MT_MIB_CTL_READ_CLR_DIS BIT(31) 564c8846e10SFelix Fietkau 565c8846e10SFelix Fietkau #define MT_MIB_STAT(_n) MT_MIB(0x08 + (_n) * 4) 566c8846e10SFelix Fietkau 567c8846e10SFelix Fietkau #define MT_MIB_STAT_CCA MT_MIB_STAT(9) 568c8846e10SFelix Fietkau #define MT_MIB_STAT_CCA_MASK GENMASK(23, 0) 569c8846e10SFelix Fietkau 570c8846e10SFelix Fietkau #define MT_MIB_STAT_PSCCA MT_MIB_STAT(16) 571c8846e10SFelix Fietkau #define MT_MIB_STAT_PSCCA_MASK GENMASK(23, 0) 572c8846e10SFelix Fietkau 5735a8d4678SLorenzo Bianconi #define MT_TX_AGG_CNT(n) MT_MIB(0xa8 + ((n) << 2)) 5745a8d4678SLorenzo Bianconi 575c8846e10SFelix Fietkau #define MT_MIB_STAT_ED MT_MIB_STAT(18) 576c8846e10SFelix Fietkau #define MT_MIB_STAT_ED_MASK GENMASK(23, 0) 577c8846e10SFelix Fietkau 578c8846e10SFelix Fietkau #define MT_PCIE_REMAP_BASE_1 0x40000 579c8846e10SFelix Fietkau #define MT_PCIE_REMAP_BASE_2 0x80000 580c8846e10SFelix Fietkau 581c8846e10SFelix Fietkau #define MT_TX_HW_QUEUE_MGMT 4 582c8846e10SFelix Fietkau #define MT_TX_HW_QUEUE_MCU 5 583c8846e10SFelix Fietkau #define MT_TX_HW_QUEUE_BCN 7 584c8846e10SFelix Fietkau #define MT_TX_HW_QUEUE_BMC 8 585c8846e10SFelix Fietkau 586c8846e10SFelix Fietkau #define MT_LED_BASE_PHYS 0x80024000 587c8846e10SFelix Fietkau #define MT_LED_PHYS(_n) (MT_LED_BASE_PHYS + (_n)) 588c8846e10SFelix Fietkau 589c8846e10SFelix Fietkau #define MT_LED_CTRL MT_LED_PHYS(0x00) 590c8846e10SFelix Fietkau 591c8846e10SFelix Fietkau #define MT_LED_CTRL_REPLAY(_n) BIT(0 + (8 * (_n))) 592c8846e10SFelix Fietkau #define MT_LED_CTRL_POLARITY(_n) BIT(1 + (8 * (_n))) 593c8846e10SFelix Fietkau #define MT_LED_CTRL_TX_BLINK_MODE(_n) BIT(2 + (8 * (_n))) 594c8846e10SFelix Fietkau #define MT_LED_CTRL_TX_MANUAL_BLINK(_n) BIT(3 + (8 * (_n))) 595c8846e10SFelix Fietkau #define MT_LED_CTRL_TX_OVER_BLINK(_n) BIT(5 + (8 * (_n))) 596c8846e10SFelix Fietkau #define MT_LED_CTRL_KICK(_n) BIT(7 + (8 * (_n))) 597c8846e10SFelix Fietkau 598c8846e10SFelix Fietkau #define MT_LED_STATUS_0(_n) MT_LED_PHYS(0x10 + ((_n) * 8)) 599c8846e10SFelix Fietkau #define MT_LED_STATUS_1(_n) MT_LED_PHYS(0x14 + ((_n) * 8)) 600ff44d907SLorenzo Bianconi #define MT_LED_STATUS_OFF GENMASK(31, 24) 601ff44d907SLorenzo Bianconi #define MT_LED_STATUS_ON GENMASK(23, 16) 602ff44d907SLorenzo Bianconi #define MT_LED_STATUS_DURATION GENMASK(15, 0) 603c8846e10SFelix Fietkau 604c8846e10SFelix Fietkau #define MT_CLIENT_BASE_PHYS_ADDR 0x800c0000 605c8846e10SFelix Fietkau 606c8846e10SFelix Fietkau #define MT_CLIENT_TMAC_INFO_TEMPLATE 0x040 607c8846e10SFelix Fietkau 608c8846e10SFelix Fietkau #define MT_CLIENT_STATUS 0x06c 609c8846e10SFelix Fietkau 610c8846e10SFelix Fietkau #define MT_CLIENT_RESET_TX 0x070 611c8846e10SFelix Fietkau #define MT_CLIENT_RESET_TX_R_E_1 BIT(16) 612c8846e10SFelix Fietkau #define MT_CLIENT_RESET_TX_R_E_2 BIT(17) 613c8846e10SFelix Fietkau #define MT_CLIENT_RESET_TX_R_E_1_S BIT(20) 614c8846e10SFelix Fietkau #define MT_CLIENT_RESET_TX_R_E_2_S BIT(21) 615c8846e10SFelix Fietkau 616c8846e10SFelix Fietkau #define MT_EFUSE_BASE 0x81070000 617c8846e10SFelix Fietkau 618c8846e10SFelix Fietkau #define MT_EFUSE_BASE_CTRL 0x000 619c8846e10SFelix Fietkau #define MT_EFUSE_BASE_CTRL_EMPTY BIT(30) 620c8846e10SFelix Fietkau 621c8846e10SFelix Fietkau #define MT_EFUSE_CTRL 0x008 622c8846e10SFelix Fietkau #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0) 623c8846e10SFelix Fietkau #define MT_EFUSE_CTRL_MODE GENMASK(7, 6) 624c8846e10SFelix Fietkau #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8) 625c8846e10SFelix Fietkau #define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14) 626c8846e10SFelix Fietkau #define MT_EFUSE_CTRL_AIN GENMASK(25, 16) 627c8846e10SFelix Fietkau #define MT_EFUSE_CTRL_VALID BIT(29) 628c8846e10SFelix Fietkau #define MT_EFUSE_CTRL_KICK BIT(30) 629c8846e10SFelix Fietkau #define MT_EFUSE_CTRL_SEL BIT(31) 630c8846e10SFelix Fietkau 631c8846e10SFelix Fietkau #define MT_EFUSE_WDATA(_i) (0x010 + ((_i) * 4)) 632c8846e10SFelix Fietkau #define MT_EFUSE_RDATA(_i) (0x030 + ((_i) * 4)) 633c8846e10SFelix Fietkau 634c8846e10SFelix Fietkau #define MT_CLIENT_RXINF 0x068 635c8846e10SFelix Fietkau #define MT_CLIENT_RXINF_RXSH_GROUPS GENMASK(2, 0) 636c8846e10SFelix Fietkau 637c8846e10SFelix Fietkau #define MT_PSE_BASE_PHYS_ADDR 0xa0000000 638c8846e10SFelix Fietkau 639c8846e10SFelix Fietkau #define MT_PSE_WTBL_2_PHYS_ADDR 0xa5000000 640c8846e10SFelix Fietkau 641c8846e10SFelix Fietkau #define MT_WTBL1_SIZE (8 * 4) 642c8846e10SFelix Fietkau #define MT_WTBL2_SIZE (16 * 4) 643c8846e10SFelix Fietkau #define MT_WTBL3_OFFSET (MT7603_WTBL_SIZE * MT_WTBL2_SIZE) 644c8846e10SFelix Fietkau #define MT_WTBL3_SIZE (16 * 4) 645c8846e10SFelix Fietkau #define MT_WTBL4_OFFSET (MT7603_WTBL_SIZE * MT_WTBL3_SIZE + \ 646c8846e10SFelix Fietkau MT_WTBL3_OFFSET) 647c8846e10SFelix Fietkau #define MT_WTBL4_SIZE (8 * 4) 648c8846e10SFelix Fietkau 649c8846e10SFelix Fietkau #define MT_WTBL1_W0_ADDR_HI GENMASK(15, 0) 650c8846e10SFelix Fietkau #define MT_WTBL1_W0_MUAR_IDX GENMASK(21, 16) 651c8846e10SFelix Fietkau #define MT_WTBL1_W0_RX_CHECK_A1 BIT(22) 652c8846e10SFelix Fietkau #define MT_WTBL1_W0_KEY_IDX GENMASK(24, 23) 653c8846e10SFelix Fietkau #define MT_WTBL1_W0_RX_CHECK_KEY_IDX BIT(25) 654c8846e10SFelix Fietkau #define MT_WTBL1_W0_RX_KEY_VALID BIT(26) 655c8846e10SFelix Fietkau #define MT_WTBL1_W0_RX_IK_VALID BIT(27) 656c8846e10SFelix Fietkau #define MT_WTBL1_W0_RX_VALID BIT(28) 657c8846e10SFelix Fietkau #define MT_WTBL1_W0_RX_CHECK_A2 BIT(29) 658c8846e10SFelix Fietkau #define MT_WTBL1_W0_RX_DATA_VALID BIT(30) 659c8846e10SFelix Fietkau #define MT_WTBL1_W0_WRITE_BURST BIT(31) 660c8846e10SFelix Fietkau 661c8846e10SFelix Fietkau #define MT_WTBL1_W1_ADDR_LO GENMASK(31, 0) 662c8846e10SFelix Fietkau 663c8846e10SFelix Fietkau #define MT_WTBL1_W2_MPDU_DENSITY GENMASK(2, 0) 664c8846e10SFelix Fietkau #define MT_WTBL1_W2_KEY_TYPE GENMASK(6, 3) 665c8846e10SFelix Fietkau #define MT_WTBL1_W2_EVEN_PN BIT(7) 666c8846e10SFelix Fietkau #define MT_WTBL1_W2_TO_DS BIT(8) 667c8846e10SFelix Fietkau #define MT_WTBL1_W2_FROM_DS BIT(9) 668c8846e10SFelix Fietkau #define MT_WTBL1_W2_HEADER_TRANS BIT(10) 669c8846e10SFelix Fietkau #define MT_WTBL1_W2_AMPDU_FACTOR GENMASK(13, 11) 670c8846e10SFelix Fietkau #define MT_WTBL1_W2_PWR_MGMT BIT(14) 671c8846e10SFelix Fietkau #define MT_WTBL1_W2_RDG BIT(15) 672c8846e10SFelix Fietkau #define MT_WTBL1_W2_RTS BIT(16) 673c8846e10SFelix Fietkau #define MT_WTBL1_W2_CFACK BIT(17) 674c8846e10SFelix Fietkau #define MT_WTBL1_W2_RDG_BA BIT(18) 675c8846e10SFelix Fietkau #define MT_WTBL1_W2_SMPS BIT(19) 676c8846e10SFelix Fietkau #define MT_WTBL1_W2_TXS_BAF_REPORT BIT(20) 677c8846e10SFelix Fietkau #define MT_WTBL1_W2_DYN_BW BIT(21) 678c8846e10SFelix Fietkau #define MT_WTBL1_W2_LDPC BIT(22) 679c8846e10SFelix Fietkau #define MT_WTBL1_W2_ITXBF BIT(23) 680c8846e10SFelix Fietkau #define MT_WTBL1_W2_ETXBF BIT(24) 681c8846e10SFelix Fietkau #define MT_WTBL1_W2_TXOP_PS BIT(25) 682c8846e10SFelix Fietkau #define MT_WTBL1_W2_MESH BIT(26) 683c8846e10SFelix Fietkau #define MT_WTBL1_W2_QOS BIT(27) 684c8846e10SFelix Fietkau #define MT_WTBL1_W2_HT BIT(28) 685c8846e10SFelix Fietkau #define MT_WTBL1_W2_VHT BIT(29) 686c8846e10SFelix Fietkau #define MT_WTBL1_W2_ADMISSION_CONTROL BIT(30) 687c8846e10SFelix Fietkau #define MT_WTBL1_W2_GROUP_ID BIT(31) 688c8846e10SFelix Fietkau 689c8846e10SFelix Fietkau #define MT_WTBL1_W3_WTBL2_FRAME_ID GENMASK(10, 0) 690c8846e10SFelix Fietkau #define MT_WTBL1_W3_WTBL2_ENTRY_ID GENMASK(15, 11) 691c8846e10SFelix Fietkau #define MT_WTBL1_W3_WTBL4_FRAME_ID GENMASK(26, 16) 692c8846e10SFelix Fietkau #define MT_WTBL1_W3_CHECK_PER BIT(27) 693c8846e10SFelix Fietkau #define MT_WTBL1_W3_KEEP_I_PSM BIT(28) 694c8846e10SFelix Fietkau #define MT_WTBL1_W3_I_PSM BIT(29) 695c8846e10SFelix Fietkau #define MT_WTBL1_W3_POWER_SAVE BIT(30) 696c8846e10SFelix Fietkau #define MT_WTBL1_W3_SKIP_TX BIT(31) 697c8846e10SFelix Fietkau 698c8846e10SFelix Fietkau #define MT_WTBL1_W4_WTBL3_FRAME_ID GENMASK(10, 0) 699c8846e10SFelix Fietkau #define MT_WTBL1_W4_WTBL3_ENTRY_ID GENMASK(16, 11) 700c8846e10SFelix Fietkau #define MT_WTBL1_W4_WTBL4_ENTRY_ID GENMASK(22, 17) 701c8846e10SFelix Fietkau #define MT_WTBL1_W4_PARTIAL_AID GENMASK(31, 23) 702c8846e10SFelix Fietkau 703c8846e10SFelix Fietkau #define MT_WTBL2_W0_PN_LO GENMASK(31, 0) 704c8846e10SFelix Fietkau 705c8846e10SFelix Fietkau #define MT_WTBL2_W1_PN_HI GENMASK(15, 0) 706c8846e10SFelix Fietkau #define MT_WTBL2_W1_NON_QOS_SEQNO GENMASK(27, 16) 707c8846e10SFelix Fietkau 708c8846e10SFelix Fietkau #define MT_WTBL2_W2_TID0_SN GENMASK(11, 0) 709c8846e10SFelix Fietkau #define MT_WTBL2_W2_TID1_SN GENMASK(23, 12) 710c8846e10SFelix Fietkau #define MT_WTBL2_W2_TID2_SN_LO GENMASK(31, 24) 711c8846e10SFelix Fietkau 712c8846e10SFelix Fietkau #define MT_WTBL2_W3_TID2_SN_HI GENMASK(3, 0) 713c8846e10SFelix Fietkau #define MT_WTBL2_W3_TID3_SN GENMASK(15, 4) 714c8846e10SFelix Fietkau #define MT_WTBL2_W3_TID4_SN GENMASK(27, 16) 715c8846e10SFelix Fietkau #define MT_WTBL2_W3_TID5_SN_LO GENMASK(31, 28) 716c8846e10SFelix Fietkau 717c8846e10SFelix Fietkau #define MT_WTBL2_W4_TID5_SN_HI GENMASK(7, 0) 718c8846e10SFelix Fietkau #define MT_WTBL2_W4_TID6_SN GENMASK(19, 8) 719c8846e10SFelix Fietkau #define MT_WTBL2_W4_TID7_SN GENMASK(31, 20) 720c8846e10SFelix Fietkau 721c8846e10SFelix Fietkau #define MT_WTBL2_W5_TX_COUNT_RATE1 GENMASK(15, 0) 722c8846e10SFelix Fietkau #define MT_WTBL2_W5_FAIL_COUNT_RATE1 GENAMSK(31, 16) 723c8846e10SFelix Fietkau 724c8846e10SFelix Fietkau #define MT_WTBL2_W6_TX_COUNT_RATE2 GENMASK(7, 0) 725c8846e10SFelix Fietkau #define MT_WTBL2_W6_TX_COUNT_RATE3 GENMASK(15, 8) 726c8846e10SFelix Fietkau #define MT_WTBL2_W6_TX_COUNT_RATE4 GENMASK(23, 16) 727c8846e10SFelix Fietkau #define MT_WTBL2_W6_TX_COUNT_RATE5 GENMASK(31, 24) 728c8846e10SFelix Fietkau 729c8846e10SFelix Fietkau #define MT_WTBL2_W7_TX_COUNT_CUR_BW GENMASK(15, 0) 730c8846e10SFelix Fietkau #define MT_WTBL2_W7_FAIL_COUNT_CUR_BW GENMASK(31, 16) 731c8846e10SFelix Fietkau 732c8846e10SFelix Fietkau #define MT_WTBL2_W8_TX_COUNT_OTHER_BW GENMASK(15, 0) 733c8846e10SFelix Fietkau #define MT_WTBL2_W8_FAIL_COUNT_OTHER_BW GENMASK(31, 16) 734c8846e10SFelix Fietkau 735c8846e10SFelix Fietkau #define MT_WTBL2_W9_POWER_OFFSET GENMASK(4, 0) 736c8846e10SFelix Fietkau #define MT_WTBL2_W9_SPATIAL_EXT BIT(5) 737c8846e10SFelix Fietkau #define MT_WTBL2_W9_ANT_PRIORITY GENMASK(8, 6) 738c8846e10SFelix Fietkau #define MT_WTBL2_W9_CC_BW_SEL GENMASK(10, 9) 739c8846e10SFelix Fietkau #define MT_WTBL2_W9_CHANGE_BW_RATE GENMASK(13, 11) 740c8846e10SFelix Fietkau #define MT_WTBL2_W9_BW_CAP GENMASK(15, 14) 741c8846e10SFelix Fietkau #define MT_WTBL2_W9_SHORT_GI_20 BIT(16) 742c8846e10SFelix Fietkau #define MT_WTBL2_W9_SHORT_GI_40 BIT(17) 743c8846e10SFelix Fietkau #define MT_WTBL2_W9_SHORT_GI_80 BIT(18) 744c8846e10SFelix Fietkau #define MT_WTBL2_W9_SHORT_GI_160 BIT(19) 745c8846e10SFelix Fietkau #define MT_WTBL2_W9_MPDU_FAIL_COUNT GENMASK(25, 23) 746c8846e10SFelix Fietkau #define MT_WTBL2_W9_MPDU_OK_COUNT GENMASK(28, 26) 747c8846e10SFelix Fietkau #define MT_WTBL2_W9_RATE_IDX GENMASK(31, 29) 748c8846e10SFelix Fietkau 749c8846e10SFelix Fietkau #define MT_WTBL2_W10_RATE1 GENMASK(11, 0) 750c8846e10SFelix Fietkau #define MT_WTBL2_W10_RATE2 GENMASK(23, 12) 751c8846e10SFelix Fietkau #define MT_WTBL2_W10_RATE3_LO GENMASK(31, 24) 752c8846e10SFelix Fietkau 753c8846e10SFelix Fietkau #define MT_WTBL2_W11_RATE3_HI GENMASK(3, 0) 754c8846e10SFelix Fietkau #define MT_WTBL2_W11_RATE4 GENMASK(15, 4) 755c8846e10SFelix Fietkau #define MT_WTBL2_W11_RATE5 GENMASK(27, 16) 756c8846e10SFelix Fietkau #define MT_WTBL2_W11_RATE6_LO GENMASK(31, 28) 757c8846e10SFelix Fietkau 758c8846e10SFelix Fietkau #define MT_WTBL2_W12_RATE6_HI GENMASK(7, 0) 759c8846e10SFelix Fietkau #define MT_WTBL2_W12_RATE7 GENMASK(19, 8) 760c8846e10SFelix Fietkau #define MT_WTBL2_W12_RATE8 GENMASK(31, 20) 761c8846e10SFelix Fietkau 762c8846e10SFelix Fietkau #define MT_WTBL2_W13_AVG_RCPI0 GENMASK(7, 0) 763c8846e10SFelix Fietkau #define MT_WTBL2_W13_AVG_RCPI1 GENMASK(15, 8) 764c8846e10SFelix Fietkau #define MT_WTBL2_W13_AVG_RCPI2 GENAMSK(23, 16) 765c8846e10SFelix Fietkau 766c8846e10SFelix Fietkau #define MT_WTBL2_W14_CC_NOISE_1S GENMASK(6, 0) 767c8846e10SFelix Fietkau #define MT_WTBL2_W14_CC_NOISE_2S GENMASK(13, 7) 768c8846e10SFelix Fietkau #define MT_WTBL2_W14_CC_NOISE_3S GENMASK(20, 14) 769c8846e10SFelix Fietkau #define MT_WTBL2_W14_CHAN_EST_RMS GENMASK(24, 21) 770c8846e10SFelix Fietkau #define MT_WTBL2_W14_CC_NOISE_SEL BIT(15) 771c8846e10SFelix Fietkau #define MT_WTBL2_W14_ANT_SEL GENMASK(31, 26) 772c8846e10SFelix Fietkau 773c8846e10SFelix Fietkau #define MT_WTBL2_W15_BA_WIN_SIZE GENMASK(2, 0) 774c8846e10SFelix Fietkau #define MT_WTBL2_W15_BA_WIN_SIZE_SHIFT 3 775c8846e10SFelix Fietkau #define MT_WTBL2_W15_BA_EN_TIDS GENMASK(31, 24) 776c8846e10SFelix Fietkau 777c8846e10SFelix Fietkau #define MT_WTBL1_OR (MT_WTBL1_BASE + 0x2300) 778c8846e10SFelix Fietkau #define MT_WTBL1_OR_PSM_WRITE BIT(31) 779c8846e10SFelix Fietkau 780c8846e10SFelix Fietkau #endif 781