1*e7ae4cf2SDavid Wu // SPDX-License-Identifier: GPL-2.0+
2*e7ae4cf2SDavid Wu /*
3*e7ae4cf2SDavid Wu * (C) Copyright 2019 Rockchip Electronics Co., Ltd
4*e7ae4cf2SDavid Wu */
5*e7ae4cf2SDavid Wu
6*e7ae4cf2SDavid Wu #include <common.h>
7*e7ae4cf2SDavid Wu #include <dm.h>
8*e7ae4cf2SDavid Wu #include <dm/pinctrl.h>
9*e7ae4cf2SDavid Wu #include <regmap.h>
10*e7ae4cf2SDavid Wu #include <syscon.h>
11*e7ae4cf2SDavid Wu
12*e7ae4cf2SDavid Wu #include "pinctrl-rockchip.h"
13*e7ae4cf2SDavid Wu
14*e7ae4cf2SDavid Wu static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = {
15*e7ae4cf2SDavid Wu {
16*e7ae4cf2SDavid Wu .num = 2,
17*e7ae4cf2SDavid Wu .pin = 12,
18*e7ae4cf2SDavid Wu .reg = 0x24,
19*e7ae4cf2SDavid Wu .bit = 8,
20*e7ae4cf2SDavid Wu .mask = 0x3
21*e7ae4cf2SDavid Wu }, {
22*e7ae4cf2SDavid Wu .num = 2,
23*e7ae4cf2SDavid Wu .pin = 15,
24*e7ae4cf2SDavid Wu .reg = 0x28,
25*e7ae4cf2SDavid Wu .bit = 0,
26*e7ae4cf2SDavid Wu .mask = 0x7
27*e7ae4cf2SDavid Wu }, {
28*e7ae4cf2SDavid Wu .num = 2,
29*e7ae4cf2SDavid Wu .pin = 23,
30*e7ae4cf2SDavid Wu .reg = 0x30,
31*e7ae4cf2SDavid Wu .bit = 14,
32*e7ae4cf2SDavid Wu .mask = 0x3
33*e7ae4cf2SDavid Wu },
34*e7ae4cf2SDavid Wu };
35*e7ae4cf2SDavid Wu
36*e7ae4cf2SDavid Wu static struct rockchip_mux_route_data rk3328_mux_route_data[] = {
37*e7ae4cf2SDavid Wu {
38*e7ae4cf2SDavid Wu /* uart2dbg_rxm0 */
39*e7ae4cf2SDavid Wu .bank_num = 1,
40*e7ae4cf2SDavid Wu .pin = 1,
41*e7ae4cf2SDavid Wu .func = 2,
42*e7ae4cf2SDavid Wu .route_offset = 0x50,
43*e7ae4cf2SDavid Wu .route_val = BIT(16) | BIT(16 + 1),
44*e7ae4cf2SDavid Wu }, {
45*e7ae4cf2SDavid Wu /* uart2dbg_rxm1 */
46*e7ae4cf2SDavid Wu .bank_num = 2,
47*e7ae4cf2SDavid Wu .pin = 1,
48*e7ae4cf2SDavid Wu .func = 1,
49*e7ae4cf2SDavid Wu .route_offset = 0x50,
50*e7ae4cf2SDavid Wu .route_val = BIT(16) | BIT(16 + 1) | BIT(0),
51*e7ae4cf2SDavid Wu }, {
52*e7ae4cf2SDavid Wu /* gmac-m1_rxd0 */
53*e7ae4cf2SDavid Wu .bank_num = 1,
54*e7ae4cf2SDavid Wu .pin = 11,
55*e7ae4cf2SDavid Wu .func = 2,
56*e7ae4cf2SDavid Wu .route_offset = 0x50,
57*e7ae4cf2SDavid Wu .route_val = BIT(16 + 2) | BIT(2),
58*e7ae4cf2SDavid Wu }, {
59*e7ae4cf2SDavid Wu /* gmac-m1-optimized_rxd3 */
60*e7ae4cf2SDavid Wu .bank_num = 1,
61*e7ae4cf2SDavid Wu .pin = 14,
62*e7ae4cf2SDavid Wu .func = 2,
63*e7ae4cf2SDavid Wu .route_offset = 0x50,
64*e7ae4cf2SDavid Wu .route_val = BIT(16 + 10) | BIT(10),
65*e7ae4cf2SDavid Wu }, {
66*e7ae4cf2SDavid Wu /* pdm_sdi0m0 */
67*e7ae4cf2SDavid Wu .bank_num = 2,
68*e7ae4cf2SDavid Wu .pin = 19,
69*e7ae4cf2SDavid Wu .func = 2,
70*e7ae4cf2SDavid Wu .route_offset = 0x50,
71*e7ae4cf2SDavid Wu .route_val = BIT(16 + 3),
72*e7ae4cf2SDavid Wu }, {
73*e7ae4cf2SDavid Wu /* pdm_sdi0m1 */
74*e7ae4cf2SDavid Wu .bank_num = 1,
75*e7ae4cf2SDavid Wu .pin = 23,
76*e7ae4cf2SDavid Wu .func = 3,
77*e7ae4cf2SDavid Wu .route_offset = 0x50,
78*e7ae4cf2SDavid Wu .route_val = BIT(16 + 3) | BIT(3),
79*e7ae4cf2SDavid Wu }, {
80*e7ae4cf2SDavid Wu /* spi_rxdm2 */
81*e7ae4cf2SDavid Wu .bank_num = 3,
82*e7ae4cf2SDavid Wu .pin = 2,
83*e7ae4cf2SDavid Wu .func = 4,
84*e7ae4cf2SDavid Wu .route_offset = 0x50,
85*e7ae4cf2SDavid Wu .route_val = BIT(16 + 4) | BIT(16 + 5) | BIT(5),
86*e7ae4cf2SDavid Wu }, {
87*e7ae4cf2SDavid Wu /* i2s2_sdim0 */
88*e7ae4cf2SDavid Wu .bank_num = 1,
89*e7ae4cf2SDavid Wu .pin = 24,
90*e7ae4cf2SDavid Wu .func = 1,
91*e7ae4cf2SDavid Wu .route_offset = 0x50,
92*e7ae4cf2SDavid Wu .route_val = BIT(16 + 6),
93*e7ae4cf2SDavid Wu }, {
94*e7ae4cf2SDavid Wu /* i2s2_sdim1 */
95*e7ae4cf2SDavid Wu .bank_num = 3,
96*e7ae4cf2SDavid Wu .pin = 2,
97*e7ae4cf2SDavid Wu .func = 6,
98*e7ae4cf2SDavid Wu .route_offset = 0x50,
99*e7ae4cf2SDavid Wu .route_val = BIT(16 + 6) | BIT(6),
100*e7ae4cf2SDavid Wu }, {
101*e7ae4cf2SDavid Wu /* card_iom1 */
102*e7ae4cf2SDavid Wu .bank_num = 2,
103*e7ae4cf2SDavid Wu .pin = 22,
104*e7ae4cf2SDavid Wu .func = 3,
105*e7ae4cf2SDavid Wu .route_offset = 0x50,
106*e7ae4cf2SDavid Wu .route_val = BIT(16 + 7) | BIT(7),
107*e7ae4cf2SDavid Wu }, {
108*e7ae4cf2SDavid Wu /* tsp_d5m1 */
109*e7ae4cf2SDavid Wu .bank_num = 2,
110*e7ae4cf2SDavid Wu .pin = 16,
111*e7ae4cf2SDavid Wu .func = 3,
112*e7ae4cf2SDavid Wu .route_offset = 0x50,
113*e7ae4cf2SDavid Wu .route_val = BIT(16 + 8) | BIT(8),
114*e7ae4cf2SDavid Wu }, {
115*e7ae4cf2SDavid Wu /* cif_data5m1 */
116*e7ae4cf2SDavid Wu .bank_num = 2,
117*e7ae4cf2SDavid Wu .pin = 16,
118*e7ae4cf2SDavid Wu .func = 4,
119*e7ae4cf2SDavid Wu .route_offset = 0x50,
120*e7ae4cf2SDavid Wu .route_val = BIT(16 + 9) | BIT(9),
121*e7ae4cf2SDavid Wu },
122*e7ae4cf2SDavid Wu };
123*e7ae4cf2SDavid Wu
124*e7ae4cf2SDavid Wu #define RK3328_PULL_OFFSET 0x100
125*e7ae4cf2SDavid Wu
rk3328_calc_pull_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)126*e7ae4cf2SDavid Wu static void rk3328_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
127*e7ae4cf2SDavid Wu int pin_num, struct regmap **regmap,
128*e7ae4cf2SDavid Wu int *reg, u8 *bit)
129*e7ae4cf2SDavid Wu {
130*e7ae4cf2SDavid Wu struct rockchip_pinctrl_priv *priv = bank->priv;
131*e7ae4cf2SDavid Wu
132*e7ae4cf2SDavid Wu *regmap = priv->regmap_base;
133*e7ae4cf2SDavid Wu *reg = RK3328_PULL_OFFSET;
134*e7ae4cf2SDavid Wu *reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
135*e7ae4cf2SDavid Wu *reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
136*e7ae4cf2SDavid Wu
137*e7ae4cf2SDavid Wu *bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
138*e7ae4cf2SDavid Wu *bit *= ROCKCHIP_PULL_BITS_PER_PIN;
139*e7ae4cf2SDavid Wu }
140*e7ae4cf2SDavid Wu
141*e7ae4cf2SDavid Wu #define RK3328_DRV_GRF_OFFSET 0x200
142*e7ae4cf2SDavid Wu
rk3328_calc_drv_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)143*e7ae4cf2SDavid Wu static void rk3328_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
144*e7ae4cf2SDavid Wu int pin_num, struct regmap **regmap,
145*e7ae4cf2SDavid Wu int *reg, u8 *bit)
146*e7ae4cf2SDavid Wu {
147*e7ae4cf2SDavid Wu struct rockchip_pinctrl_priv *priv = bank->priv;
148*e7ae4cf2SDavid Wu
149*e7ae4cf2SDavid Wu *regmap = priv->regmap_base;
150*e7ae4cf2SDavid Wu *reg = RK3328_DRV_GRF_OFFSET;
151*e7ae4cf2SDavid Wu *reg += bank->bank_num * ROCKCHIP_DRV_BANK_STRIDE;
152*e7ae4cf2SDavid Wu *reg += ((pin_num / ROCKCHIP_DRV_PINS_PER_REG) * 4);
153*e7ae4cf2SDavid Wu
154*e7ae4cf2SDavid Wu *bit = (pin_num % ROCKCHIP_DRV_PINS_PER_REG);
155*e7ae4cf2SDavid Wu *bit *= ROCKCHIP_DRV_BITS_PER_PIN;
156*e7ae4cf2SDavid Wu }
157*e7ae4cf2SDavid Wu
158*e7ae4cf2SDavid Wu #define RK3328_SCHMITT_BITS_PER_PIN 1
159*e7ae4cf2SDavid Wu #define RK3328_SCHMITT_PINS_PER_REG 16
160*e7ae4cf2SDavid Wu #define RK3328_SCHMITT_BANK_STRIDE 8
161*e7ae4cf2SDavid Wu #define RK3328_SCHMITT_GRF_OFFSET 0x380
162*e7ae4cf2SDavid Wu
rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank * bank,int pin_num,struct regmap ** regmap,int * reg,u8 * bit)163*e7ae4cf2SDavid Wu static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
164*e7ae4cf2SDavid Wu int pin_num,
165*e7ae4cf2SDavid Wu struct regmap **regmap,
166*e7ae4cf2SDavid Wu int *reg, u8 *bit)
167*e7ae4cf2SDavid Wu {
168*e7ae4cf2SDavid Wu struct rockchip_pinctrl_priv *priv = bank->priv;
169*e7ae4cf2SDavid Wu
170*e7ae4cf2SDavid Wu *regmap = priv->regmap_base;
171*e7ae4cf2SDavid Wu *reg = RK3328_SCHMITT_GRF_OFFSET;
172*e7ae4cf2SDavid Wu
173*e7ae4cf2SDavid Wu *reg += bank->bank_num * RK3328_SCHMITT_BANK_STRIDE;
174*e7ae4cf2SDavid Wu *reg += ((pin_num / RK3328_SCHMITT_PINS_PER_REG) * 4);
175*e7ae4cf2SDavid Wu *bit = pin_num % RK3328_SCHMITT_PINS_PER_REG;
176*e7ae4cf2SDavid Wu
177*e7ae4cf2SDavid Wu return 0;
178*e7ae4cf2SDavid Wu }
179*e7ae4cf2SDavid Wu
180*e7ae4cf2SDavid Wu static struct rockchip_pin_bank rk3328_pin_banks[] = {
181*e7ae4cf2SDavid Wu PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0),
182*e7ae4cf2SDavid Wu PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0),
183*e7ae4cf2SDavid Wu PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0,
184*e7ae4cf2SDavid Wu IOMUX_WIDTH_3BIT,
185*e7ae4cf2SDavid Wu IOMUX_WIDTH_3BIT,
186*e7ae4cf2SDavid Wu 0),
187*e7ae4cf2SDavid Wu PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3",
188*e7ae4cf2SDavid Wu IOMUX_WIDTH_3BIT,
189*e7ae4cf2SDavid Wu IOMUX_WIDTH_3BIT,
190*e7ae4cf2SDavid Wu 0,
191*e7ae4cf2SDavid Wu 0),
192*e7ae4cf2SDavid Wu };
193*e7ae4cf2SDavid Wu
194*e7ae4cf2SDavid Wu static struct rockchip_pin_ctrl rk3328_pin_ctrl = {
195*e7ae4cf2SDavid Wu .pin_banks = rk3328_pin_banks,
196*e7ae4cf2SDavid Wu .nr_banks = ARRAY_SIZE(rk3328_pin_banks),
197*e7ae4cf2SDavid Wu .label = "RK3328-GPIO",
198*e7ae4cf2SDavid Wu .type = RK3288,
199*e7ae4cf2SDavid Wu .grf_mux_offset = 0x0,
200*e7ae4cf2SDavid Wu .iomux_recalced = rk3328_mux_recalced_data,
201*e7ae4cf2SDavid Wu .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data),
202*e7ae4cf2SDavid Wu .iomux_routes = rk3328_mux_route_data,
203*e7ae4cf2SDavid Wu .niomux_routes = ARRAY_SIZE(rk3328_mux_route_data),
204*e7ae4cf2SDavid Wu .pull_calc_reg = rk3328_calc_pull_reg_and_bit,
205*e7ae4cf2SDavid Wu .drv_calc_reg = rk3328_calc_drv_reg_and_bit,
206*e7ae4cf2SDavid Wu .schmitt_calc_reg = rk3328_calc_schmitt_reg_and_bit,
207*e7ae4cf2SDavid Wu };
208*e7ae4cf2SDavid Wu
209*e7ae4cf2SDavid Wu static const struct udevice_id rk3328_pinctrl_ids[] = {
210*e7ae4cf2SDavid Wu {
211*e7ae4cf2SDavid Wu .compatible = "rockchip,rk3328-pinctrl",
212*e7ae4cf2SDavid Wu .data = (ulong)&rk3328_pin_ctrl
213*e7ae4cf2SDavid Wu },
214*e7ae4cf2SDavid Wu { }
215*e7ae4cf2SDavid Wu };
216*e7ae4cf2SDavid Wu
217*e7ae4cf2SDavid Wu U_BOOT_DRIVER(pinctrl_rk3328) = {
218*e7ae4cf2SDavid Wu .name = "rockchip_rk3328_pinctrl",
219*e7ae4cf2SDavid Wu .id = UCLASS_PINCTRL,
220*e7ae4cf2SDavid Wu .of_match = rk3328_pinctrl_ids,
221*e7ae4cf2SDavid Wu .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
222*e7ae4cf2SDavid Wu .ops = &rockchip_pinctrl_ops,
223*e7ae4cf2SDavid Wu #if !CONFIG_IS_ENABLED(OF_PLATDATA)
224*e7ae4cf2SDavid Wu .bind = dm_scan_fdt_dev,
225*e7ae4cf2SDavid Wu #endif
226*e7ae4cf2SDavid Wu .probe = rockchip_pinctrl_probe,
227*e7ae4cf2SDavid Wu };
228