Home
last modified time | relevance | path

Searched +full:12 +full:bit +full:- +full:clkdiv +full:- +full:mode (Results 1 – 25 of 29) sorted by relevance

12

/openbmc/linux/drivers/hwtracing/intel_th/
H A Dpti.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2016 Intel Corporation.
25 unsigned int mode; member
27 unsigned int clkdiv; member
33 /* map PTI widths to MODE settings of PTI_CTL register */
35 0, 4, 8, 0, 12, 0, 0, 0, 16, 0, 0, 0, 0, 0, 0, 0,
46 return -EINVAL; in pti_width_mode()
54 return scnprintf(buf, PAGE_SIZE, "%d\n", pti_mode[pti->mode]); in mode_show()
72 pti->mode = ret; in mode_store()
77 static DEVICE_ATTR_RW(mode);
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,adf4350.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
15 - adi,adf4350
16 - adi,adf4351
21 spi-max-frequency:
28 clock-names:
35 adi,channel-spacing:
40 adi,power-up-frequency:
[all …]
/openbmc/linux/drivers/pwm/
H A Dpwm-tiehrpwm.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2012 Texas Instruments, Inc. - https://www.ti.com/
23 #define TBCTL_PRDLD_MASK BIT(3)
25 #define TBCTL_PRDLD_IMDT BIT(3)
26 #define TBCTL_CLKDIV_MASK (BIT(12) | BIT(11) | BIT(10) | BIT(9) | \
27 BIT(8) | BIT(7))
28 #define TBCTL_CTRMODE_MASK (BIT(1) | BIT(0))
30 #define TBCTL_CTRMODE_DOWN BIT(0)
31 #define TBCTL_CTRMODE_UPDOWN BIT(1)
32 #define TBCTL_CTRMODE_FREEZE (BIT(1) | BIT(0))
[all …]
/openbmc/qemu/hw/sd/
H A Domap_mmc.c2 * OMAP on-chip MMC/SD host emulation.
6 * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
41 int mode; member
49 int clkdiv; member
73 qemu_set_irq(s->irq, !!(s->status & s->mask)); in omap_mmc_interrupts_update()
78 if (!host->transfer && !host->fifo_len) { in omap_mmc_fifolevel_update()
79 host->status &= 0xf3ff; in omap_mmc_fifolevel_update()
83 if (host->fifo_len > host->af_level && host->ddir) { in omap_mmc_fifolevel_update()
84 if (host->rx_dma) { in omap_mmc_fifolevel_update()
85 host->status &= 0xfbff; in omap_mmc_fifolevel_update()
[all …]
/openbmc/u-boot/board/freescale/mpc8569mds/
H A Dmpc8569mds.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2010 Freescale Semiconductor.
30 #include "../common/pq-mds-pib.h"
52 {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
88 {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
109 {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
131 {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
139 /* UART1 is muxed with QE PortF bit [9-12].*/
140 {5, 12, 2, 0, 3}, /* UART1_SIN */
188 gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK; in board_early_init_f()
[all …]
/openbmc/linux/drivers/mmc/host/
H A Dsunplus-mmc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Author: Li-hao Kuo <lhjeff911@gmail.com>
11 #include <linux/dma-mapping.h>
18 #include <linux/mmc/slot-gpio.h>
44 #define SPMMC_HW_DMA_RST BIT(9)
45 #define SPMMC_DMAIDLE BIT(10)
65 #define SPMMC_SDINT_SDCMPEN BIT(0)
66 #define SPMMC_SDINT_SDCMP BIT(1)
67 #define SPMMC_SDINT_SDCMPCLR BIT(2)
68 #define SPMMC_SDINT_SDIOEN BIT(3)
[all …]
H A Datmel-mci.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2004-2008 Atmel Corporation
12 #include <linux/dma-mapping.h>
50 #define ATMCI_CR_MCIEN BIT(0) /* MCI Enable */
51 #define ATMCI_CR_MCIDIS BIT(1) /* MCI Disable */
52 #define ATMCI_CR_PWSEN BIT(2) /* Power Save Enable */
53 #define ATMCI_CR_PWSDIS BIT(3) /* Power Save Disable */
54 #define ATMCI_CR_SWRST BIT(7) /* Software Reset */
55 #define ATMCI_MR 0x0004 /* Mode */
58 #define ATMCI_MR_RDPROOF BIT(11) /* Read Proof */
[all …]
H A Dsdhci-omap.c1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/mmc/slot-gpio.h>
23 #include "sdhci-pltfm.h"
33 #define CON_DW8 BIT(5)
34 #define CON_DMA_MASTER BIT(20)
35 #define CON_DDR BIT(19)
36 #define CON_CLKEXTFREE BIT(16)
37 #define CON_PADEN BIT(15)
38 #define CON_CTPL BIT(11)
39 #define CON_INIT BIT(1)
[all …]
H A Dmmci.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
6 * Copyright (C) 2010 ST-Ericsson SA
26 #include <linux/mmc/slot-gpio.h>
33 #include <linux/dma-mapping.h>
47 #define DRIVER_NAME "mmci-pl18x"
273 .stm32_idmabsize_mask = GENMASK(12, 5),
274 .stm32_idmabsize_align = BIT(5),
301 .stm32_idmabsize_align = BIT(5),
329 .stm32_idmabsize_align = BIT(6),
[all …]
/openbmc/u-boot/drivers/clk/
H A Dclk_stm32mp1.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
7 #include <clk-uclass.h>
15 #include <dt-bindings/clock/stm32mp1-clks.h>
16 #include <dt-bindings/clock/stm32mp1-clksrc.h>
36 #define STGENC_CNTCR_EN BIT(0)
112 #define RCC_SELR_SRCRDY BIT(31)
138 #define RCC_DIVR_DIVRDY BIT(31)
150 #define RCC_BDCR_LSEON BIT(0)
151 #define RCC_BDCR_LSEBYP BIT(1)
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dadau1701.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
94 #define ADAU1701_SERICTL_INV_BCLK BIT(3)
95 #define ADAU1701_SERICTL_INV_LRCLK BIT(4)
100 #define ADAU1707_CLKDIV_UNSET (-1U)
116 u8 pin_config[12];
192 size = adau1701_register_size(&client->dev, reg); in adau1701_reg_write()
194 return -EINVAL; in adau1701_reg_write()
199 for (i = size + 1; i >= 2; --i) { in adau1701_reg_write()
210 return -EIO; in adau1701_reg_write()
[all …]
/openbmc/linux/drivers/gpu/drm/bridge/
H A Dtc358775.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/media-bus-format.h>
35 /* DSI D-PHY Layer Registers */
48 #define DFTMODE_CNTRL 0x0054 /* DFT Mode Control */
51 #define PPI_STARTPPI 0x0104 /* START control bit of PPI-TX function. */
89 #define PPI_CLRSIPO 0x01E4 /* Clear SIPO values, Slave mode use only. */
92 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX function */
97 #define DSI_LANESTATUS0 0x0214 /* Displays lane is in HS RX mode. */
115 #define VFUEN_EN BIT(0) /* Upload Enable */
118 #define LV_MX0003 0x0480 /* Bit 0 to 3 */
[all …]
/openbmc/u-boot/board/freescale/mpc8568mds/
H A Dmpc8568mds.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
37 {4, 12, 2, 0, 2}, /* RxD3 */
62 {5, 12, 2, 0, 2}, /* RxD3 */
108 port_c->cpdir2 |= 0x0f000000; in board_early_init_f()
109 port_c->cppar2 &= ~0x0f000000; in board_early_init_f()
110 port_c->cppar2 |= 0x0a000000; in board_early_init_f()
132 uint clkdiv; in local_bus_init() local
136 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; in local_bus_init()
138 gur->lbiuiplldcr1 = 0x00078080; in local_bus_init()
[all …]
/openbmc/linux/drivers/gpu/drm/exynos/
H A Dexynos_drm_fimd.c1 // SPDX-License-Identifier: GPL-2.0-or-later
63 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
65 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
77 /* display mode change control register except exynos4 */
85 #define LCD_WR_SETUP(x) ((x) << 12)
194 u32 clkdiv; member
202 { .compatible = "samsung,s3c6400-fimd",
204 { .compatible = "samsung,s5pv210-fimd",
206 { .compatible = "samsung,exynos3250-fimd",
208 { .compatible = "samsung,exynos4210-fimd",
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dfsl_lbc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2004-2008,2010-2011 Freescale Semiconductor, Inc.
16 /* BR - Base Registers
33 #define BR_PS_8 0x00000800 /* Port Size 8 bit */
34 #define BR_PS_16 0x00001000 /* Port Size 16 bit */
35 #define BR_PS_32 0x00001800 /* Port Size 32 bit */
84 /* OR - Option Registers
100 #define OR_GPCM_BCTLD_SHIFT 12
141 /* helpers to convert values into an OR address mask (GPCM mode) */
142 #define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */
[all …]
/openbmc/linux/drivers/gpu/drm/tilcdc/
H A Dtilcdc_crtc.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
65 struct drm_device *dev = crtc->dev; in set_scanout()
66 struct tilcdc_drm_private *priv = dev->dev_private; in set_scanout()
73 start = gem->dma_addr + fb->offsets[0] + in set_scanout()
74 crtc->y * fb->pitches[0] + in set_scanout()
75 crtc->x * fb->format->cpp[0]; in set_scanout()
77 end = start + (crtc->mode.vdisplay * fb->pitches[0]); in set_scanout()
84 if (priv->rev == 1) in set_scanout()
85 end -= 1; in set_scanout()
[all …]
/openbmc/linux/drivers/net/ethernet/
H A Dethoc.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2007-2008 Avionic Design Development GmbH
6 * Copyright (C) 2008-2009 Avionic Design GmbH
8 * Written by Thierry Reding <thierry.reding@avionic-design.de>
11 #include <linux/dma-mapping.h>
55 /* mode register */
60 #define MODER_IAM (1 << 4) /* individual address mode */
61 #define MODER_PRO (1 << 5) /* promiscuous mode */
64 #define MODER_NBO (1 << 8) /* no back-off */
68 #define MODER_DCRC (1 << 12) /* delayed CRC enable */
[all …]
/openbmc/linux/drivers/video/fbdev/
H A Ds3c-fb.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* linux/drivers/video/s3c-fb.c
5 * Copyright 2008-2010 Simtec Electronics
15 #include <linux/dma-mapping.h>
31 * setting of the alpha-blending functions that each window has, so only
35 * output timings and as the control for the output power-down state.
38 /* note, the previous use of <mach/regs-fb.h> to get platform specific data
58 #define VALID_BPP(x) (1 << ((x) - 1))
67 * struct s3c_fb_variant - fb variant information
83 * @has_clksel: Set if VIDCON0 register has CLKSEL bit.
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/include/
H A Dchipcommon.h1 // SPDX-License-Identifier: ISC
49 /* gpio - cleared only by power-on-reset */
79 u32 clkdiv; /* corerev >= 3 */ member
234 #define CC_CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
238 #define CC_CAP_UARTGPIO 0x00000020 /* UARTs own GPIOs 15:12 */
251 #define CC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */
262 #define CC_SR_CTL0_ENABLE_MASK BIT(0)
/openbmc/linux/include/linux/ssb/
H A Dssb_driver_chipcommon.h1 /* SPDX-License-Identifier: GPL-2.0-only */
27 #define SSB_CHIPCO_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */
30 #define SSB_CHIPCO_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
52 #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
174 #define SSB_CHIPCO_SYSCLKCTL_CLKDIV 0xFFFF0000 /* ClkDiv (ILP = 1/(4+divisor)) */
296 #define SSB_PMU1_PLLCTL2_NDIVMODE 0x000E0000 /* NDIV mode */
321 #define SSB_PMURES_4312_BB_PLL_FILTBYP 12
338 #define SSB_PMURES_4325_LNLDO4_PU 12
362 #define SSB_PMURES_4328_BG_FILTBYP 12
384 #define SSB_PMURES_5354_BG_FILTBYP 12
[all …]
/openbmc/linux/include/linux/bcma/
H A Dbcma_driver_chipcommon.h1 /* SPDX-License-Identifier: GPL-2.0 */
23 #define BCMA_CC_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */
26 #define BCMA_CC_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
49 #define BCMA_CC_CAP_64BIT 0x08000000 /* 64-bit Backplane */
103 #define BCMA_CC_CHIPST_4706_PKG_OPTION BIT(0) /* 0: full-featured package 1: low-cost package */
104 #define BCMA_CC_CHIPST_4706_SFLASH_PRESENT BIT(1) /* 0: parallel, 1: serial flash is present */
105 #define BCMA_CC_CHIPST_4706_SFLASH_TYPE BIT(2) /* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
106 #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
107 #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
108 #define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
[all …]
/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Daiutils.c73 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */
90 /* 43224 chip-specific ChipControl register bits */
92 /* 12 mA drive strength */
94 /* 12 mA drive strength for later 43224s */
109 /* 4331 chip-specific ChipControl register bits */
116 /* sprom/gpio13-15 mux */
147 /* 4319 chip-specific ChipStatus register bits */
162 /* gpio [8], sdio/usb mode */
178 /* 4336 chip-specific ChipStatus register bits */
194 /* 4313 chip-specific ChipStatus register bits */
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dcpu_init.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2007-2011 Freescale Semiconductor, Inc.
69 clrbits_be32(&usb_phy->pllprg[1], in usb_single_source_clk_configure()
71 setbits_be32(&usb_phy->pllprg[1], in usb_single_source_clk_configure()
83 u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg); in fsl_erratum_a006261_workaround()
90 out_be32(&usb_phy->port1.xcvrprg, xcvrprg); in fsl_erratum_a006261_workaround()
92 xcvrprg = in_be32(&usb_phy->port2.xcvrprg); in fsl_erratum_a006261_workaround()
98 out_be32(&usb_phy->port2.xcvrprg, xcvrprg); in fsl_erratum_a006261_workaround()
102 u32 status = in_be32(&usb_phy->status1); in fsl_erratum_a006261_workaround()
112 setbits_be32(&usb_phy->config1, in fsl_erratum_a006261_workaround()
[all …]
/openbmc/linux/drivers/tty/serial/
H A Damba-pl011.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright (C) 2010 ST-Ericsson SA
11 * This is a generic driver for ARM AMBA-type serial ports. They
12 * have a lot of 16550-like features, but are not register compatible.
35 #include <linux/dma-mapping.h>
82 /* The size of the array - must be last */
262 unsigned int fifosize; /* vendor-specific */
263 unsigned int fixed_baud; /* vendor-set fixed baud rate */
264 char type[12];
282 return uap->reg_offset[reg]; in pl011_reg_to_offset()
[all …]
/openbmc/qemu/pc-bios/
HDu-boot.e500 ... 2d 0 %2d *?[\ %-12s= %6s MHz %-12 ...

12