12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
21c248b7dSInki Dae /* exynos_drm_fimd.c
31c248b7dSInki Dae *
41c248b7dSInki Dae * Copyright (C) 2011 Samsung Electronics Co.Ltd
51c248b7dSInki Dae * Authors:
61c248b7dSInki Dae * Joonyoung Shim <jy0922.shim@samsung.com>
71c248b7dSInki Dae * Inki Dae <inki.dae@samsung.com>
81c248b7dSInki Dae */
91c248b7dSInki Dae
101c248b7dSInki Dae #include <linux/clk.h>
112bda34d7SSam Ravnborg #include <linux/component.h>
122bda34d7SSam Ravnborg #include <linux/kernel.h>
132bda34d7SSam Ravnborg #include <linux/mfd/syscon.h>
143f1c781dSSachin Kamat #include <linux/of.h>
152bda34d7SSam Ravnborg #include <linux/platform_device.h>
16cb91f6a0SJoonyoung Shim #include <linux/pm_runtime.h>
173854fab2SYoungJun Cho #include <linux/regmap.h>
181c248b7dSInki Dae
197f4596f4SVikas Sajjan #include <video/of_display_timing.h>
20111e6055SAndrzej Hajda #include <video/of_videomode.h>
215a213a55SLeela Krishna Amudala #include <video/samsung_fimd.h>
222bda34d7SSam Ravnborg
2390bb087fSVille Syrjälä #include <drm/drm_blend.h>
242bda34d7SSam Ravnborg #include <drm/drm_fourcc.h>
25720cf96dSVille Syrjälä #include <drm/drm_framebuffer.h>
262bda34d7SSam Ravnborg #include <drm/drm_vblank.h>
271c248b7dSInki Dae #include <drm/exynos_drm.h>
281c248b7dSInki Dae
292bda34d7SSam Ravnborg #include "exynos_drm_crtc.h"
301c248b7dSInki Dae #include "exynos_drm_drv.h"
310488f50eSMarek Szyprowski #include "exynos_drm_fb.h"
327ee14cdcSGustavo Padovan #include "exynos_drm_plane.h"
331c248b7dSInki Dae
341c248b7dSInki Dae /*
35b8654b37SSachin Kamat * FIMD stands for Fully Interactive Mobile Display and
361c248b7dSInki Dae * as a display controller, it transfers contents drawn on memory
371c248b7dSInki Dae * to a LCD Panel through Display Interfaces such as RGB or
381c248b7dSInki Dae * CPU Interface.
391c248b7dSInki Dae */
401c248b7dSInki Dae
4166367461SRahul Sharma #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
42111e6055SAndrzej Hajda
431c248b7dSInki Dae /* position control register for hardware window 0, 2 ~ 4.*/
441c248b7dSInki Dae #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
451c248b7dSInki Dae #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
460f10cf14SLeela Krishna Amudala /*
470f10cf14SLeela Krishna Amudala * size control register for hardware windows 0 and alpha control register
480f10cf14SLeela Krishna Amudala * for hardware windows 1 ~ 4
490f10cf14SLeela Krishna Amudala */
500f10cf14SLeela Krishna Amudala #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
510f10cf14SLeela Krishna Amudala /* size control register for hardware windows 1 ~ 2. */
521c248b7dSInki Dae #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
531c248b7dSInki Dae
54453b44a3SGustavo Padovan #define VIDWnALPHA0(win) (VIDW_ALPHA + 0x00 + (win) * 8)
55453b44a3SGustavo Padovan #define VIDWnALPHA1(win) (VIDW_ALPHA + 0x04 + (win) * 8)
56453b44a3SGustavo Padovan
571c248b7dSInki Dae #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
58cb11b3f1SGustavo Padovan #define VIDWx_BUF_START_S(win, buf) (VIDW_BUF_START_S(buf) + (win) * 8)
591c248b7dSInki Dae #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
601c248b7dSInki Dae #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
611c248b7dSInki Dae
621c248b7dSInki Dae /* color key control register for hardware window 1 ~ 4. */
630f10cf14SLeela Krishna Amudala #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
641c248b7dSInki Dae /* color key value register for hardware window 1 ~ 4. */
650f10cf14SLeela Krishna Amudala #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
661c248b7dSInki Dae
67b5bf0f1eSInki Dae /* I80 trigger control register */
683854fab2SYoungJun Cho #define TRIGCON 0x1A4
69b5bf0f1eSInki Dae #define TRGMODE_ENABLE (1 << 0)
70b5bf0f1eSInki Dae #define SWTRGCMD_ENABLE (1 << 1)
716bdc92eeSKrzysztof Kozlowski /* Exynos3250, 3472, 5260 5410, 5420 and 5422 only supported. */
72b5bf0f1eSInki Dae #define HWTRGEN_ENABLE (1 << 3)
73b5bf0f1eSInki Dae #define HWTRGMASK_ENABLE (1 << 4)
746bdc92eeSKrzysztof Kozlowski /* Exynos3250, 3472, 5260, 5420 and 5422 only supported. */
75b5bf0f1eSInki Dae #define HWTRIGEN_PER_ENABLE (1 << 31)
763854fab2SYoungJun Cho
773854fab2SYoungJun Cho /* display mode change control register except exynos4 */
783854fab2SYoungJun Cho #define VIDOUT_CON 0x000
793854fab2SYoungJun Cho #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8)
803854fab2SYoungJun Cho
813854fab2SYoungJun Cho /* I80 interface control for main LDI register */
823854fab2SYoungJun Cho #define I80IFCONFAx(x) (0x1B0 + (x) * 4)
833854fab2SYoungJun Cho #define I80IFCONFBx(x) (0x1B8 + (x) * 4)
843854fab2SYoungJun Cho #define LCD_CS_SETUP(x) ((x) << 16)
853854fab2SYoungJun Cho #define LCD_WR_SETUP(x) ((x) << 12)
863854fab2SYoungJun Cho #define LCD_WR_ACTIVE(x) ((x) << 8)
873854fab2SYoungJun Cho #define LCD_WR_HOLD(x) ((x) << 4)
883854fab2SYoungJun Cho #define I80IFEN_ENABLE (1 << 0)
893854fab2SYoungJun Cho
901c248b7dSInki Dae /* FIMD has totally five hardware windows. */
911c248b7dSInki Dae #define WINDOWS_NR 5
921c248b7dSInki Dae
93a6f75aa1SInki Dae /* HW trigger flag on i80 panel. */
94a6f75aa1SInki Dae #define I80_HW_TRG (1 << 1)
95a6f75aa1SInki Dae
96e2e13389SLeela Krishna Amudala struct fimd_driver_data {
97e2e13389SLeela Krishna Amudala unsigned int timing_base;
983854fab2SYoungJun Cho unsigned int lcdblk_offset;
993854fab2SYoungJun Cho unsigned int lcdblk_vt_shift;
1003854fab2SYoungJun Cho unsigned int lcdblk_bypass_shift;
1011feafd3aSChanho Park unsigned int lcdblk_mic_bypass_shift;
102a6f75aa1SInki Dae unsigned int trg_type;
103de7af100STomasz Figa
104de7af100STomasz Figa unsigned int has_shadowcon:1;
105411d9ed4STomasz Figa unsigned int has_clksel:1;
1065cc4621aSInki Dae unsigned int has_limited_fmt:1;
1073854fab2SYoungJun Cho unsigned int has_vidoutcon:1;
1083c3c9c1dSJoonyoung Shim unsigned int has_vtsel:1;
1091feafd3aSChanho Park unsigned int has_mic_bypass:1;
110196e059aSAndrzej Hajda unsigned int has_dp_clk:1;
111a6f75aa1SInki Dae unsigned int has_hw_trigger:1;
112a6f75aa1SInki Dae unsigned int has_trigger_per_te:1;
1132d684f4eSMartin Jücker unsigned int has_bgr_support:1;
114e2e13389SLeela Krishna Amudala };
115e2e13389SLeela Krishna Amudala
116725ddeadSTomasz Figa static struct fimd_driver_data s3c64xx_fimd_driver_data = {
117725ddeadSTomasz Figa .timing_base = 0x0,
118725ddeadSTomasz Figa .has_clksel = 1,
1195cc4621aSInki Dae .has_limited_fmt = 1,
120725ddeadSTomasz Figa };
121725ddeadSTomasz Figa
122fa50b7b4STomasz Figa static struct fimd_driver_data s5pv210_fimd_driver_data = {
123fa50b7b4STomasz Figa .timing_base = 0x0,
124fa50b7b4STomasz Figa .has_shadowcon = 1,
125fa50b7b4STomasz Figa .has_clksel = 1,
126fa50b7b4STomasz Figa };
127fa50b7b4STomasz Figa
128d6ce7b58SInki Dae static struct fimd_driver_data exynos3_fimd_driver_data = {
129d6ce7b58SInki Dae .timing_base = 0x20000,
130d6ce7b58SInki Dae .lcdblk_offset = 0x210,
131d6ce7b58SInki Dae .lcdblk_bypass_shift = 1,
132d6ce7b58SInki Dae .has_shadowcon = 1,
133d6ce7b58SInki Dae .has_vidoutcon = 1,
134d6ce7b58SInki Dae };
135d6ce7b58SInki Dae
1366ecf18f9SSachin Kamat static struct fimd_driver_data exynos4_fimd_driver_data = {
137e2e13389SLeela Krishna Amudala .timing_base = 0x0,
1383854fab2SYoungJun Cho .lcdblk_offset = 0x210,
1393854fab2SYoungJun Cho .lcdblk_vt_shift = 10,
1403854fab2SYoungJun Cho .lcdblk_bypass_shift = 1,
141de7af100STomasz Figa .has_shadowcon = 1,
1423c3c9c1dSJoonyoung Shim .has_vtsel = 1,
1432d684f4eSMartin Jücker .has_bgr_support = 1,
144e2e13389SLeela Krishna Amudala };
145e2e13389SLeela Krishna Amudala
1466ecf18f9SSachin Kamat static struct fimd_driver_data exynos5_fimd_driver_data = {
147e2e13389SLeela Krishna Amudala .timing_base = 0x20000,
1483854fab2SYoungJun Cho .lcdblk_offset = 0x214,
1493854fab2SYoungJun Cho .lcdblk_vt_shift = 24,
1503854fab2SYoungJun Cho .lcdblk_bypass_shift = 15,
151de7af100STomasz Figa .has_shadowcon = 1,
1523854fab2SYoungJun Cho .has_vidoutcon = 1,
1533c3c9c1dSJoonyoung Shim .has_vtsel = 1,
154196e059aSAndrzej Hajda .has_dp_clk = 1,
1552d684f4eSMartin Jücker .has_bgr_support = 1,
156e2e13389SLeela Krishna Amudala };
157e2e13389SLeela Krishna Amudala
1581feafd3aSChanho Park static struct fimd_driver_data exynos5420_fimd_driver_data = {
1591feafd3aSChanho Park .timing_base = 0x20000,
1601feafd3aSChanho Park .lcdblk_offset = 0x214,
1611feafd3aSChanho Park .lcdblk_vt_shift = 24,
1621feafd3aSChanho Park .lcdblk_bypass_shift = 15,
1631feafd3aSChanho Park .lcdblk_mic_bypass_shift = 11,
1641feafd3aSChanho Park .has_shadowcon = 1,
1651feafd3aSChanho Park .has_vidoutcon = 1,
1661feafd3aSChanho Park .has_vtsel = 1,
1671feafd3aSChanho Park .has_mic_bypass = 1,
168196e059aSAndrzej Hajda .has_dp_clk = 1,
1692d684f4eSMartin Jücker .has_bgr_support = 1,
1701feafd3aSChanho Park };
1711feafd3aSChanho Park
1721c248b7dSInki Dae struct fimd_context {
173bb7704d6SSean Paul struct device *dev;
17440c8ab4bSSean Paul struct drm_device *drm_dev;
17507dc3678SMarek Szyprowski void *dma_priv;
17693bca243SGustavo Padovan struct exynos_drm_crtc *crtc;
1777ee14cdcSGustavo Padovan struct exynos_drm_plane planes[WINDOWS_NR];
178fd2d2fc2SMarek Szyprowski struct exynos_drm_plane_config configs[WINDOWS_NR];
1791c248b7dSInki Dae struct clk *bus_clk;
1801c248b7dSInki Dae struct clk *lcd_clk;
1811c248b7dSInki Dae void __iomem *regs;
1823854fab2SYoungJun Cho struct regmap *sysreg;
1831c248b7dSInki Dae unsigned long irq_flags;
1843854fab2SYoungJun Cho u32 vidcon0;
1851c248b7dSInki Dae u32 vidcon1;
1863854fab2SYoungJun Cho u32 vidout_con;
1873854fab2SYoungJun Cho u32 i80ifcon;
1883854fab2SYoungJun Cho bool i80_if;
189cb91f6a0SJoonyoung Shim bool suspended;
19001ce113cSPrathyush K wait_queue_head_t wait_vsync_queue;
19101ce113cSPrathyush K atomic_t wait_vsync_event;
1923854fab2SYoungJun Cho atomic_t win_updated;
1933854fab2SYoungJun Cho atomic_t triggering;
194c96fdfdeSAndrzej Hajda u32 clkdiv;
1951c248b7dSInki Dae
196e1a7b9b4SMarek Szyprowski const struct fimd_driver_data *driver_data;
1972b8376c8SGustavo Padovan struct drm_encoder *encoder;
198196e059aSAndrzej Hajda struct exynos_drm_clk dp_clk;
1991c248b7dSInki Dae };
2001c248b7dSInki Dae
201d636ead8SJoonyoung Shim static const struct of_device_id fimd_driver_dt_match[] = {
202725ddeadSTomasz Figa { .compatible = "samsung,s3c6400-fimd",
203725ddeadSTomasz Figa .data = &s3c64xx_fimd_driver_data },
204fa50b7b4STomasz Figa { .compatible = "samsung,s5pv210-fimd",
205fa50b7b4STomasz Figa .data = &s5pv210_fimd_driver_data },
206d6ce7b58SInki Dae { .compatible = "samsung,exynos3250-fimd",
207d6ce7b58SInki Dae .data = &exynos3_fimd_driver_data },
2085830daf8SVikas Sajjan { .compatible = "samsung,exynos4210-fimd",
209d636ead8SJoonyoung Shim .data = &exynos4_fimd_driver_data },
2105830daf8SVikas Sajjan { .compatible = "samsung,exynos5250-fimd",
211d636ead8SJoonyoung Shim .data = &exynos5_fimd_driver_data },
2121feafd3aSChanho Park { .compatible = "samsung,exynos5420-fimd",
2131feafd3aSChanho Park .data = &exynos5420_fimd_driver_data },
214d636ead8SJoonyoung Shim {},
215d636ead8SJoonyoung Shim };
2160262ceebSSjoerd Simons MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
217d636ead8SJoonyoung Shim
218fd2d2fc2SMarek Szyprowski static const enum drm_plane_type fimd_win_types[WINDOWS_NR] = {
219fd2d2fc2SMarek Szyprowski DRM_PLANE_TYPE_PRIMARY,
220fd2d2fc2SMarek Szyprowski DRM_PLANE_TYPE_OVERLAY,
221fd2d2fc2SMarek Szyprowski DRM_PLANE_TYPE_OVERLAY,
222fd2d2fc2SMarek Szyprowski DRM_PLANE_TYPE_OVERLAY,
223fd2d2fc2SMarek Szyprowski DRM_PLANE_TYPE_CURSOR,
224fd2d2fc2SMarek Szyprowski };
225fd2d2fc2SMarek Szyprowski
226fbbb1e1aSMarek Szyprowski static const uint32_t fimd_formats[] = {
227fbbb1e1aSMarek Szyprowski DRM_FORMAT_C8,
228fbbb1e1aSMarek Szyprowski DRM_FORMAT_XRGB1555,
229fbbb1e1aSMarek Szyprowski DRM_FORMAT_RGB565,
230fbbb1e1aSMarek Szyprowski DRM_FORMAT_XRGB8888,
231fbbb1e1aSMarek Szyprowski DRM_FORMAT_ARGB8888,
232fbbb1e1aSMarek Szyprowski };
233fbbb1e1aSMarek Szyprowski
2342d684f4eSMartin Jücker static const uint32_t fimd_extended_formats[] = {
2352d684f4eSMartin Jücker DRM_FORMAT_C8,
2362d684f4eSMartin Jücker DRM_FORMAT_XRGB1555,
2372d684f4eSMartin Jücker DRM_FORMAT_XBGR1555,
2382d684f4eSMartin Jücker DRM_FORMAT_RGB565,
2392d684f4eSMartin Jücker DRM_FORMAT_BGR565,
2402d684f4eSMartin Jücker DRM_FORMAT_XRGB8888,
2412d684f4eSMartin Jücker DRM_FORMAT_XBGR8888,
2422d684f4eSMartin Jücker DRM_FORMAT_ARGB8888,
2432d684f4eSMartin Jücker DRM_FORMAT_ABGR8888,
2442d684f4eSMartin Jücker };
2452d684f4eSMartin Jücker
2466f8ee5c2SChristoph Manszewski static const unsigned int capabilities[WINDOWS_NR] = {
2476f8ee5c2SChristoph Manszewski 0,
2483b5129b3SChristoph Manszewski EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
2493b5129b3SChristoph Manszewski EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
2503b5129b3SChristoph Manszewski EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
2513b5129b3SChristoph Manszewski EXYNOS_DRM_PLANE_CAP_WIN_BLEND | EXYNOS_DRM_PLANE_CAP_PIX_BLEND,
2526f8ee5c2SChristoph Manszewski };
2536f8ee5c2SChristoph Manszewski
fimd_set_bits(struct fimd_context * ctx,u32 reg,u32 mask,u32 val)2546f8ee5c2SChristoph Manszewski static inline void fimd_set_bits(struct fimd_context *ctx, u32 reg, u32 mask,
2556f8ee5c2SChristoph Manszewski u32 val)
2566f8ee5c2SChristoph Manszewski {
2576f8ee5c2SChristoph Manszewski val = (val & mask) | (readl(ctx->regs + reg) & ~mask);
2586f8ee5c2SChristoph Manszewski writel(val, ctx->regs + reg);
2596f8ee5c2SChristoph Manszewski }
2606f8ee5c2SChristoph Manszewski
fimd_enable_vblank(struct exynos_drm_crtc * crtc)261fb88e214SMarek Szyprowski static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
262fb88e214SMarek Szyprowski {
263fb88e214SMarek Szyprowski struct fimd_context *ctx = crtc->ctx;
264fb88e214SMarek Szyprowski u32 val;
265fb88e214SMarek Szyprowski
266fb88e214SMarek Szyprowski if (ctx->suspended)
267fb88e214SMarek Szyprowski return -EPERM;
268fb88e214SMarek Szyprowski
269fb88e214SMarek Szyprowski if (!test_and_set_bit(0, &ctx->irq_flags)) {
270fb88e214SMarek Szyprowski val = readl(ctx->regs + VIDINTCON0);
271fb88e214SMarek Szyprowski
272fb88e214SMarek Szyprowski val |= VIDINTCON0_INT_ENABLE;
273fb88e214SMarek Szyprowski
274fb88e214SMarek Szyprowski if (ctx->i80_if) {
275fb88e214SMarek Szyprowski val |= VIDINTCON0_INT_I80IFDONE;
276fb88e214SMarek Szyprowski val |= VIDINTCON0_INT_SYSMAINCON;
277fb88e214SMarek Szyprowski val &= ~VIDINTCON0_INT_SYSSUBCON;
278fb88e214SMarek Szyprowski } else {
279fb88e214SMarek Szyprowski val |= VIDINTCON0_INT_FRAME;
280fb88e214SMarek Szyprowski
281fb88e214SMarek Szyprowski val &= ~VIDINTCON0_FRAMESEL0_MASK;
28282a01783SAndrzej Hajda val |= VIDINTCON0_FRAMESEL0_FRONTPORCH;
283fb88e214SMarek Szyprowski val &= ~VIDINTCON0_FRAMESEL1_MASK;
284fb88e214SMarek Szyprowski val |= VIDINTCON0_FRAMESEL1_NONE;
285fb88e214SMarek Szyprowski }
286fb88e214SMarek Szyprowski
287fb88e214SMarek Szyprowski writel(val, ctx->regs + VIDINTCON0);
288fb88e214SMarek Szyprowski }
289fb88e214SMarek Szyprowski
290fb88e214SMarek Szyprowski return 0;
291fb88e214SMarek Szyprowski }
292fb88e214SMarek Szyprowski
fimd_disable_vblank(struct exynos_drm_crtc * crtc)293fb88e214SMarek Szyprowski static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
294fb88e214SMarek Szyprowski {
295fb88e214SMarek Szyprowski struct fimd_context *ctx = crtc->ctx;
296fb88e214SMarek Szyprowski u32 val;
297fb88e214SMarek Szyprowski
298fb88e214SMarek Szyprowski if (ctx->suspended)
299fb88e214SMarek Szyprowski return;
300fb88e214SMarek Szyprowski
301fb88e214SMarek Szyprowski if (test_and_clear_bit(0, &ctx->irq_flags)) {
302fb88e214SMarek Szyprowski val = readl(ctx->regs + VIDINTCON0);
303fb88e214SMarek Szyprowski
304fb88e214SMarek Szyprowski val &= ~VIDINTCON0_INT_ENABLE;
305fb88e214SMarek Szyprowski
306fb88e214SMarek Szyprowski if (ctx->i80_if) {
307fb88e214SMarek Szyprowski val &= ~VIDINTCON0_INT_I80IFDONE;
308fb88e214SMarek Szyprowski val &= ~VIDINTCON0_INT_SYSMAINCON;
309fb88e214SMarek Szyprowski val &= ~VIDINTCON0_INT_SYSSUBCON;
310fb88e214SMarek Szyprowski } else
311fb88e214SMarek Szyprowski val &= ~VIDINTCON0_INT_FRAME;
312fb88e214SMarek Szyprowski
313fb88e214SMarek Szyprowski writel(val, ctx->regs + VIDINTCON0);
314fb88e214SMarek Szyprowski }
315fb88e214SMarek Szyprowski }
316fb88e214SMarek Szyprowski
fimd_wait_for_vblank(struct exynos_drm_crtc * crtc)31793bca243SGustavo Padovan static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
318f13bdbd1SAkshu Agrawal {
31993bca243SGustavo Padovan struct fimd_context *ctx = crtc->ctx;
320f13bdbd1SAkshu Agrawal
321f13bdbd1SAkshu Agrawal if (ctx->suspended)
322f13bdbd1SAkshu Agrawal return;
323f13bdbd1SAkshu Agrawal
324f13bdbd1SAkshu Agrawal atomic_set(&ctx->wait_vsync_event, 1);
325f13bdbd1SAkshu Agrawal
326f13bdbd1SAkshu Agrawal /*
327f13bdbd1SAkshu Agrawal * wait for FIMD to signal VSYNC interrupt or return after
328f13bdbd1SAkshu Agrawal * timeout which is set to 50ms (refresh rate of 20).
329f13bdbd1SAkshu Agrawal */
330f13bdbd1SAkshu Agrawal if (!wait_event_timeout(ctx->wait_vsync_queue,
331f13bdbd1SAkshu Agrawal !atomic_read(&ctx->wait_vsync_event),
332f13bdbd1SAkshu Agrawal HZ/20))
3336be90056SInki Dae DRM_DEV_DEBUG_KMS(ctx->dev, "vblank wait timed out.\n");
334f13bdbd1SAkshu Agrawal }
335f13bdbd1SAkshu Agrawal
fimd_enable_video_output(struct fimd_context * ctx,unsigned int win,bool enable)3365b1d5bc6STobias Jakobi static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win,
337f181a543SYoungJun Cho bool enable)
338f181a543SYoungJun Cho {
339f181a543SYoungJun Cho u32 val = readl(ctx->regs + WINCON(win));
340f181a543SYoungJun Cho
341f181a543SYoungJun Cho if (enable)
342f181a543SYoungJun Cho val |= WINCONx_ENWIN;
343f181a543SYoungJun Cho else
344f181a543SYoungJun Cho val &= ~WINCONx_ENWIN;
345f181a543SYoungJun Cho
346f181a543SYoungJun Cho writel(val, ctx->regs + WINCON(win));
347f181a543SYoungJun Cho }
348f181a543SYoungJun Cho
fimd_enable_shadow_channel_path(struct fimd_context * ctx,unsigned int win,bool enable)3495b1d5bc6STobias Jakobi static void fimd_enable_shadow_channel_path(struct fimd_context *ctx,
3505b1d5bc6STobias Jakobi unsigned int win,
351999d8b31SYoungJun Cho bool enable)
352999d8b31SYoungJun Cho {
353999d8b31SYoungJun Cho u32 val = readl(ctx->regs + SHADOWCON);
354999d8b31SYoungJun Cho
355999d8b31SYoungJun Cho if (enable)
356999d8b31SYoungJun Cho val |= SHADOWCON_CHx_ENABLE(win);
357999d8b31SYoungJun Cho else
358999d8b31SYoungJun Cho val &= ~SHADOWCON_CHx_ENABLE(win);
359999d8b31SYoungJun Cho
360999d8b31SYoungJun Cho writel(val, ctx->regs + SHADOWCON);
361999d8b31SYoungJun Cho }
362999d8b31SYoungJun Cho
fimd_clear_channels(struct exynos_drm_crtc * crtc)363445d3bedSInki Dae static int fimd_clear_channels(struct exynos_drm_crtc *crtc)
364f13bdbd1SAkshu Agrawal {
365fc2e013fSHyungwon Hwang struct fimd_context *ctx = crtc->ctx;
3665b1d5bc6STobias Jakobi unsigned int win, ch_enabled = 0;
367445d3bedSInki Dae int ret;
368f13bdbd1SAkshu Agrawal
369fb88e214SMarek Szyprowski /* Hardware is in unknown state, so ensure it gets enabled properly */
370445d3bedSInki Dae ret = pm_runtime_resume_and_get(ctx->dev);
371445d3bedSInki Dae if (ret < 0) {
372445d3bedSInki Dae dev_err(ctx->dev, "failed to enable FIMD device.\n");
373445d3bedSInki Dae return ret;
374445d3bedSInki Dae }
375fb88e214SMarek Szyprowski
376fb88e214SMarek Szyprowski clk_prepare_enable(ctx->bus_clk);
377fb88e214SMarek Szyprowski clk_prepare_enable(ctx->lcd_clk);
378fb88e214SMarek Szyprowski
379f13bdbd1SAkshu Agrawal /* Check if any channel is enabled. */
380f13bdbd1SAkshu Agrawal for (win = 0; win < WINDOWS_NR; win++) {
381eb8a3bf7SMarek Szyprowski u32 val = readl(ctx->regs + WINCON(win));
382eb8a3bf7SMarek Szyprowski
383eb8a3bf7SMarek Szyprowski if (val & WINCONx_ENWIN) {
384f181a543SYoungJun Cho fimd_enable_video_output(ctx, win, false);
385eb8a3bf7SMarek Szyprowski
386999d8b31SYoungJun Cho if (ctx->driver_data->has_shadowcon)
387999d8b31SYoungJun Cho fimd_enable_shadow_channel_path(ctx, win,
388999d8b31SYoungJun Cho false);
389999d8b31SYoungJun Cho
390f13bdbd1SAkshu Agrawal ch_enabled = 1;
391f13bdbd1SAkshu Agrawal }
392f13bdbd1SAkshu Agrawal }
393f13bdbd1SAkshu Agrawal
394f13bdbd1SAkshu Agrawal /* Wait for vsync, as disable channel takes effect at next vsync */
395eb8a3bf7SMarek Szyprowski if (ch_enabled) {
396fb88e214SMarek Szyprowski ctx->suspended = false;
397fb88e214SMarek Szyprowski
398fb88e214SMarek Szyprowski fimd_enable_vblank(ctx->crtc);
39992dc7a04SJoonyoung Shim fimd_wait_for_vblank(ctx->crtc);
400fb88e214SMarek Szyprowski fimd_disable_vblank(ctx->crtc);
401fb88e214SMarek Szyprowski
402fb88e214SMarek Szyprowski ctx->suspended = true;
403eb8a3bf7SMarek Szyprowski }
404fb88e214SMarek Szyprowski
405fb88e214SMarek Szyprowski clk_disable_unprepare(ctx->lcd_clk);
406fb88e214SMarek Szyprowski clk_disable_unprepare(ctx->bus_clk);
407fb88e214SMarek Szyprowski
408fb88e214SMarek Szyprowski pm_runtime_put(ctx->dev);
409445d3bedSInki Dae
410445d3bedSInki Dae return 0;
411f13bdbd1SAkshu Agrawal }
412f13bdbd1SAkshu Agrawal
413c96fdfdeSAndrzej Hajda
fimd_atomic_check(struct exynos_drm_crtc * crtc,struct drm_crtc_state * state)414c96fdfdeSAndrzej Hajda static int fimd_atomic_check(struct exynos_drm_crtc *crtc,
415c96fdfdeSAndrzej Hajda struct drm_crtc_state *state)
416a968e727SSean Paul {
417c96fdfdeSAndrzej Hajda struct drm_display_mode *mode = &state->adjusted_mode;
418c96fdfdeSAndrzej Hajda struct fimd_context *ctx = crtc->ctx;
419c96fdfdeSAndrzej Hajda unsigned long ideal_clk, lcd_rate;
420a968e727SSean Paul u32 clkdiv;
421a968e727SSean Paul
422fa9971d6STobias Jakobi if (mode->clock == 0) {
4236f83d208SInki Dae DRM_DEV_ERROR(ctx->dev, "Mode has zero clock value.\n");
424c96fdfdeSAndrzej Hajda return -EINVAL;
425fa9971d6STobias Jakobi }
426fa9971d6STobias Jakobi
427fa9971d6STobias Jakobi ideal_clk = mode->clock * 1000;
428fa9971d6STobias Jakobi
4293854fab2SYoungJun Cho if (ctx->i80_if) {
4303854fab2SYoungJun Cho /*
4313854fab2SYoungJun Cho * The frame done interrupt should be occurred prior to the
4323854fab2SYoungJun Cho * next TE signal.
4333854fab2SYoungJun Cho */
4343854fab2SYoungJun Cho ideal_clk *= 2;
4353854fab2SYoungJun Cho }
4363854fab2SYoungJun Cho
437c96fdfdeSAndrzej Hajda lcd_rate = clk_get_rate(ctx->lcd_clk);
438c96fdfdeSAndrzej Hajda if (2 * lcd_rate < ideal_clk) {
4396f83d208SInki Dae DRM_DEV_ERROR(ctx->dev,
4406f83d208SInki Dae "sclk_fimd clock too low(%lu) for requested pixel clock(%lu)\n",
441c96fdfdeSAndrzej Hajda lcd_rate, ideal_clk);
442c96fdfdeSAndrzej Hajda return -EINVAL;
443c96fdfdeSAndrzej Hajda }
444a968e727SSean Paul
445c96fdfdeSAndrzej Hajda /* Find the clock divider value that gets us closest to ideal_clk */
446c96fdfdeSAndrzej Hajda clkdiv = DIV_ROUND_CLOSEST(lcd_rate, ideal_clk);
447c96fdfdeSAndrzej Hajda if (clkdiv >= 0x200) {
4486f83d208SInki Dae DRM_DEV_ERROR(ctx->dev, "requested pixel clock(%lu) too low\n",
4496f83d208SInki Dae ideal_clk);
450c96fdfdeSAndrzej Hajda return -EINVAL;
451c96fdfdeSAndrzej Hajda }
452c96fdfdeSAndrzej Hajda
453c96fdfdeSAndrzej Hajda ctx->clkdiv = (clkdiv < 0x100) ? clkdiv : 0xff;
454c96fdfdeSAndrzej Hajda
455c96fdfdeSAndrzej Hajda return 0;
456a968e727SSean Paul }
457a968e727SSean Paul
fimd_setup_trigger(struct fimd_context * ctx)458a6f75aa1SInki Dae static void fimd_setup_trigger(struct fimd_context *ctx)
459a6f75aa1SInki Dae {
460a6f75aa1SInki Dae void __iomem *timing_base = ctx->regs + ctx->driver_data->timing_base;
461a6f75aa1SInki Dae u32 trg_type = ctx->driver_data->trg_type;
462a6f75aa1SInki Dae u32 val = readl(timing_base + TRIGCON);
463a6f75aa1SInki Dae
464b5bf0f1eSInki Dae val &= ~(TRGMODE_ENABLE);
465a6f75aa1SInki Dae
466a6f75aa1SInki Dae if (trg_type == I80_HW_TRG) {
467a6f75aa1SInki Dae if (ctx->driver_data->has_hw_trigger)
468b5bf0f1eSInki Dae val |= HWTRGEN_ENABLE | HWTRGMASK_ENABLE;
469a6f75aa1SInki Dae if (ctx->driver_data->has_trigger_per_te)
470b5bf0f1eSInki Dae val |= HWTRIGEN_PER_ENABLE;
471a6f75aa1SInki Dae } else {
472b5bf0f1eSInki Dae val |= TRGMODE_ENABLE;
473a6f75aa1SInki Dae }
474a6f75aa1SInki Dae
475a6f75aa1SInki Dae writel(val, timing_base + TRIGCON);
476a6f75aa1SInki Dae }
477a6f75aa1SInki Dae
fimd_commit(struct exynos_drm_crtc * crtc)47893bca243SGustavo Padovan static void fimd_commit(struct exynos_drm_crtc *crtc)
4791c248b7dSInki Dae {
48093bca243SGustavo Padovan struct fimd_context *ctx = crtc->ctx;
481020e79deSJoonyoung Shim struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
482e1a7b9b4SMarek Szyprowski const struct fimd_driver_data *driver_data = ctx->driver_data;
4833854fab2SYoungJun Cho void *timing_base = ctx->regs + driver_data->timing_base;
484c96fdfdeSAndrzej Hajda u32 val;
4851c248b7dSInki Dae
486e30d4bcfSInki Dae if (ctx->suspended)
487e30d4bcfSInki Dae return;
488e30d4bcfSInki Dae
489a968e727SSean Paul /* nothing to do if we haven't set the mode yet */
490a968e727SSean Paul if (mode->htotal == 0 || mode->vtotal == 0)
491a968e727SSean Paul return;
492a968e727SSean Paul
4933854fab2SYoungJun Cho if (ctx->i80_if) {
4943854fab2SYoungJun Cho val = ctx->i80ifcon | I80IFEN_ENABLE;
4953854fab2SYoungJun Cho writel(val, timing_base + I80IFCONFAx(0));
4963854fab2SYoungJun Cho
4973854fab2SYoungJun Cho /* disable auto frame rate */
4983854fab2SYoungJun Cho writel(0, timing_base + I80IFCONFBx(0));
4993854fab2SYoungJun Cho
5003854fab2SYoungJun Cho /* set video type selection to I80 interface */
5013c3c9c1dSJoonyoung Shim if (driver_data->has_vtsel && ctx->sysreg &&
5023c3c9c1dSJoonyoung Shim regmap_update_bits(ctx->sysreg,
5033854fab2SYoungJun Cho driver_data->lcdblk_offset,
5043854fab2SYoungJun Cho 0x3 << driver_data->lcdblk_vt_shift,
5053854fab2SYoungJun Cho 0x1 << driver_data->lcdblk_vt_shift)) {
5066f83d208SInki Dae DRM_DEV_ERROR(ctx->dev,
5076f83d208SInki Dae "Failed to update sysreg for I80 i/f.\n");
5083854fab2SYoungJun Cho return;
5093854fab2SYoungJun Cho }
5103854fab2SYoungJun Cho } else {
5113854fab2SYoungJun Cho int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
5123854fab2SYoungJun Cho u32 vidcon1;
5133854fab2SYoungJun Cho
5141417f109SSean Paul /* setup polarity values */
5151417f109SSean Paul vidcon1 = ctx->vidcon1;
5161417f109SSean Paul if (mode->flags & DRM_MODE_FLAG_NVSYNC)
5171417f109SSean Paul vidcon1 |= VIDCON1_INV_VSYNC;
5181417f109SSean Paul if (mode->flags & DRM_MODE_FLAG_NHSYNC)
5191417f109SSean Paul vidcon1 |= VIDCON1_INV_HSYNC;
5201417f109SSean Paul writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
5211c248b7dSInki Dae
5221c248b7dSInki Dae /* setup vertical timing values. */
523a968e727SSean Paul vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
5248b4cad23SAndrzej Hajda vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
5258b4cad23SAndrzej Hajda vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
526a968e727SSean Paul
527a968e727SSean Paul val = VIDTCON0_VBPD(vbpd - 1) |
528a968e727SSean Paul VIDTCON0_VFPD(vfpd - 1) |
529a968e727SSean Paul VIDTCON0_VSPW(vsync_len - 1);
530e2e13389SLeela Krishna Amudala writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
5311c248b7dSInki Dae
5321c248b7dSInki Dae /* setup horizontal timing values. */
533a968e727SSean Paul hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
5348b4cad23SAndrzej Hajda hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
5358b4cad23SAndrzej Hajda hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
536a968e727SSean Paul
537a968e727SSean Paul val = VIDTCON1_HBPD(hbpd - 1) |
538a968e727SSean Paul VIDTCON1_HFPD(hfpd - 1) |
539a968e727SSean Paul VIDTCON1_HSPW(hsync_len - 1);
540e2e13389SLeela Krishna Amudala writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
5413854fab2SYoungJun Cho }
5423854fab2SYoungJun Cho
5433854fab2SYoungJun Cho if (driver_data->has_vidoutcon)
5443854fab2SYoungJun Cho writel(ctx->vidout_con, timing_base + VIDOUT_CON);
5453854fab2SYoungJun Cho
5463854fab2SYoungJun Cho /* set bypass selection */
5473854fab2SYoungJun Cho if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
5483854fab2SYoungJun Cho driver_data->lcdblk_offset,
5493854fab2SYoungJun Cho 0x1 << driver_data->lcdblk_bypass_shift,
5503854fab2SYoungJun Cho 0x1 << driver_data->lcdblk_bypass_shift)) {
5516f83d208SInki Dae DRM_DEV_ERROR(ctx->dev,
5526f83d208SInki Dae "Failed to update sysreg for bypass setting.\n");
5533854fab2SYoungJun Cho return;
5543854fab2SYoungJun Cho }
5551c248b7dSInki Dae
5561feafd3aSChanho Park /* TODO: When MIC is enabled for display path, the lcdblk_mic_bypass
5571feafd3aSChanho Park * bit should be cleared.
5581feafd3aSChanho Park */
5591feafd3aSChanho Park if (driver_data->has_mic_bypass && ctx->sysreg &&
5601feafd3aSChanho Park regmap_update_bits(ctx->sysreg,
5611feafd3aSChanho Park driver_data->lcdblk_offset,
5621feafd3aSChanho Park 0x1 << driver_data->lcdblk_mic_bypass_shift,
5631feafd3aSChanho Park 0x1 << driver_data->lcdblk_mic_bypass_shift)) {
5646f83d208SInki Dae DRM_DEV_ERROR(ctx->dev,
5656f83d208SInki Dae "Failed to update sysreg for bypass mic.\n");
5661feafd3aSChanho Park return;
5671feafd3aSChanho Park }
5681feafd3aSChanho Park
5691c248b7dSInki Dae /* setup horizontal and vertical display size. */
570a968e727SSean Paul val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
571a968e727SSean Paul VIDTCON2_HOZVAL(mode->hdisplay - 1) |
572a968e727SSean Paul VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
573a968e727SSean Paul VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
574e2e13389SLeela Krishna Amudala writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
5751c248b7dSInki Dae
576a6f75aa1SInki Dae fimd_setup_trigger(ctx);
577a6f75aa1SInki Dae
5781c248b7dSInki Dae /*
5791c248b7dSInki Dae * fields of register with prefix '_F' would be updated
5801c248b7dSInki Dae * at vsync(same as dma start)
5811c248b7dSInki Dae */
5823854fab2SYoungJun Cho val = ctx->vidcon0;
5833854fab2SYoungJun Cho val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
5841d531062SAndrzej Hajda
5851d531062SAndrzej Hajda if (ctx->driver_data->has_clksel)
5861d531062SAndrzej Hajda val |= VIDCON0_CLKSEL_LCD;
5871d531062SAndrzej Hajda
588c96fdfdeSAndrzej Hajda if (ctx->clkdiv > 1)
589c96fdfdeSAndrzej Hajda val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
5901d531062SAndrzej Hajda
5911c248b7dSInki Dae writel(val, ctx->regs + VIDCON0);
5921c248b7dSInki Dae }
5931c248b7dSInki Dae
fimd_win_set_bldeq(struct fimd_context * ctx,unsigned int win,unsigned int alpha,unsigned int pixel_alpha)5943b5129b3SChristoph Manszewski static void fimd_win_set_bldeq(struct fimd_context *ctx, unsigned int win,
5953b5129b3SChristoph Manszewski unsigned int alpha, unsigned int pixel_alpha)
5963b5129b3SChristoph Manszewski {
5973b5129b3SChristoph Manszewski u32 mask = BLENDEQ_A_FUNC_F(0xf) | BLENDEQ_B_FUNC_F(0xf);
5983b5129b3SChristoph Manszewski u32 val = 0;
5993b5129b3SChristoph Manszewski
6003b5129b3SChristoph Manszewski switch (pixel_alpha) {
6013b5129b3SChristoph Manszewski case DRM_MODE_BLEND_PIXEL_NONE:
6023b5129b3SChristoph Manszewski case DRM_MODE_BLEND_COVERAGE:
6033b5129b3SChristoph Manszewski val |= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA_A);
6043b5129b3SChristoph Manszewski val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A);
6053b5129b3SChristoph Manszewski break;
6063b5129b3SChristoph Manszewski case DRM_MODE_BLEND_PREMULTI:
6073b5129b3SChristoph Manszewski default:
6083b5129b3SChristoph Manszewski if (alpha != DRM_BLEND_ALPHA_OPAQUE) {
6093b5129b3SChristoph Manszewski val |= BLENDEQ_A_FUNC_F(BLENDEQ_ALPHA0);
6103b5129b3SChristoph Manszewski val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A);
6113b5129b3SChristoph Manszewski } else {
6123b5129b3SChristoph Manszewski val |= BLENDEQ_A_FUNC_F(BLENDEQ_ONE);
6133b5129b3SChristoph Manszewski val |= BLENDEQ_B_FUNC_F(BLENDEQ_ONE_MINUS_ALPHA_A);
6143b5129b3SChristoph Manszewski }
6153b5129b3SChristoph Manszewski break;
6163b5129b3SChristoph Manszewski }
6173b5129b3SChristoph Manszewski fimd_set_bits(ctx, BLENDEQx(win), mask, val);
6183b5129b3SChristoph Manszewski }
6193b5129b3SChristoph Manszewski
fimd_win_set_bldmod(struct fimd_context * ctx,unsigned int win,unsigned int alpha,unsigned int pixel_alpha)6206f8ee5c2SChristoph Manszewski static void fimd_win_set_bldmod(struct fimd_context *ctx, unsigned int win,
6213b5129b3SChristoph Manszewski unsigned int alpha, unsigned int pixel_alpha)
6226f8ee5c2SChristoph Manszewski {
6236f8ee5c2SChristoph Manszewski u32 win_alpha_l = (alpha >> 8) & 0xf;
6246f8ee5c2SChristoph Manszewski u32 win_alpha_h = alpha >> 12;
6256f8ee5c2SChristoph Manszewski u32 val = 0;
6266f8ee5c2SChristoph Manszewski
6273b5129b3SChristoph Manszewski switch (pixel_alpha) {
6283b5129b3SChristoph Manszewski case DRM_MODE_BLEND_PIXEL_NONE:
6293b5129b3SChristoph Manszewski break;
6303b5129b3SChristoph Manszewski case DRM_MODE_BLEND_COVERAGE:
6313b5129b3SChristoph Manszewski case DRM_MODE_BLEND_PREMULTI:
6323b5129b3SChristoph Manszewski default:
6333b5129b3SChristoph Manszewski val |= WINCON1_ALPHA_SEL;
6343b5129b3SChristoph Manszewski val |= WINCON1_BLD_PIX;
6353b5129b3SChristoph Manszewski val |= WINCON1_ALPHA_MUL;
6363b5129b3SChristoph Manszewski break;
6373b5129b3SChristoph Manszewski }
6383b5129b3SChristoph Manszewski fimd_set_bits(ctx, WINCON(win), WINCONx_BLEND_MODE_MASK, val);
6393b5129b3SChristoph Manszewski
6406f8ee5c2SChristoph Manszewski /* OSD alpha */
6416f8ee5c2SChristoph Manszewski val = VIDISD14C_ALPHA0_R(win_alpha_h) |
6426f8ee5c2SChristoph Manszewski VIDISD14C_ALPHA0_G(win_alpha_h) |
6436f8ee5c2SChristoph Manszewski VIDISD14C_ALPHA0_B(win_alpha_h) |
6446f8ee5c2SChristoph Manszewski VIDISD14C_ALPHA1_R(0x0) |
6456f8ee5c2SChristoph Manszewski VIDISD14C_ALPHA1_G(0x0) |
6466f8ee5c2SChristoph Manszewski VIDISD14C_ALPHA1_B(0x0);
6476f8ee5c2SChristoph Manszewski writel(val, ctx->regs + VIDOSD_C(win));
6486f8ee5c2SChristoph Manszewski
6496f8ee5c2SChristoph Manszewski val = VIDW_ALPHA_R(win_alpha_l) | VIDW_ALPHA_G(win_alpha_l) |
6506f8ee5c2SChristoph Manszewski VIDW_ALPHA_B(win_alpha_l);
6516f8ee5c2SChristoph Manszewski writel(val, ctx->regs + VIDWnALPHA0(win));
6526f8ee5c2SChristoph Manszewski
6536f8ee5c2SChristoph Manszewski val = VIDW_ALPHA_R(0x0) | VIDW_ALPHA_G(0x0) |
6546f8ee5c2SChristoph Manszewski VIDW_ALPHA_B(0x0);
6556f8ee5c2SChristoph Manszewski writel(val, ctx->regs + VIDWnALPHA1(win));
6566f8ee5c2SChristoph Manszewski
6576f8ee5c2SChristoph Manszewski fimd_set_bits(ctx, BLENDCON, BLENDCON_NEW_MASK,
6586f8ee5c2SChristoph Manszewski BLENDCON_NEW_8BIT_ALPHA_VALUE);
6596f8ee5c2SChristoph Manszewski }
6601c248b7dSInki Dae
fimd_win_set_pixfmt(struct fimd_context * ctx,unsigned int win,struct drm_framebuffer * fb,int width)6612eeb2e5eSGustavo Padovan static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win,
6626f8ee5c2SChristoph Manszewski struct drm_framebuffer *fb, int width)
6631c248b7dSInki Dae {
664*38a31370SArnd Bergmann struct exynos_drm_plane *plane = &ctx->planes[win];
6656f8ee5c2SChristoph Manszewski struct exynos_drm_plane_state *state =
666*38a31370SArnd Bergmann to_exynos_plane_state(plane->base.state);
6676f8ee5c2SChristoph Manszewski uint32_t pixel_format = fb->format->format;
6686f8ee5c2SChristoph Manszewski unsigned int alpha = state->base.alpha;
6696f8ee5c2SChristoph Manszewski u32 val = WINCONx_ENWIN;
6703b5129b3SChristoph Manszewski unsigned int pixel_alpha;
6713b5129b3SChristoph Manszewski
6723b5129b3SChristoph Manszewski if (fb->format->has_alpha)
6733b5129b3SChristoph Manszewski pixel_alpha = state->base.pixel_blend_mode;
6743b5129b3SChristoph Manszewski else
6753b5129b3SChristoph Manszewski pixel_alpha = DRM_MODE_BLEND_PIXEL_NONE;
6761c248b7dSInki Dae
6775cc4621aSInki Dae /*
6785cc4621aSInki Dae * In case of s3c64xx, window 0 doesn't support alpha channel.
6795cc4621aSInki Dae * So the request format is ARGB8888 then change it to XRGB8888.
6805cc4621aSInki Dae */
6815cc4621aSInki Dae if (ctx->driver_data->has_limited_fmt && !win) {
6828b704d8aSMarek Szyprowski if (pixel_format == DRM_FORMAT_ARGB8888)
6838b704d8aSMarek Szyprowski pixel_format = DRM_FORMAT_XRGB8888;
6845cc4621aSInki Dae }
6855cc4621aSInki Dae
6868b704d8aSMarek Szyprowski switch (pixel_format) {
687a4f38a80SInki Dae case DRM_FORMAT_C8:
6881c248b7dSInki Dae val |= WINCON0_BPPMODE_8BPP_PALETTE;
6891c248b7dSInki Dae val |= WINCONx_BURSTLEN_8WORD;
6901c248b7dSInki Dae val |= WINCONx_BYTSWP;
6911c248b7dSInki Dae break;
692a4f38a80SInki Dae case DRM_FORMAT_XRGB1555:
6932d684f4eSMartin Jücker case DRM_FORMAT_XBGR1555:
694a4f38a80SInki Dae val |= WINCON0_BPPMODE_16BPP_1555;
695a4f38a80SInki Dae val |= WINCONx_HAWSWP;
696a4f38a80SInki Dae val |= WINCONx_BURSTLEN_16WORD;
697a4f38a80SInki Dae break;
698a4f38a80SInki Dae case DRM_FORMAT_RGB565:
6992d684f4eSMartin Jücker case DRM_FORMAT_BGR565:
7001c248b7dSInki Dae val |= WINCON0_BPPMODE_16BPP_565;
7011c248b7dSInki Dae val |= WINCONx_HAWSWP;
7021c248b7dSInki Dae val |= WINCONx_BURSTLEN_16WORD;
7031c248b7dSInki Dae break;
704a4f38a80SInki Dae case DRM_FORMAT_XRGB8888:
7052d684f4eSMartin Jücker case DRM_FORMAT_XBGR8888:
7061c248b7dSInki Dae val |= WINCON0_BPPMODE_24BPP_888;
7071c248b7dSInki Dae val |= WINCONx_WSWP;
7081c248b7dSInki Dae val |= WINCONx_BURSTLEN_16WORD;
7091c248b7dSInki Dae break;
710a4f38a80SInki Dae case DRM_FORMAT_ARGB8888:
7112d684f4eSMartin Jücker case DRM_FORMAT_ABGR8888:
7125b7b1b7fSTobias Jakobi default:
7133b5129b3SChristoph Manszewski val |= WINCON1_BPPMODE_25BPP_A1888;
7141c248b7dSInki Dae val |= WINCONx_WSWP;
7151c248b7dSInki Dae val |= WINCONx_BURSTLEN_16WORD;
7161c248b7dSInki Dae break;
7171c248b7dSInki Dae }
7181c248b7dSInki Dae
7192d684f4eSMartin Jücker switch (pixel_format) {
7202d684f4eSMartin Jücker case DRM_FORMAT_XBGR1555:
7212d684f4eSMartin Jücker case DRM_FORMAT_XBGR8888:
7222d684f4eSMartin Jücker case DRM_FORMAT_ABGR8888:
7232d684f4eSMartin Jücker case DRM_FORMAT_BGR565:
7242d684f4eSMartin Jücker writel(WIN_RGB_ORDER_REVERSE, ctx->regs + WIN_RGB_ORDER(win));
7252d684f4eSMartin Jücker break;
7262d684f4eSMartin Jücker default:
7272d684f4eSMartin Jücker writel(WIN_RGB_ORDER_FORWARD, ctx->regs + WIN_RGB_ORDER(win));
7282d684f4eSMartin Jücker break;
7292d684f4eSMartin Jücker }
7302d684f4eSMartin Jücker
73166367461SRahul Sharma /*
7328b704d8aSMarek Szyprowski * Setting dma-burst to 16Word causes permanent tearing for very small
7338b704d8aSMarek Szyprowski * buffers, e.g. cursor buffer. Burst Mode switching which based on
7348b704d8aSMarek Szyprowski * plane size is not recommended as plane size varies alot towards the
7358b704d8aSMarek Szyprowski * end of the screen and rapid movement causes unstable DMA, but it is
7368b704d8aSMarek Szyprowski * still better to change dma-burst than displaying garbage.
73766367461SRahul Sharma */
73866367461SRahul Sharma
7398b704d8aSMarek Szyprowski if (width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
74066367461SRahul Sharma val &= ~WINCONx_BURSTLEN_MASK;
74166367461SRahul Sharma val |= WINCONx_BURSTLEN_4WORD;
74266367461SRahul Sharma }
7433b5129b3SChristoph Manszewski fimd_set_bits(ctx, WINCON(win), ~WINCONx_BLEND_MODE_MASK, val);
744453b44a3SGustavo Padovan
745453b44a3SGustavo Padovan /* hardware window 0 doesn't support alpha channel. */
7463b5129b3SChristoph Manszewski if (win != 0) {
7473b5129b3SChristoph Manszewski fimd_win_set_bldmod(ctx, win, alpha, pixel_alpha);
7483b5129b3SChristoph Manszewski fimd_win_set_bldeq(ctx, win, alpha, pixel_alpha);
7493b5129b3SChristoph Manszewski }
7501c248b7dSInki Dae }
7511c248b7dSInki Dae
fimd_win_set_colkey(struct fimd_context * ctx,unsigned int win)752bb7704d6SSean Paul static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
7531c248b7dSInki Dae {
7541c248b7dSInki Dae unsigned int keycon0 = 0, keycon1 = 0;
7551c248b7dSInki Dae
7561c248b7dSInki Dae keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
7571c248b7dSInki Dae WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
7581c248b7dSInki Dae
7591c248b7dSInki Dae keycon1 = WxKEYCON1_COLVAL(0xffffffff);
7601c248b7dSInki Dae
7611c248b7dSInki Dae writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
7621c248b7dSInki Dae writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
7631c248b7dSInki Dae }
7641c248b7dSInki Dae
765de7af100STomasz Figa /**
766b80bfc59SKrzysztof Kozlowski * fimd_shadow_protect_win() - disable updating values from shadow registers at vsync
767de7af100STomasz Figa *
768cc40c475SLee Jones * @ctx: local driver data
769de7af100STomasz Figa * @win: window to protect registers for
770de7af100STomasz Figa * @protect: 1 to protect (disable updates)
771de7af100STomasz Figa */
fimd_shadow_protect_win(struct fimd_context * ctx,unsigned int win,bool protect)772de7af100STomasz Figa static void fimd_shadow_protect_win(struct fimd_context *ctx,
7736e2a3b66SGustavo Padovan unsigned int win, bool protect)
774de7af100STomasz Figa {
775de7af100STomasz Figa u32 reg, bits, val;
776de7af100STomasz Figa
777ce3ff36bSGustavo Padovan /*
778ce3ff36bSGustavo Padovan * SHADOWCON/PRTCON register is used for enabling timing.
779ce3ff36bSGustavo Padovan *
780ce3ff36bSGustavo Padovan * for example, once only width value of a register is set,
781ce3ff36bSGustavo Padovan * if the dma is started then fimd hardware could malfunction so
782ce3ff36bSGustavo Padovan * with protect window setting, the register fields with prefix '_F'
783ce3ff36bSGustavo Padovan * wouldn't be updated at vsync also but updated once unprotect window
784ce3ff36bSGustavo Padovan * is set.
785ce3ff36bSGustavo Padovan */
786ce3ff36bSGustavo Padovan
787de7af100STomasz Figa if (ctx->driver_data->has_shadowcon) {
788de7af100STomasz Figa reg = SHADOWCON;
789de7af100STomasz Figa bits = SHADOWCON_WINx_PROTECT(win);
790de7af100STomasz Figa } else {
791de7af100STomasz Figa reg = PRTCON;
792de7af100STomasz Figa bits = PRTCON_PROTECT;
793de7af100STomasz Figa }
794de7af100STomasz Figa
795de7af100STomasz Figa val = readl(ctx->regs + reg);
796de7af100STomasz Figa if (protect)
797de7af100STomasz Figa val |= bits;
798de7af100STomasz Figa else
799de7af100STomasz Figa val &= ~bits;
800de7af100STomasz Figa writel(val, ctx->regs + reg);
801de7af100STomasz Figa }
802de7af100STomasz Figa
fimd_atomic_begin(struct exynos_drm_crtc * crtc)803d29c2c14SMarek Szyprowski static void fimd_atomic_begin(struct exynos_drm_crtc *crtc)
804ce3ff36bSGustavo Padovan {
805ce3ff36bSGustavo Padovan struct fimd_context *ctx = crtc->ctx;
806d29c2c14SMarek Szyprowski int i;
807ce3ff36bSGustavo Padovan
808ce3ff36bSGustavo Padovan if (ctx->suspended)
809ce3ff36bSGustavo Padovan return;
810ce3ff36bSGustavo Padovan
811d29c2c14SMarek Szyprowski for (i = 0; i < WINDOWS_NR; i++)
812d29c2c14SMarek Szyprowski fimd_shadow_protect_win(ctx, i, true);
813ce3ff36bSGustavo Padovan }
814ce3ff36bSGustavo Padovan
fimd_atomic_flush(struct exynos_drm_crtc * crtc)815d29c2c14SMarek Szyprowski static void fimd_atomic_flush(struct exynos_drm_crtc *crtc)
816ce3ff36bSGustavo Padovan {
817ce3ff36bSGustavo Padovan struct fimd_context *ctx = crtc->ctx;
818d29c2c14SMarek Szyprowski int i;
819ce3ff36bSGustavo Padovan
820ce3ff36bSGustavo Padovan if (ctx->suspended)
821ce3ff36bSGustavo Padovan return;
822ce3ff36bSGustavo Padovan
823d29c2c14SMarek Szyprowski for (i = 0; i < WINDOWS_NR; i++)
824d29c2c14SMarek Szyprowski fimd_shadow_protect_win(ctx, i, false);
825a392276dSAndrzej Hajda
826a392276dSAndrzej Hajda exynos_crtc_handle_event(crtc);
827ce3ff36bSGustavo Padovan }
828ce3ff36bSGustavo Padovan
fimd_update_plane(struct exynos_drm_crtc * crtc,struct exynos_drm_plane * plane)8291e1d1393SGustavo Padovan static void fimd_update_plane(struct exynos_drm_crtc *crtc,
8301e1d1393SGustavo Padovan struct exynos_drm_plane *plane)
8311c248b7dSInki Dae {
8320114f404SMarek Szyprowski struct exynos_drm_plane_state *state =
8330114f404SMarek Szyprowski to_exynos_plane_state(plane->base.state);
83493bca243SGustavo Padovan struct fimd_context *ctx = crtc->ctx;
8350114f404SMarek Szyprowski struct drm_framebuffer *fb = state->base.fb;
8367ee14cdcSGustavo Padovan dma_addr_t dma_addr;
8377ee14cdcSGustavo Padovan unsigned long val, size, offset;
8387ee14cdcSGustavo Padovan unsigned int last_x, last_y, buf_offsize, line_size;
83940bdfb0aSMarek Szyprowski unsigned int win = plane->index;
840ac60944cSTobias Jakobi unsigned int cpp = fb->format->cpp[0];
8410488f50eSMarek Szyprowski unsigned int pitch = fb->pitches[0];
8421c248b7dSInki Dae
843e30d4bcfSInki Dae if (ctx->suspended)
844e30d4bcfSInki Dae return;
845e30d4bcfSInki Dae
846ac60944cSTobias Jakobi offset = state->src.x * cpp;
8470114f404SMarek Szyprowski offset += state->src.y * pitch;
8487ee14cdcSGustavo Padovan
8491c248b7dSInki Dae /* buffer start address */
8500488f50eSMarek Szyprowski dma_addr = exynos_drm_fb_dma_addr(fb, 0) + offset;
8517ee14cdcSGustavo Padovan val = (unsigned long)dma_addr;
8521c248b7dSInki Dae writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
8531c248b7dSInki Dae
8541c248b7dSInki Dae /* buffer end address */
8550114f404SMarek Szyprowski size = pitch * state->crtc.h;
8567ee14cdcSGustavo Padovan val = (unsigned long)(dma_addr + size);
8571c248b7dSInki Dae writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
8581c248b7dSInki Dae
8596be90056SInki Dae DRM_DEV_DEBUG_KMS(ctx->dev,
8606be90056SInki Dae "start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
8617ee14cdcSGustavo Padovan (unsigned long)dma_addr, val, size);
8626be90056SInki Dae DRM_DEV_DEBUG_KMS(ctx->dev, "ovl_width = %d, ovl_height = %d\n",
8630114f404SMarek Szyprowski state->crtc.w, state->crtc.h);
8641c248b7dSInki Dae
8651c248b7dSInki Dae /* buffer size */
866ac60944cSTobias Jakobi buf_offsize = pitch - (state->crtc.w * cpp);
867ac60944cSTobias Jakobi line_size = state->crtc.w * cpp;
8687ee14cdcSGustavo Padovan val = VIDW_BUF_SIZE_OFFSET(buf_offsize) |
8697ee14cdcSGustavo Padovan VIDW_BUF_SIZE_PAGEWIDTH(line_size) |
8707ee14cdcSGustavo Padovan VIDW_BUF_SIZE_OFFSET_E(buf_offsize) |
8717ee14cdcSGustavo Padovan VIDW_BUF_SIZE_PAGEWIDTH_E(line_size);
8721c248b7dSInki Dae writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
8731c248b7dSInki Dae
8741c248b7dSInki Dae /* OSD position */
8750114f404SMarek Szyprowski val = VIDOSDxA_TOPLEFT_X(state->crtc.x) |
8760114f404SMarek Szyprowski VIDOSDxA_TOPLEFT_Y(state->crtc.y) |
8770114f404SMarek Szyprowski VIDOSDxA_TOPLEFT_X_E(state->crtc.x) |
8780114f404SMarek Szyprowski VIDOSDxA_TOPLEFT_Y_E(state->crtc.y);
8791c248b7dSInki Dae writel(val, ctx->regs + VIDOSD_A(win));
8801c248b7dSInki Dae
8810114f404SMarek Szyprowski last_x = state->crtc.x + state->crtc.w;
882f56aad3aSJoonyoung Shim if (last_x)
883f56aad3aSJoonyoung Shim last_x--;
8840114f404SMarek Szyprowski last_y = state->crtc.y + state->crtc.h;
885f56aad3aSJoonyoung Shim if (last_y)
886f56aad3aSJoonyoung Shim last_y--;
887f56aad3aSJoonyoung Shim
888ca555e5aSJoonyoung Shim val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
889ca555e5aSJoonyoung Shim VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
890ca555e5aSJoonyoung Shim
8911c248b7dSInki Dae writel(val, ctx->regs + VIDOSD_B(win));
8921c248b7dSInki Dae
8936be90056SInki Dae DRM_DEV_DEBUG_KMS(ctx->dev,
8946be90056SInki Dae "osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
8950114f404SMarek Szyprowski state->crtc.x, state->crtc.y, last_x, last_y);
8961c248b7dSInki Dae
8971c248b7dSInki Dae /* OSD size */
8981c248b7dSInki Dae if (win != 3 && win != 4) {
8991c248b7dSInki Dae u32 offset = VIDOSD_D(win);
9001c248b7dSInki Dae if (win == 0)
9010f10cf14SLeela Krishna Amudala offset = VIDOSD_C(win);
9020114f404SMarek Szyprowski val = state->crtc.w * state->crtc.h;
9031c248b7dSInki Dae writel(val, ctx->regs + offset);
9041c248b7dSInki Dae
9056be90056SInki Dae DRM_DEV_DEBUG_KMS(ctx->dev, "osd size = 0x%x\n",
9066be90056SInki Dae (unsigned int)val);
9071c248b7dSInki Dae }
9081c248b7dSInki Dae
9096f8ee5c2SChristoph Manszewski fimd_win_set_pixfmt(ctx, win, fb, state->src.w);
9101c248b7dSInki Dae
9111c248b7dSInki Dae /* hardware window 0 doesn't support color key. */
9121c248b7dSInki Dae if (win != 0)
913bb7704d6SSean Paul fimd_win_set_colkey(ctx, win);
9141c248b7dSInki Dae
915f181a543SYoungJun Cho fimd_enable_video_output(ctx, win, true);
916ec05da95SInki Dae
917999d8b31SYoungJun Cho if (ctx->driver_data->has_shadowcon)
918999d8b31SYoungJun Cho fimd_enable_shadow_channel_path(ctx, win, true);
919ec05da95SInki Dae
9203854fab2SYoungJun Cho if (ctx->i80_if)
9213854fab2SYoungJun Cho atomic_set(&ctx->win_updated, 1);
9221c248b7dSInki Dae }
9231c248b7dSInki Dae
fimd_disable_plane(struct exynos_drm_crtc * crtc,struct exynos_drm_plane * plane)9241e1d1393SGustavo Padovan static void fimd_disable_plane(struct exynos_drm_crtc *crtc,
9251e1d1393SGustavo Padovan struct exynos_drm_plane *plane)
9261c248b7dSInki Dae {
92793bca243SGustavo Padovan struct fimd_context *ctx = crtc->ctx;
92840bdfb0aSMarek Szyprowski unsigned int win = plane->index;
929ec05da95SInki Dae
930c329f667SJoonyoung Shim if (ctx->suspended)
931db7e55aeSPrathyush K return;
932db7e55aeSPrathyush K
933f181a543SYoungJun Cho fimd_enable_video_output(ctx, win, false);
9341c248b7dSInki Dae
935999d8b31SYoungJun Cho if (ctx->driver_data->has_shadowcon)
936999d8b31SYoungJun Cho fimd_enable_shadow_channel_path(ctx, win, false);
937a43b933bSSean Paul }
938a43b933bSSean Paul
fimd_atomic_enable(struct exynos_drm_crtc * crtc)93911f95489SInki Dae static void fimd_atomic_enable(struct exynos_drm_crtc *crtc)
940a43b933bSSean Paul {
9413cecda03SGustavo Padovan struct fimd_context *ctx = crtc->ctx;
942a43b933bSSean Paul
943a43b933bSSean Paul if (!ctx->suspended)
9443cecda03SGustavo Padovan return;
945a43b933bSSean Paul
946a43b933bSSean Paul ctx->suspended = false;
947a43b933bSSean Paul
948445d3bedSInki Dae if (pm_runtime_resume_and_get(ctx->dev) < 0) {
949445d3bedSInki Dae dev_warn(ctx->dev, "failed to enable FIMD device.\n");
950445d3bedSInki Dae return;
951445d3bedSInki Dae }
952af65c804SSean Paul
953a43b933bSSean Paul /* if vblank was enabled status, enable it again. */
9543cecda03SGustavo Padovan if (test_and_clear_bit(0, &ctx->irq_flags))
9553cecda03SGustavo Padovan fimd_enable_vblank(ctx->crtc);
956a43b933bSSean Paul
957c329f667SJoonyoung Shim fimd_commit(ctx->crtc);
958a43b933bSSean Paul }
959a43b933bSSean Paul
fimd_atomic_disable(struct exynos_drm_crtc * crtc)96011f95489SInki Dae static void fimd_atomic_disable(struct exynos_drm_crtc *crtc)
961a43b933bSSean Paul {
9623cecda03SGustavo Padovan struct fimd_context *ctx = crtc->ctx;
963c329f667SJoonyoung Shim int i;
9643cecda03SGustavo Padovan
965a43b933bSSean Paul if (ctx->suspended)
9663cecda03SGustavo Padovan return;
967a43b933bSSean Paul
968a43b933bSSean Paul /*
969a43b933bSSean Paul * We need to make sure that all windows are disabled before we
970a43b933bSSean Paul * suspend that connector. Otherwise we might try to scan from
971a43b933bSSean Paul * a destroyed buffer later.
972a43b933bSSean Paul */
973c329f667SJoonyoung Shim for (i = 0; i < WINDOWS_NR; i++)
9741e1d1393SGustavo Padovan fimd_disable_plane(crtc, &ctx->planes[i]);
975a43b933bSSean Paul
97694ab95a9SInki Dae fimd_enable_vblank(crtc);
97794ab95a9SInki Dae fimd_wait_for_vblank(crtc);
97894ab95a9SInki Dae fimd_disable_vblank(crtc);
97994ab95a9SInki Dae
980b74f14fdSJoonyoung Shim writel(0, ctx->regs + VIDCON0);
981b74f14fdSJoonyoung Shim
982af65c804SSean Paul pm_runtime_put_sync(ctx->dev);
983a43b933bSSean Paul ctx->suspended = true;
984080be03dSSean Paul }
985080be03dSSean Paul
fimd_trigger(struct device * dev)9863854fab2SYoungJun Cho static void fimd_trigger(struct device *dev)
9873854fab2SYoungJun Cho {
988e152dbd7SAndrzej Hajda struct fimd_context *ctx = dev_get_drvdata(dev);
989e1a7b9b4SMarek Szyprowski const struct fimd_driver_data *driver_data = ctx->driver_data;
9903854fab2SYoungJun Cho void *timing_base = ctx->regs + driver_data->timing_base;
9913854fab2SYoungJun Cho u32 reg;
9923854fab2SYoungJun Cho
9939b67eb73SJoonyoung Shim /*
9941c905d95SYoungJun Cho * Skips triggering if in triggering state, because multiple triggering
9959b67eb73SJoonyoung Shim * requests can cause panel reset.
9969b67eb73SJoonyoung Shim */
9979b67eb73SJoonyoung Shim if (atomic_read(&ctx->triggering))
9989b67eb73SJoonyoung Shim return;
9999b67eb73SJoonyoung Shim
10001c905d95SYoungJun Cho /* Enters triggering mode */
10013854fab2SYoungJun Cho atomic_set(&ctx->triggering, 1);
10023854fab2SYoungJun Cho
10033854fab2SYoungJun Cho reg = readl(timing_base + TRIGCON);
1004b5bf0f1eSInki Dae reg |= (TRGMODE_ENABLE | SWTRGCMD_ENABLE);
10053854fab2SYoungJun Cho writel(reg, timing_base + TRIGCON);
100687ab85b3SYoungJun Cho
100787ab85b3SYoungJun Cho /*
100887ab85b3SYoungJun Cho * Exits triggering mode if vblank is not enabled yet, because when the
100987ab85b3SYoungJun Cho * VIDINTCON0 register is not set, it can not exit from triggering mode.
101087ab85b3SYoungJun Cho */
101187ab85b3SYoungJun Cho if (!test_bit(0, &ctx->irq_flags))
101287ab85b3SYoungJun Cho atomic_set(&ctx->triggering, 0);
10133854fab2SYoungJun Cho }
10143854fab2SYoungJun Cho
fimd_te_handler(struct exynos_drm_crtc * crtc)101593bca243SGustavo Padovan static void fimd_te_handler(struct exynos_drm_crtc *crtc)
10163854fab2SYoungJun Cho {
101793bca243SGustavo Padovan struct fimd_context *ctx = crtc->ctx;
1018a6f75aa1SInki Dae u32 trg_type = ctx->driver_data->trg_type;
10193854fab2SYoungJun Cho
10203854fab2SYoungJun Cho /* Checks the crtc is detached already from encoder */
10212949390eSAndrzej Hajda if (!ctx->drm_dev)
10223854fab2SYoungJun Cho return;
10233854fab2SYoungJun Cho
1024a6f75aa1SInki Dae if (trg_type == I80_HW_TRG)
1025a6f75aa1SInki Dae goto out;
1026a6f75aa1SInki Dae
10273854fab2SYoungJun Cho /*
10283854fab2SYoungJun Cho * If there is a page flip request, triggers and handles the page flip
10293854fab2SYoungJun Cho * event so that current fb can be updated into panel GRAM.
10303854fab2SYoungJun Cho */
10313854fab2SYoungJun Cho if (atomic_add_unless(&ctx->win_updated, -1, 0))
10323854fab2SYoungJun Cho fimd_trigger(ctx->dev);
10333854fab2SYoungJun Cho
1034a6f75aa1SInki Dae out:
10353854fab2SYoungJun Cho /* Wakes up vsync event queue */
10363854fab2SYoungJun Cho if (atomic_read(&ctx->wait_vsync_event)) {
10373854fab2SYoungJun Cho atomic_set(&ctx->wait_vsync_event, 0);
10383854fab2SYoungJun Cho wake_up(&ctx->wait_vsync_queue);
1039b301ae24SYoungJun Cho }
10403854fab2SYoungJun Cho
1041adf67abfSJoonyoung Shim if (test_bit(0, &ctx->irq_flags))
1042eafd540aSGustavo Padovan drm_crtc_handle_vblank(&ctx->crtc->base);
10433854fab2SYoungJun Cho }
10443854fab2SYoungJun Cho
fimd_dp_clock_enable(struct exynos_drm_clk * clk,bool enable)1045196e059aSAndrzej Hajda static void fimd_dp_clock_enable(struct exynos_drm_clk *clk, bool enable)
104648107d7bSKrzysztof Kozlowski {
1047196e059aSAndrzej Hajda struct fimd_context *ctx = container_of(clk, struct fimd_context,
1048196e059aSAndrzej Hajda dp_clk);
1049196e059aSAndrzej Hajda u32 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
10503c79fb8cSGustavo Padovan writel(val, ctx->regs + DP_MIE_CLKCON);
105148107d7bSKrzysztof Kozlowski }
105248107d7bSKrzysztof Kozlowski
1053f3aaf762SKrzysztof Kozlowski static const struct exynos_drm_crtc_ops fimd_crtc_ops = {
105411f95489SInki Dae .atomic_enable = fimd_atomic_enable,
105511f95489SInki Dae .atomic_disable = fimd_atomic_disable,
10561c6244c3SSean Paul .enable_vblank = fimd_enable_vblank,
10571c6244c3SSean Paul .disable_vblank = fimd_disable_vblank,
1058ce3ff36bSGustavo Padovan .atomic_begin = fimd_atomic_begin,
10599cc7610aSGustavo Padovan .update_plane = fimd_update_plane,
10609cc7610aSGustavo Padovan .disable_plane = fimd_disable_plane,
1061ce3ff36bSGustavo Padovan .atomic_flush = fimd_atomic_flush,
1062c96fdfdeSAndrzej Hajda .atomic_check = fimd_atomic_check,
10633854fab2SYoungJun Cho .te_handler = fimd_te_handler,
10641c248b7dSInki Dae };
10651c248b7dSInki Dae
fimd_irq_handler(int irq,void * dev_id)10661c248b7dSInki Dae static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
10671c248b7dSInki Dae {
10681c248b7dSInki Dae struct fimd_context *ctx = (struct fimd_context *)dev_id;
10699276dff7SAndrzej Hajda u32 val, clear_bit;
10701c248b7dSInki Dae
10711c248b7dSInki Dae val = readl(ctx->regs + VIDINTCON1);
10721c248b7dSInki Dae
10733854fab2SYoungJun Cho clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
10743854fab2SYoungJun Cho if (val & clear_bit)
10753854fab2SYoungJun Cho writel(clear_bit, ctx->regs + VIDINTCON1);
10761c248b7dSInki Dae
1077ec05da95SInki Dae /* check the crtc is detached already from encoder */
10782949390eSAndrzej Hajda if (!ctx->drm_dev)
1079ec05da95SInki Dae goto out;
1080483b88f8SInki Dae
1081fc75f710SGustavo Padovan if (!ctx->i80_if)
1082fc75f710SGustavo Padovan drm_crtc_handle_vblank(&ctx->crtc->base);
1083fc75f710SGustavo Padovan
1084fc75f710SGustavo Padovan if (ctx->i80_if) {
10851c905d95SYoungJun Cho /* Exits triggering mode */
10863854fab2SYoungJun Cho atomic_set(&ctx->triggering, 0);
10873854fab2SYoungJun Cho } else {
108801ce113cSPrathyush K /* set wait vsync event to zero and wake up queue. */
108901ce113cSPrathyush K if (atomic_read(&ctx->wait_vsync_event)) {
109001ce113cSPrathyush K atomic_set(&ctx->wait_vsync_event, 0);
10918dd9ad5dSSeung-Woo Kim wake_up(&ctx->wait_vsync_queue);
109201ce113cSPrathyush K }
10933854fab2SYoungJun Cho }
10943854fab2SYoungJun Cho
1095ec05da95SInki Dae out:
10961c248b7dSInki Dae return IRQ_HANDLED;
10971c248b7dSInki Dae }
10981c248b7dSInki Dae
fimd_bind(struct device * dev,struct device * master,void * data)1099f37cd5e8SInki Dae static int fimd_bind(struct device *dev, struct device *master, void *data)
1100562ad9f4SAndrzej Hajda {
1101e152dbd7SAndrzej Hajda struct fimd_context *ctx = dev_get_drvdata(dev);
1102f37cd5e8SInki Dae struct drm_device *drm_dev = data;
11037ee14cdcSGustavo Padovan struct exynos_drm_plane *exynos_plane;
1104fd2d2fc2SMarek Szyprowski unsigned int i;
11056e2a3b66SGustavo Padovan int ret;
1106000cc920SAndrzej Hajda
1107cdbfca89SHyungwon Hwang ctx->drm_dev = drm_dev;
1108efa75bcdSAjay Kumar
1109fd2d2fc2SMarek Szyprowski for (i = 0; i < WINDOWS_NR; i++) {
11102d684f4eSMartin Jücker if (ctx->driver_data->has_bgr_support) {
11112d684f4eSMartin Jücker ctx->configs[i].pixel_formats = fimd_extended_formats;
11122d684f4eSMartin Jücker ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_extended_formats);
11132d684f4eSMartin Jücker } else {
1114fd2d2fc2SMarek Szyprowski ctx->configs[i].pixel_formats = fimd_formats;
1115fd2d2fc2SMarek Szyprowski ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats);
11162d684f4eSMartin Jücker }
11172d684f4eSMartin Jücker
1118fd2d2fc2SMarek Szyprowski ctx->configs[i].zpos = i;
1119fd2d2fc2SMarek Szyprowski ctx->configs[i].type = fimd_win_types[i];
11206f8ee5c2SChristoph Manszewski ctx->configs[i].capabilities = capabilities[i];
112140bdfb0aSMarek Szyprowski ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
11222c82607bSAndrzej Hajda &ctx->configs[i]);
11237ee14cdcSGustavo Padovan if (ret)
11247ee14cdcSGustavo Padovan return ret;
11257ee14cdcSGustavo Padovan }
11267ee14cdcSGustavo Padovan
11275d3d0995SGustavo Padovan exynos_plane = &ctx->planes[DEFAULT_WIN];
11287ee14cdcSGustavo Padovan ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
1129d644951cSAndrzej Hajda EXYNOS_DISPLAY_TYPE_LCD, &fimd_crtc_ops, ctx);
1130d1222842SHyungwon Hwang if (IS_ERR(ctx->crtc))
1131d1222842SHyungwon Hwang return PTR_ERR(ctx->crtc);
113293bca243SGustavo Padovan
1133196e059aSAndrzej Hajda if (ctx->driver_data->has_dp_clk) {
1134196e059aSAndrzej Hajda ctx->dp_clk.enable = fimd_dp_clock_enable;
1135196e059aSAndrzej Hajda ctx->crtc->pipe_clk = &ctx->dp_clk;
1136196e059aSAndrzej Hajda }
1137196e059aSAndrzej Hajda
1138cf67cc9aSGustavo Padovan if (ctx->encoder)
1139a2986e80SGustavo Padovan exynos_dpi_bind(drm_dev, ctx->encoder);
1140000cc920SAndrzej Hajda
1141445d3bedSInki Dae if (is_drm_iommu_supported(drm_dev)) {
1142445d3bedSInki Dae int ret;
1143445d3bedSInki Dae
1144445d3bedSInki Dae ret = fimd_clear_channels(ctx->crtc);
1145445d3bedSInki Dae if (ret < 0)
1146445d3bedSInki Dae return ret;
1147445d3bedSInki Dae }
1148eb7a3fc7SJoonyoung Shim
114907dc3678SMarek Szyprowski return exynos_drm_register_dma(drm_dev, dev, &ctx->dma_priv);
1150000cc920SAndrzej Hajda }
1151000cc920SAndrzej Hajda
fimd_unbind(struct device * dev,struct device * master,void * data)1152000cc920SAndrzej Hajda static void fimd_unbind(struct device *dev, struct device *master,
1153000cc920SAndrzej Hajda void *data)
1154000cc920SAndrzej Hajda {
1155e152dbd7SAndrzej Hajda struct fimd_context *ctx = dev_get_drvdata(dev);
1156000cc920SAndrzej Hajda
115711f95489SInki Dae fimd_atomic_disable(ctx->crtc);
1158000cc920SAndrzej Hajda
115907dc3678SMarek Szyprowski exynos_drm_unregister_dma(ctx->drm_dev, ctx->dev, &ctx->dma_priv);
1160cdbfca89SHyungwon Hwang
1161cf67cc9aSGustavo Padovan if (ctx->encoder)
1162cf67cc9aSGustavo Padovan exynos_dpi_remove(ctx->encoder);
1163000cc920SAndrzej Hajda }
1164000cc920SAndrzej Hajda
1165000cc920SAndrzej Hajda static const struct component_ops fimd_component_ops = {
1166000cc920SAndrzej Hajda .bind = fimd_bind,
1167000cc920SAndrzej Hajda .unbind = fimd_unbind,
1168000cc920SAndrzej Hajda };
1169000cc920SAndrzej Hajda
fimd_probe(struct platform_device * pdev)1170000cc920SAndrzej Hajda static int fimd_probe(struct platform_device *pdev)
1171000cc920SAndrzej Hajda {
1172000cc920SAndrzej Hajda struct device *dev = &pdev->dev;
1173000cc920SAndrzej Hajda struct fimd_context *ctx;
11743854fab2SYoungJun Cho struct device_node *i80_if_timings;
1175fe42cfb4SGustavo Padovan int ret;
1176562ad9f4SAndrzej Hajda
1177e152dbd7SAndrzej Hajda if (!dev->of_node)
1178e152dbd7SAndrzej Hajda return -ENODEV;
11792d3f173cSSachin Kamat
1180d873ab99SSeung-Woo Kim ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1181e152dbd7SAndrzej Hajda if (!ctx)
1182e152dbd7SAndrzej Hajda return -ENOMEM;
1183e152dbd7SAndrzej Hajda
1184bb7704d6SSean Paul ctx->dev = dev;
1185a43b933bSSean Paul ctx->suspended = true;
1186e1a7b9b4SMarek Szyprowski ctx->driver_data = of_device_get_match_data(dev);
1187bb7704d6SSean Paul
11881417f109SSean Paul if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
11891417f109SSean Paul ctx->vidcon1 |= VIDCON1_INV_VDEN;
11901417f109SSean Paul if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
11911417f109SSean Paul ctx->vidcon1 |= VIDCON1_INV_VCLK;
1192562ad9f4SAndrzej Hajda
11933854fab2SYoungJun Cho i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
11943854fab2SYoungJun Cho if (i80_if_timings) {
11953854fab2SYoungJun Cho u32 val;
11963854fab2SYoungJun Cho
11973854fab2SYoungJun Cho ctx->i80_if = true;
11983854fab2SYoungJun Cho
11993854fab2SYoungJun Cho if (ctx->driver_data->has_vidoutcon)
12003854fab2SYoungJun Cho ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
12013854fab2SYoungJun Cho else
12023854fab2SYoungJun Cho ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
12033854fab2SYoungJun Cho /*
12043854fab2SYoungJun Cho * The user manual describes that this "DSI_EN" bit is required
12053854fab2SYoungJun Cho * to enable I80 24-bit data interface.
12063854fab2SYoungJun Cho */
12073854fab2SYoungJun Cho ctx->vidcon0 |= VIDCON0_DSI_EN;
12083854fab2SYoungJun Cho
12093854fab2SYoungJun Cho if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
12103854fab2SYoungJun Cho val = 0;
12113854fab2SYoungJun Cho ctx->i80ifcon = LCD_CS_SETUP(val);
12123854fab2SYoungJun Cho if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
12133854fab2SYoungJun Cho val = 0;
12143854fab2SYoungJun Cho ctx->i80ifcon |= LCD_WR_SETUP(val);
12153854fab2SYoungJun Cho if (of_property_read_u32(i80_if_timings, "wr-active", &val))
12163854fab2SYoungJun Cho val = 1;
12173854fab2SYoungJun Cho ctx->i80ifcon |= LCD_WR_ACTIVE(val);
12183854fab2SYoungJun Cho if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
12193854fab2SYoungJun Cho val = 0;
12203854fab2SYoungJun Cho ctx->i80ifcon |= LCD_WR_HOLD(val);
12213854fab2SYoungJun Cho }
12223854fab2SYoungJun Cho of_node_put(i80_if_timings);
12233854fab2SYoungJun Cho
12243854fab2SYoungJun Cho ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
12253854fab2SYoungJun Cho "samsung,sysreg");
12263854fab2SYoungJun Cho if (IS_ERR(ctx->sysreg)) {
12273854fab2SYoungJun Cho dev_warn(dev, "failed to get system register.\n");
12283854fab2SYoungJun Cho ctx->sysreg = NULL;
12293854fab2SYoungJun Cho }
12303854fab2SYoungJun Cho
1231a968e727SSean Paul ctx->bus_clk = devm_clk_get(dev, "fimd");
1232a968e727SSean Paul if (IS_ERR(ctx->bus_clk)) {
1233a968e727SSean Paul dev_err(dev, "failed to get bus clock\n");
123486650408SAndrzej Hajda return PTR_ERR(ctx->bus_clk);
1235a968e727SSean Paul }
1236a968e727SSean Paul
1237a968e727SSean Paul ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1238a968e727SSean Paul if (IS_ERR(ctx->lcd_clk)) {
1239a968e727SSean Paul dev_err(dev, "failed to get lcd clock\n");
124086650408SAndrzej Hajda return PTR_ERR(ctx->lcd_clk);
1241a968e727SSean Paul }
12421c248b7dSInki Dae
124317ac76e0SCai Huoqing ctx->regs = devm_platform_ioremap_resource(pdev, 0);
124486650408SAndrzej Hajda if (IS_ERR(ctx->regs))
124586650408SAndrzej Hajda return PTR_ERR(ctx->regs);
12461c248b7dSInki Dae
12479df3f43aSLad Prabhakar ret = platform_get_irq_byname(pdev, ctx->i80_if ? "lcd_sys" : "vsync");
12489df3f43aSLad Prabhakar if (ret < 0)
12499df3f43aSLad Prabhakar return ret;
12501c248b7dSInki Dae
12519df3f43aSLad Prabhakar ret = devm_request_irq(dev, ret, fimd_irq_handler, 0, "drm_fimd", ctx);
1252edc57266SSachin Kamat if (ret) {
12531c248b7dSInki Dae dev_err(dev, "irq request failed.\n");
125486650408SAndrzej Hajda return ret;
12551c248b7dSInki Dae }
12561c248b7dSInki Dae
125757ed0f7bSDaniel Vetter init_waitqueue_head(&ctx->wait_vsync_queue);
125801ce113cSPrathyush K atomic_set(&ctx->wait_vsync_event, 0);
12591c248b7dSInki Dae
1260e152dbd7SAndrzej Hajda platform_set_drvdata(pdev, ctx);
1261080be03dSSean Paul
1262cf67cc9aSGustavo Padovan ctx->encoder = exynos_dpi_probe(dev);
1263cf67cc9aSGustavo Padovan if (IS_ERR(ctx->encoder))
1264cf67cc9aSGustavo Padovan return PTR_ERR(ctx->encoder);
1265f37cd5e8SInki Dae
1266e152dbd7SAndrzej Hajda pm_runtime_enable(dev);
1267f37cd5e8SInki Dae
1268e152dbd7SAndrzej Hajda ret = component_add(dev, &fimd_component_ops);
1269df5225bcSInki Dae if (ret)
1270df5225bcSInki Dae goto err_disable_pm_runtime;
1271df5225bcSInki Dae
1272df5225bcSInki Dae return ret;
1273df5225bcSInki Dae
1274df5225bcSInki Dae err_disable_pm_runtime:
1275e152dbd7SAndrzej Hajda pm_runtime_disable(dev);
1276df5225bcSInki Dae
1277df5225bcSInki Dae return ret;
1278f37cd5e8SInki Dae }
1279f37cd5e8SInki Dae
fimd_remove(struct platform_device * pdev)1280f37cd5e8SInki Dae static int fimd_remove(struct platform_device *pdev)
1281f37cd5e8SInki Dae {
1282af65c804SSean Paul pm_runtime_disable(&pdev->dev);
1283cb91f6a0SJoonyoung Shim
1284df5225bcSInki Dae component_del(&pdev->dev, &fimd_component_ops);
1285df5225bcSInki Dae
12861c248b7dSInki Dae return 0;
12871c248b7dSInki Dae }
12881c248b7dSInki Dae
exynos_fimd_suspend(struct device * dev)128941571976SGustavo Padovan static int exynos_fimd_suspend(struct device *dev)
129041571976SGustavo Padovan {
129141571976SGustavo Padovan struct fimd_context *ctx = dev_get_drvdata(dev);
129241571976SGustavo Padovan
129341571976SGustavo Padovan clk_disable_unprepare(ctx->lcd_clk);
129441571976SGustavo Padovan clk_disable_unprepare(ctx->bus_clk);
129541571976SGustavo Padovan
129641571976SGustavo Padovan return 0;
129741571976SGustavo Padovan }
129841571976SGustavo Padovan
exynos_fimd_resume(struct device * dev)129941571976SGustavo Padovan static int exynos_fimd_resume(struct device *dev)
130041571976SGustavo Padovan {
130141571976SGustavo Padovan struct fimd_context *ctx = dev_get_drvdata(dev);
130241571976SGustavo Padovan int ret;
130341571976SGustavo Padovan
130441571976SGustavo Padovan ret = clk_prepare_enable(ctx->bus_clk);
130541571976SGustavo Padovan if (ret < 0) {
13066f83d208SInki Dae DRM_DEV_ERROR(dev,
13076f83d208SInki Dae "Failed to prepare_enable the bus clk [%d]\n",
13086f83d208SInki Dae ret);
130941571976SGustavo Padovan return ret;
131041571976SGustavo Padovan }
131141571976SGustavo Padovan
131241571976SGustavo Padovan ret = clk_prepare_enable(ctx->lcd_clk);
131341571976SGustavo Padovan if (ret < 0) {
13146f83d208SInki Dae DRM_DEV_ERROR(dev,
13156f83d208SInki Dae "Failed to prepare_enable the lcd clk [%d]\n",
13166f83d208SInki Dae ret);
131741571976SGustavo Padovan return ret;
131841571976SGustavo Padovan }
131941571976SGustavo Padovan
132041571976SGustavo Padovan return 0;
132141571976SGustavo Padovan }
132241571976SGustavo Padovan
13231d9e6664SPaul Cercueil static DEFINE_RUNTIME_DEV_PM_OPS(exynos_fimd_pm_ops, exynos_fimd_suspend,
13241d9e6664SPaul Cercueil exynos_fimd_resume, NULL);
132541571976SGustavo Padovan
1326132a5b91SJoonyoung Shim struct platform_driver fimd_driver = {
13271c248b7dSInki Dae .probe = fimd_probe,
132856550d94SGreg Kroah-Hartman .remove = fimd_remove,
13291c248b7dSInki Dae .driver = {
13301c248b7dSInki Dae .name = "exynos4-fb",
13311c248b7dSInki Dae .owner = THIS_MODULE,
13321d9e6664SPaul Cercueil .pm = pm_ptr(&exynos_fimd_pm_ops),
13332d3f173cSSachin Kamat .of_match_table = fimd_driver_dt_match,
13341c248b7dSInki Dae },
13351c248b7dSInki Dae };
1336