14e268fedSTony Huang // SPDX-License-Identifier: GPL-2.0-only
24e268fedSTony Huang /*
34e268fedSTony Huang * Copyright (c) Sunplus Inc.
44e268fedSTony Huang * Author: Tony Huang <tonyhuang.sunplus@gmail.com>
54e268fedSTony Huang * Author: Li-hao Kuo <lhjeff911@gmail.com>
64e268fedSTony Huang */
74e268fedSTony Huang
84e268fedSTony Huang #include <linux/bitfield.h>
94e268fedSTony Huang #include <linux/clk.h>
104e268fedSTony Huang #include <linux/delay.h>
114e268fedSTony Huang #include <linux/dma-mapping.h>
124e268fedSTony Huang #include <linux/interrupt.h>
134e268fedSTony Huang #include <linux/iopoll.h>
144e268fedSTony Huang #include <linux/mmc/core.h>
154e268fedSTony Huang #include <linux/mmc/host.h>
164e268fedSTony Huang #include <linux/mmc/mmc.h>
174e268fedSTony Huang #include <linux/mmc/sdio.h>
184e268fedSTony Huang #include <linux/mmc/slot-gpio.h>
194e268fedSTony Huang #include <linux/module.h>
204e268fedSTony Huang #include <linux/of.h>
214e268fedSTony Huang #include <linux/platform_device.h>
224e268fedSTony Huang #include <linux/pm.h>
234e268fedSTony Huang #include <linux/pm_runtime.h>
244e268fedSTony Huang #include <linux/reset.h>
254e268fedSTony Huang
264e268fedSTony Huang #define SPMMC_MIN_CLK 400000
274e268fedSTony Huang #define SPMMC_MAX_CLK 52000000
284e268fedSTony Huang #define SPMMC_MAX_BLK_COUNT 65536
294e268fedSTony Huang #define SPMMC_MAX_TUNABLE_DLY 7
304e268fedSTony Huang #define SPMMC_TIMEOUT_US 500000
314e268fedSTony Huang #define SPMMC_POLL_DELAY_US 10
324e268fedSTony Huang
334e268fedSTony Huang #define SPMMC_CARD_MEDIATYPE_SRCDST_REG 0x0000
344e268fedSTony Huang #define SPMMC_MEDIA_TYPE GENMASK(2, 0)
354e268fedSTony Huang #define SPMMC_DMA_SOURCE GENMASK(6, 4)
364e268fedSTony Huang #define SPMMC_DMA_DESTINATION GENMASK(10, 8)
374e268fedSTony Huang #define SPMMC_MEDIA_NONE 0
384e268fedSTony Huang #define SPMMC_MEDIA_SD 6
394e268fedSTony Huang #define SPMMC_MEDIA_MS 7
404e268fedSTony Huang
414e268fedSTony Huang #define SPMMC_SDRAM_SECTOR_0_SIZE_REG 0x0008
424e268fedSTony Huang #define SPMMC_DMA_BASE_ADDR_REG 0x000C
434e268fedSTony Huang #define SPMMC_HW_DMA_CTRL_REG 0x0010
444e268fedSTony Huang #define SPMMC_HW_DMA_RST BIT(9)
454e268fedSTony Huang #define SPMMC_DMAIDLE BIT(10)
464e268fedSTony Huang
474e268fedSTony Huang #define SPMMC_MAX_DMA_MEMORY_SECTORS 8
484e268fedSTony Huang
494e268fedSTony Huang #define SPMMC_SDRAM_SECTOR_1_ADDR_REG 0x0018
504e268fedSTony Huang #define SPMMC_SDRAM_SECTOR_1_LENG_REG 0x001C
514e268fedSTony Huang #define SPMMC_SDRAM_SECTOR_2_ADDR_REG 0x0020
524e268fedSTony Huang #define SPMMC_SDRAM_SECTOR_2_LENG_REG 0x0024
534e268fedSTony Huang #define SPMMC_SDRAM_SECTOR_3_ADDR_REG 0x0028
544e268fedSTony Huang #define SPMMC_SDRAM_SECTOR_3_LENG_REG 0x002C
554e268fedSTony Huang #define SPMMC_SDRAM_SECTOR_4_ADDR_REG 0x0030
564e268fedSTony Huang #define SPMMC_SDRAM_SECTOR_4_LENG_REG 0x0034
574e268fedSTony Huang #define SPMMC_SDRAM_SECTOR_5_ADDR_REG 0x0038
584e268fedSTony Huang #define SPMMC_SDRAM_SECTOR_5_LENG_REG 0x003C
594e268fedSTony Huang #define SPMMC_SDRAM_SECTOR_6_ADDR_REG 0x0040
604e268fedSTony Huang #define SPMMC_SDRAM_SECTOR_6_LENG_REG 0x0044
614e268fedSTony Huang #define SPMMC_SDRAM_SECTOR_7_ADDR_REG 0x0048
624e268fedSTony Huang #define SPMMC_SDRAM_SECTOR_7_LENG_REG 0x004C
634e268fedSTony Huang
644e268fedSTony Huang #define SPMMC_SD_INT_REG 0x0088
654e268fedSTony Huang #define SPMMC_SDINT_SDCMPEN BIT(0)
664e268fedSTony Huang #define SPMMC_SDINT_SDCMP BIT(1)
674e268fedSTony Huang #define SPMMC_SDINT_SDCMPCLR BIT(2)
684e268fedSTony Huang #define SPMMC_SDINT_SDIOEN BIT(3)
694e268fedSTony Huang #define SPMMC_SDINT_SDIO BIT(4)
704e268fedSTony Huang #define SPMMC_SDINT_SDIOCLR BIT(5)
714e268fedSTony Huang
724e268fedSTony Huang #define SPMMC_SD_PAGE_NUM_REG 0x008C
734e268fedSTony Huang
744e268fedSTony Huang #define SPMMC_SD_CONFIG0_REG 0x0090
754e268fedSTony Huang #define SPMMC_SD_PIO_MODE BIT(0)
764e268fedSTony Huang #define SPMMC_SD_DDR_MODE BIT(1)
774e268fedSTony Huang #define SPMMC_SD_LEN_MODE BIT(2)
784e268fedSTony Huang #define SPMMC_SD_TRANS_MODE GENMASK(5, 4)
794e268fedSTony Huang #define SPMMC_SD_AUTO_RESPONSE BIT(6)
804e268fedSTony Huang #define SPMMC_SD_CMD_DUMMY BIT(7)
814e268fedSTony Huang #define SPMMC_SD_RSP_CHK_EN BIT(8)
824e268fedSTony Huang #define SPMMC_SDIO_MODE BIT(9)
834e268fedSTony Huang #define SPMMC_SD_MMC_MODE BIT(10)
844e268fedSTony Huang #define SPMMC_SD_DATA_WD BIT(11)
854e268fedSTony Huang #define SPMMC_RX4_EN BIT(14)
864e268fedSTony Huang #define SPMMC_SD_RSP_TYPE BIT(15)
874e268fedSTony Huang #define SPMMC_MMC8_EN BIT(18)
884e268fedSTony Huang #define SPMMC_CLOCK_DIVISION GENMASK(31, 20)
894e268fedSTony Huang
904e268fedSTony Huang #define SPMMC_SDIO_CTRL_REG 0x0094
914e268fedSTony Huang #define SPMMC_INT_MULTI_TRIG BIT(6)
924e268fedSTony Huang
934e268fedSTony Huang #define SPMMC_SD_RST_REG 0x0098
944e268fedSTony Huang #define SPMMC_SD_CTRL_REG 0x009C
954e268fedSTony Huang #define SPMMC_NEW_COMMAND_TRIGGER BIT(0)
964e268fedSTony Huang #define SPMMC_DUMMY_CLOCK_TRIGGER BIT(1)
974e268fedSTony Huang
984e268fedSTony Huang #define SPMMC_SD_STATUS_REG 0x00A0
994e268fedSTony Huang #define SPMMC_SDSTATUS_DUMMY_READY BIT(0)
1004e268fedSTony Huang #define SPMMC_SDSTATUS_RSP_BUF_FULL BIT(1)
1014e268fedSTony Huang #define SPMMC_SDSTATUS_TX_DATA_BUF_EMPTY BIT(2)
1024e268fedSTony Huang #define SPMMC_SDSTATUS_RX_DATA_BUF_FULL BIT(3)
1034e268fedSTony Huang #define SPMMC_SDSTATUS_CMD_PIN_STATUS BIT(4)
1044e268fedSTony Huang #define SPMMC_SDSTATUS_DAT0_PIN_STATUS BIT(5)
1054e268fedSTony Huang #define SPMMC_SDSTATUS_RSP_TIMEOUT BIT(6)
1064e268fedSTony Huang #define SPMMC_SDSTATUS_CARD_CRC_CHECK_TIMEOUT BIT(7)
1074e268fedSTony Huang #define SPMMC_SDSTATUS_STB_TIMEOUT BIT(8)
1084e268fedSTony Huang #define SPMMC_SDSTATUS_RSP_CRC7_ERROR BIT(9)
1094e268fedSTony Huang #define SPMMC_SDSTATUS_CRC_TOKEN_CHECK_ERROR BIT(10)
1104e268fedSTony Huang #define SPMMC_SDSTATUS_RDATA_CRC16_ERROR BIT(11)
1114e268fedSTony Huang #define SPMMC_SDSTATUS_SUSPEND_STATE_READY BIT(12)
1124e268fedSTony Huang #define SPMMC_SDSTATUS_BUSY_CYCLE BIT(13)
1134e268fedSTony Huang #define SPMMC_SDSTATUS_DAT1_PIN_STATUS BIT(14)
1144e268fedSTony Huang #define SPMMC_SDSTATUS_SD_SENSE_STATUS BIT(15)
1154e268fedSTony Huang #define SPMMC_SDSTATUS_BOOT_ACK_TIMEOUT BIT(16)
1164e268fedSTony Huang #define SPMMC_SDSTATUS_BOOT_DATA_TIMEOUT BIT(17)
1174e268fedSTony Huang #define SPMMC_SDSTATUS_BOOT_ACK_ERROR BIT(18)
1184e268fedSTony Huang
1194e268fedSTony Huang #define SPMMC_SD_STATE_REG 0x00A4
1204e268fedSTony Huang #define SPMMC_CRCTOKEN_CHECK_RESULT GENMASK(6, 4)
1214e268fedSTony Huang #define SPMMC_SDSTATE_ERROR BIT(13)
1224e268fedSTony Huang #define SPMMC_SDSTATE_FINISH BIT(14)
1234e268fedSTony Huang
1244e268fedSTony Huang #define SPMMC_SD_HW_STATE_REG 0x00A8
1254e268fedSTony Huang #define SPMMC_SD_BLOCKSIZE_REG 0x00AC
1264e268fedSTony Huang
1274e268fedSTony Huang #define SPMMC_SD_CONFIG1_REG 0x00B0
1284e268fedSTony Huang #define SPMMC_TX_DUMMY_NUM GENMASK(8, 0)
1294e268fedSTony Huang #define SPMMC_SD_HIGH_SPEED_EN BIT(31)
1304e268fedSTony Huang
1314e268fedSTony Huang #define SPMMC_SD_TIMING_CONFIG0_REG 0x00B4
1324e268fedSTony Huang #define SPMMC_SD_CLOCK_DELAY GENMASK(2, 0)
1334e268fedSTony Huang #define SPMMC_SD_WRITE_DATA_DELAY GENMASK(6, 4)
1344e268fedSTony Huang #define SPMMC_SD_WRITE_COMMAND_DELAY GENMASK(10, 8)
1354e268fedSTony Huang #define SPMMC_SD_READ_RESPONSE_DELAY GENMASK(14, 12)
1364e268fedSTony Huang #define SPMMC_SD_READ_DATA_DELAY GENMASK(18, 16)
1374e268fedSTony Huang #define SPMMC_SD_READ_CRC_DELAY GENMASK(22, 20)
1384e268fedSTony Huang
1394e268fedSTony Huang #define SPMMC_SD_PIODATATX_REG 0x00BC
1404e268fedSTony Huang #define SPMMC_SD_PIODATARX_REG 0x00C0
1414e268fedSTony Huang #define SPMMC_SD_CMDBUF0_3_REG 0x00C4
1424e268fedSTony Huang #define SPMMC_SD_CMDBUF4_REG 0x00C8
1434e268fedSTony Huang #define SPMMC_SD_RSPBUF0_3_REG 0x00CC
1444e268fedSTony Huang #define SPMMC_SD_RSPBUF4_5_REG 0x00D0
1454e268fedSTony Huang
1464e268fedSTony Huang #define SPMMC_MAX_RETRIES (8 * 8)
1474e268fedSTony Huang
1484e268fedSTony Huang struct spmmc_tuning_info {
1494e268fedSTony Huang int enable_tuning;
1504e268fedSTony Huang int need_tuning;
1514e268fedSTony Huang int retried; /* how many times has been retried */
1524e268fedSTony Huang u32 rd_crc_dly:3;
1534e268fedSTony Huang u32 rd_dat_dly:3;
1544e268fedSTony Huang u32 rd_rsp_dly:3;
1554e268fedSTony Huang u32 wr_cmd_dly:3;
1564e268fedSTony Huang u32 wr_dat_dly:3;
1574e268fedSTony Huang u32 clk_dly:3;
1584e268fedSTony Huang };
1594e268fedSTony Huang
1604e268fedSTony Huang #define SPMMC_DMA_MODE 0
1614e268fedSTony Huang #define SPMMC_PIO_MODE 1
1624e268fedSTony Huang
1634e268fedSTony Huang struct spmmc_host {
1644e268fedSTony Huang void __iomem *base;
1654e268fedSTony Huang struct clk *clk;
1664e268fedSTony Huang struct reset_control *rstc;
1674e268fedSTony Huang struct mmc_host *mmc;
1684e268fedSTony Huang struct mmc_request *mrq; /* current mrq */
1694e268fedSTony Huang int irq;
1704e268fedSTony Huang int dmapio_mode;
1714e268fedSTony Huang struct spmmc_tuning_info tuning_info;
1724e268fedSTony Huang int dma_int_threshold;
1734e268fedSTony Huang int dma_use_int;
1744e268fedSTony Huang };
1754e268fedSTony Huang
spmmc_wait_finish(struct spmmc_host * host)1764e268fedSTony Huang static inline int spmmc_wait_finish(struct spmmc_host *host)
1774e268fedSTony Huang {
1784e268fedSTony Huang u32 state;
1794e268fedSTony Huang
1804e268fedSTony Huang return readl_poll_timeout(host->base + SPMMC_SD_STATE_REG, state,
1814e268fedSTony Huang (state & SPMMC_SDSTATE_FINISH),
1824e268fedSTony Huang SPMMC_POLL_DELAY_US, SPMMC_TIMEOUT_US);
1834e268fedSTony Huang }
1844e268fedSTony Huang
spmmc_wait_sdstatus(struct spmmc_host * host,unsigned int status_bit)1854e268fedSTony Huang static inline int spmmc_wait_sdstatus(struct spmmc_host *host, unsigned int status_bit)
1864e268fedSTony Huang {
1874e268fedSTony Huang u32 status;
1884e268fedSTony Huang
1894e268fedSTony Huang return readl_poll_timeout(host->base + SPMMC_SD_STATUS_REG, status,
1904e268fedSTony Huang (status & status_bit),
1914e268fedSTony Huang SPMMC_POLL_DELAY_US, SPMMC_TIMEOUT_US);
1924e268fedSTony Huang }
1934e268fedSTony Huang
1944e268fedSTony Huang #define spmmc_wait_rspbuf_full(host) spmmc_wait_sdstatus(host, SPMMC_SDSTATUS_RSP_BUF_FULL)
1954e268fedSTony Huang #define spmmc_wait_rxbuf_full(host) spmmc_wait_sdstatus(host, SPMMC_SDSTATUS_RX_DATA_BUF_FULL)
1964e268fedSTony Huang #define spmmc_wait_txbuf_empty(host) spmmc_wait_sdstatus(host, SPMMC_SDSTATUS_TX_DATA_BUF_EMPTY)
1974e268fedSTony Huang
spmmc_get_rsp(struct spmmc_host * host,struct mmc_command * cmd)1984e268fedSTony Huang static void spmmc_get_rsp(struct spmmc_host *host, struct mmc_command *cmd)
1994e268fedSTony Huang {
2004e268fedSTony Huang u32 value0_3, value4_5;
2014e268fedSTony Huang
2024e268fedSTony Huang if (!(cmd->flags & MMC_RSP_PRESENT))
2034e268fedSTony Huang return;
2044e268fedSTony Huang if (cmd->flags & MMC_RSP_136) {
2054e268fedSTony Huang if (spmmc_wait_rspbuf_full(host))
2064e268fedSTony Huang return;
2074e268fedSTony Huang value0_3 = readl(host->base + SPMMC_SD_RSPBUF0_3_REG);
2084e268fedSTony Huang value4_5 = readl(host->base + SPMMC_SD_RSPBUF4_5_REG) & 0xffff;
2094e268fedSTony Huang cmd->resp[0] = (value0_3 << 8) | (value4_5 >> 8);
2104e268fedSTony Huang cmd->resp[1] = value4_5 << 24;
2114e268fedSTony Huang value0_3 = readl(host->base + SPMMC_SD_RSPBUF0_3_REG);
2124e268fedSTony Huang value4_5 = readl(host->base + SPMMC_SD_RSPBUF4_5_REG) & 0xffff;
2134e268fedSTony Huang cmd->resp[1] |= value0_3 >> 8;
2144e268fedSTony Huang cmd->resp[2] = value0_3 << 24;
2154e268fedSTony Huang cmd->resp[2] |= value4_5 << 8;
2164e268fedSTony Huang value0_3 = readl(host->base + SPMMC_SD_RSPBUF0_3_REG);
2174e268fedSTony Huang value4_5 = readl(host->base + SPMMC_SD_RSPBUF4_5_REG) & 0xffff;
2184e268fedSTony Huang cmd->resp[2] |= value0_3 >> 24;
2194e268fedSTony Huang cmd->resp[3] = value0_3 << 8;
2204e268fedSTony Huang cmd->resp[3] |= value4_5 >> 8;
2214e268fedSTony Huang } else {
2224e268fedSTony Huang if (spmmc_wait_rspbuf_full(host))
2234e268fedSTony Huang return;
2244e268fedSTony Huang value0_3 = readl(host->base + SPMMC_SD_RSPBUF0_3_REG);
2254e268fedSTony Huang value4_5 = readl(host->base + SPMMC_SD_RSPBUF4_5_REG) & 0xffff;
2264e268fedSTony Huang cmd->resp[0] = (value0_3 << 8) | (value4_5 >> 8);
2274e268fedSTony Huang cmd->resp[1] = value4_5 << 24;
2284e268fedSTony Huang }
2294e268fedSTony Huang }
2304e268fedSTony Huang
spmmc_set_bus_clk(struct spmmc_host * host,int clk)2314e268fedSTony Huang static void spmmc_set_bus_clk(struct spmmc_host *host, int clk)
2324e268fedSTony Huang {
2334e268fedSTony Huang unsigned int clkdiv;
2344e268fedSTony Huang int f_min = host->mmc->f_min;
2354e268fedSTony Huang int f_max = host->mmc->f_max;
2364e268fedSTony Huang u32 value = readl(host->base + SPMMC_SD_CONFIG0_REG);
2374e268fedSTony Huang
2384e268fedSTony Huang if (clk < f_min)
2394e268fedSTony Huang clk = f_min;
2404e268fedSTony Huang if (clk > f_max)
2414e268fedSTony Huang clk = f_max;
2424e268fedSTony Huang
2434e268fedSTony Huang clkdiv = (clk_get_rate(host->clk) + clk) / clk - 1;
2444e268fedSTony Huang if (clkdiv > 0xfff)
2454e268fedSTony Huang clkdiv = 0xfff;
2464e268fedSTony Huang value &= ~SPMMC_CLOCK_DIVISION;
2474e268fedSTony Huang value |= FIELD_PREP(SPMMC_CLOCK_DIVISION, clkdiv);
2484e268fedSTony Huang writel(value, host->base + SPMMC_SD_CONFIG0_REG);
2494e268fedSTony Huang }
2504e268fedSTony Huang
spmmc_set_bus_timing(struct spmmc_host * host,unsigned int timing)2514e268fedSTony Huang static void spmmc_set_bus_timing(struct spmmc_host *host, unsigned int timing)
2524e268fedSTony Huang {
2534e268fedSTony Huang u32 value = readl(host->base + SPMMC_SD_CONFIG1_REG);
2544e268fedSTony Huang int clkdiv = FIELD_GET(SPMMC_CLOCK_DIVISION, readl(host->base + SPMMC_SD_CONFIG0_REG));
2554e268fedSTony Huang int delay = clkdiv / 2 < 7 ? clkdiv / 2 : 7;
2564e268fedSTony Huang int hs_en = 1, ddr_enabled = 0;
2574e268fedSTony Huang
2584e268fedSTony Huang switch (timing) {
2594e268fedSTony Huang case MMC_TIMING_LEGACY:
2604e268fedSTony Huang hs_en = 0;
2614e268fedSTony Huang break;
2624e268fedSTony Huang case MMC_TIMING_MMC_HS:
2634e268fedSTony Huang case MMC_TIMING_SD_HS:
2644e268fedSTony Huang case MMC_TIMING_UHS_SDR50:
2654e268fedSTony Huang case MMC_TIMING_UHS_SDR104:
2664e268fedSTony Huang case MMC_TIMING_MMC_HS200:
2674e268fedSTony Huang hs_en = 1;
2684e268fedSTony Huang break;
2694e268fedSTony Huang case MMC_TIMING_UHS_DDR50:
2704e268fedSTony Huang ddr_enabled = 1;
2714e268fedSTony Huang break;
2724e268fedSTony Huang case MMC_TIMING_MMC_DDR52:
2734e268fedSTony Huang ddr_enabled = 1;
2744e268fedSTony Huang break;
2754e268fedSTony Huang default:
2764e268fedSTony Huang hs_en = 0;
2774e268fedSTony Huang break;
2784e268fedSTony Huang }
2794e268fedSTony Huang
2804e268fedSTony Huang if (hs_en) {
2814e268fedSTony Huang value |= SPMMC_SD_HIGH_SPEED_EN;
2824e268fedSTony Huang writel(value, host->base + SPMMC_SD_CONFIG1_REG);
2834e268fedSTony Huang value = readl(host->base + SPMMC_SD_TIMING_CONFIG0_REG);
2844e268fedSTony Huang value &= ~SPMMC_SD_WRITE_DATA_DELAY;
2854e268fedSTony Huang value |= FIELD_PREP(SPMMC_SD_WRITE_DATA_DELAY, delay);
2864e268fedSTony Huang value &= ~SPMMC_SD_WRITE_COMMAND_DELAY;
2874e268fedSTony Huang value |= FIELD_PREP(SPMMC_SD_WRITE_COMMAND_DELAY, delay);
2884e268fedSTony Huang writel(value, host->base + SPMMC_SD_TIMING_CONFIG0_REG);
2894e268fedSTony Huang } else {
2904e268fedSTony Huang value &= ~SPMMC_SD_HIGH_SPEED_EN;
2914e268fedSTony Huang writel(value, host->base + SPMMC_SD_CONFIG1_REG);
2924e268fedSTony Huang }
2934e268fedSTony Huang if (ddr_enabled) {
2944e268fedSTony Huang value = readl(host->base + SPMMC_SD_CONFIG0_REG);
2954e268fedSTony Huang value |= SPMMC_SD_DDR_MODE;
2964e268fedSTony Huang writel(value, host->base + SPMMC_SD_CONFIG0_REG);
2974e268fedSTony Huang } else {
2984e268fedSTony Huang value = readl(host->base + SPMMC_SD_CONFIG0_REG);
2994e268fedSTony Huang value &= ~SPMMC_SD_DDR_MODE;
3004e268fedSTony Huang writel(value, host->base + SPMMC_SD_CONFIG0_REG);
3014e268fedSTony Huang }
3024e268fedSTony Huang }
3034e268fedSTony Huang
spmmc_set_bus_width(struct spmmc_host * host,int width)3044e268fedSTony Huang static void spmmc_set_bus_width(struct spmmc_host *host, int width)
3054e268fedSTony Huang {
3064e268fedSTony Huang u32 value = readl(host->base + SPMMC_SD_CONFIG0_REG);
3074e268fedSTony Huang
3084e268fedSTony Huang switch (width) {
3094e268fedSTony Huang case MMC_BUS_WIDTH_8:
3104e268fedSTony Huang value &= ~SPMMC_SD_DATA_WD;
3114e268fedSTony Huang value |= SPMMC_MMC8_EN;
3124e268fedSTony Huang break;
3134e268fedSTony Huang case MMC_BUS_WIDTH_4:
3144e268fedSTony Huang value |= SPMMC_SD_DATA_WD;
3154e268fedSTony Huang value &= ~SPMMC_MMC8_EN;
3164e268fedSTony Huang break;
3174e268fedSTony Huang default:
3184e268fedSTony Huang value &= ~SPMMC_SD_DATA_WD;
3194e268fedSTony Huang value &= ~SPMMC_MMC8_EN;
3204e268fedSTony Huang break;
3211e8cb505SYang Li }
3224e268fedSTony Huang writel(value, host->base + SPMMC_SD_CONFIG0_REG);
3234e268fedSTony Huang }
3244e268fedSTony Huang
3254e268fedSTony Huang /*
3264e268fedSTony Huang * select the working mode of controller: sd/sdio/emmc
3274e268fedSTony Huang */
spmmc_set_sdmmc_mode(struct spmmc_host * host)3284e268fedSTony Huang static void spmmc_set_sdmmc_mode(struct spmmc_host *host)
3294e268fedSTony Huang {
3304e268fedSTony Huang u32 value = readl(host->base + SPMMC_SD_CONFIG0_REG);
3314e268fedSTony Huang
3324e268fedSTony Huang value |= SPMMC_SD_MMC_MODE;
3334e268fedSTony Huang value &= ~SPMMC_SDIO_MODE;
3344e268fedSTony Huang writel(value, host->base + SPMMC_SD_CONFIG0_REG);
3354e268fedSTony Huang }
3364e268fedSTony Huang
spmmc_sw_reset(struct spmmc_host * host)3374e268fedSTony Huang static void spmmc_sw_reset(struct spmmc_host *host)
3384e268fedSTony Huang {
3394e268fedSTony Huang u32 value;
3404e268fedSTony Huang
3414e268fedSTony Huang /*
3424e268fedSTony Huang * Must reset dma operation first, or it will
3434e268fedSTony Huang * be stuck on sd_state == 0x1c00 because of
3444e268fedSTony Huang * a controller software reset bug
3454e268fedSTony Huang */
3464e268fedSTony Huang value = readl(host->base + SPMMC_HW_DMA_CTRL_REG);
3474e268fedSTony Huang value |= SPMMC_DMAIDLE;
3484e268fedSTony Huang writel(value, host->base + SPMMC_HW_DMA_CTRL_REG);
3494e268fedSTony Huang value &= ~SPMMC_DMAIDLE;
3504e268fedSTony Huang writel(value, host->base + SPMMC_HW_DMA_CTRL_REG);
3514e268fedSTony Huang value = readl(host->base + SPMMC_HW_DMA_CTRL_REG);
3524e268fedSTony Huang value |= SPMMC_HW_DMA_RST;
3534e268fedSTony Huang writel(value, host->base + SPMMC_HW_DMA_CTRL_REG);
3544e268fedSTony Huang writel(0x7, host->base + SPMMC_SD_RST_REG);
3554e268fedSTony Huang readl_poll_timeout_atomic(host->base + SPMMC_SD_HW_STATE_REG, value,
3564e268fedSTony Huang !(value & BIT(6)), 1, SPMMC_TIMEOUT_US);
3574e268fedSTony Huang }
3584e268fedSTony Huang
spmmc_prepare_cmd(struct spmmc_host * host,struct mmc_command * cmd)3594e268fedSTony Huang static void spmmc_prepare_cmd(struct spmmc_host *host, struct mmc_command *cmd)
3604e268fedSTony Huang {
3614e268fedSTony Huang u32 value;
3624e268fedSTony Huang
3634e268fedSTony Huang /* add start bit, according to spec, command format */
3644e268fedSTony Huang value = ((cmd->opcode | 0x40) << 24) | (cmd->arg >> 8);
3654e268fedSTony Huang writel(value, host->base + SPMMC_SD_CMDBUF0_3_REG);
3664e268fedSTony Huang writeb(cmd->arg & 0xff, host->base + SPMMC_SD_CMDBUF4_REG);
3674e268fedSTony Huang
3684e268fedSTony Huang /* disable interrupt if needed */
3694e268fedSTony Huang value = readl(host->base + SPMMC_SD_INT_REG);
3704e268fedSTony Huang value |= SPMMC_SDINT_SDCMPCLR;
3714e268fedSTony Huang value &= ~SPMMC_SDINT_SDCMPEN;
3724e268fedSTony Huang writel(value, host->base + SPMMC_SD_INT_REG);
3734e268fedSTony Huang
3744e268fedSTony Huang value = readl(host->base + SPMMC_SD_CONFIG0_REG);
3754e268fedSTony Huang value &= ~SPMMC_SD_TRANS_MODE;
3764e268fedSTony Huang value |= SPMMC_SD_CMD_DUMMY;
3774e268fedSTony Huang if (cmd->flags & MMC_RSP_PRESENT) {
3784e268fedSTony Huang value |= SPMMC_SD_AUTO_RESPONSE;
3794e268fedSTony Huang } else {
3804e268fedSTony Huang value &= ~SPMMC_SD_AUTO_RESPONSE;
3814e268fedSTony Huang writel(value, host->base + SPMMC_SD_CONFIG0_REG);
3824e268fedSTony Huang
3834e268fedSTony Huang return;
3844e268fedSTony Huang }
3854e268fedSTony Huang /*
3864e268fedSTony Huang * Currently, host is not capable of checking R2's CRC7,
3874e268fedSTony Huang * thus, enable crc7 check only for 48 bit response commands
3884e268fedSTony Huang */
3894e268fedSTony Huang if (cmd->flags & MMC_RSP_CRC && !(cmd->flags & MMC_RSP_136))
3904e268fedSTony Huang value |= SPMMC_SD_RSP_CHK_EN;
3914e268fedSTony Huang else
3924e268fedSTony Huang value &= ~SPMMC_SD_RSP_CHK_EN;
3934e268fedSTony Huang
3944e268fedSTony Huang if (cmd->flags & MMC_RSP_136)
3954e268fedSTony Huang value |= SPMMC_SD_RSP_TYPE;
3964e268fedSTony Huang else
3974e268fedSTony Huang value &= ~SPMMC_SD_RSP_TYPE;
3984e268fedSTony Huang writel(value, host->base + SPMMC_SD_CONFIG0_REG);
3994e268fedSTony Huang }
4004e268fedSTony Huang
spmmc_prepare_data(struct spmmc_host * host,struct mmc_data * data)4014e268fedSTony Huang static void spmmc_prepare_data(struct spmmc_host *host, struct mmc_data *data)
4024e268fedSTony Huang {
4034e268fedSTony Huang u32 value, srcdst;
4044e268fedSTony Huang
4054e268fedSTony Huang writel(data->blocks - 1, host->base + SPMMC_SD_PAGE_NUM_REG);
4064e268fedSTony Huang writel(data->blksz - 1, host->base + SPMMC_SD_BLOCKSIZE_REG);
4074e268fedSTony Huang value = readl(host->base + SPMMC_SD_CONFIG0_REG);
4084e268fedSTony Huang if (data->flags & MMC_DATA_READ) {
4094e268fedSTony Huang value &= ~SPMMC_SD_TRANS_MODE;
4104e268fedSTony Huang value |= FIELD_PREP(SPMMC_SD_TRANS_MODE, 2);
4114e268fedSTony Huang value &= ~SPMMC_SD_AUTO_RESPONSE;
4124e268fedSTony Huang value &= ~SPMMC_SD_CMD_DUMMY;
4134e268fedSTony Huang srcdst = readl(host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG);
4144e268fedSTony Huang srcdst &= ~SPMMC_DMA_SOURCE;
4154e268fedSTony Huang srcdst |= FIELD_PREP(SPMMC_DMA_SOURCE, 0x2);
4164e268fedSTony Huang srcdst &= ~SPMMC_DMA_DESTINATION;
4174e268fedSTony Huang srcdst |= FIELD_PREP(SPMMC_DMA_DESTINATION, 0x1);
4184e268fedSTony Huang writel(srcdst, host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG);
4194e268fedSTony Huang } else {
4204e268fedSTony Huang value &= ~SPMMC_SD_TRANS_MODE;
4214e268fedSTony Huang value |= FIELD_PREP(SPMMC_SD_TRANS_MODE, 1);
4224e268fedSTony Huang srcdst = readl(host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG);
4234e268fedSTony Huang srcdst &= ~SPMMC_DMA_SOURCE;
4244e268fedSTony Huang srcdst |= FIELD_PREP(SPMMC_DMA_SOURCE, 0x1);
4254e268fedSTony Huang srcdst &= ~SPMMC_DMA_DESTINATION;
4264e268fedSTony Huang srcdst |= FIELD_PREP(SPMMC_DMA_DESTINATION, 0x2);
4274e268fedSTony Huang writel(srcdst, host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG);
4284e268fedSTony Huang }
4294e268fedSTony Huang
4304e268fedSTony Huang value |= SPMMC_SD_LEN_MODE;
4314e268fedSTony Huang if (host->dmapio_mode == SPMMC_DMA_MODE) {
4324e268fedSTony Huang struct scatterlist *sg;
4334e268fedSTony Huang dma_addr_t dma_addr;
4344e268fedSTony Huang unsigned int dma_size;
4354e268fedSTony Huang int i, count = 1;
4364e268fedSTony Huang
4374e268fedSTony Huang count = dma_map_sg(host->mmc->parent, data->sg, data->sg_len,
4384e268fedSTony Huang mmc_get_dma_dir(data));
4394e268fedSTony Huang if (!count || count > SPMMC_MAX_DMA_MEMORY_SECTORS) {
4404e268fedSTony Huang data->error = -EINVAL;
4414e268fedSTony Huang
4424e268fedSTony Huang return;
4434e268fedSTony Huang }
4444e268fedSTony Huang for_each_sg(data->sg, sg, count, i) {
4454e268fedSTony Huang dma_addr = sg_dma_address(sg);
4464e268fedSTony Huang dma_size = sg_dma_len(sg) / data->blksz - 1;
4474e268fedSTony Huang if (i == 0) {
4484e268fedSTony Huang writel(dma_addr, host->base + SPMMC_DMA_BASE_ADDR_REG);
4494e268fedSTony Huang writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_0_SIZE_REG);
4504e268fedSTony Huang } else if (i == 1) {
4514e268fedSTony Huang writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_1_ADDR_REG);
4524e268fedSTony Huang writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_1_LENG_REG);
4534e268fedSTony Huang } else if (i == 2) {
4544e268fedSTony Huang writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_2_ADDR_REG);
4554e268fedSTony Huang writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_2_LENG_REG);
4564e268fedSTony Huang } else if (i == 3) {
4574e268fedSTony Huang writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_3_ADDR_REG);
4584e268fedSTony Huang writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_3_LENG_REG);
4594e268fedSTony Huang } else if (i == 4) {
4604e268fedSTony Huang writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_4_ADDR_REG);
4614e268fedSTony Huang writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_4_LENG_REG);
4624e268fedSTony Huang } else if (i == 5) {
4634e268fedSTony Huang writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_5_ADDR_REG);
4644e268fedSTony Huang writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_5_LENG_REG);
4654e268fedSTony Huang } else if (i == 6) {
4664e268fedSTony Huang writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_6_ADDR_REG);
4674e268fedSTony Huang writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_6_LENG_REG);
4684e268fedSTony Huang } else if (i == 7) {
4694e268fedSTony Huang writel(dma_addr, host->base + SPMMC_SDRAM_SECTOR_7_ADDR_REG);
4704e268fedSTony Huang writel(dma_size, host->base + SPMMC_SDRAM_SECTOR_7_LENG_REG);
4714e268fedSTony Huang }
4724e268fedSTony Huang }
4734e268fedSTony Huang value &= ~SPMMC_SD_PIO_MODE;
4744e268fedSTony Huang writel(value, host->base + SPMMC_SD_CONFIG0_REG);
4754e268fedSTony Huang /* enable interrupt if needed */
4764e268fedSTony Huang if (data->blksz * data->blocks > host->dma_int_threshold) {
4774e268fedSTony Huang host->dma_use_int = 1;
4784e268fedSTony Huang value = readl(host->base + SPMMC_SD_INT_REG);
4794e268fedSTony Huang value &= ~SPMMC_SDINT_SDCMPEN;
4804e268fedSTony Huang value |= FIELD_PREP(SPMMC_SDINT_SDCMPEN, 1); /* sdcmpen */
4814e268fedSTony Huang writel(value, host->base + SPMMC_SD_INT_REG);
4824e268fedSTony Huang }
4834e268fedSTony Huang } else {
4844e268fedSTony Huang value |= SPMMC_SD_PIO_MODE;
4854e268fedSTony Huang value |= SPMMC_RX4_EN;
4864e268fedSTony Huang writel(value, host->base + SPMMC_SD_CONFIG0_REG);
4874e268fedSTony Huang }
4884e268fedSTony Huang }
4894e268fedSTony Huang
spmmc_trigger_transaction(struct spmmc_host * host)4904e268fedSTony Huang static inline void spmmc_trigger_transaction(struct spmmc_host *host)
4914e268fedSTony Huang {
4924e268fedSTony Huang u32 value = readl(host->base + SPMMC_SD_CTRL_REG);
4934e268fedSTony Huang
4944e268fedSTony Huang value |= SPMMC_NEW_COMMAND_TRIGGER;
4954e268fedSTony Huang writel(value, host->base + SPMMC_SD_CTRL_REG);
4964e268fedSTony Huang }
4974e268fedSTony Huang
spmmc_send_stop_cmd(struct spmmc_host * host)4984e268fedSTony Huang static void spmmc_send_stop_cmd(struct spmmc_host *host)
4994e268fedSTony Huang {
5004e268fedSTony Huang struct mmc_command stop = {};
5014e268fedSTony Huang u32 value;
5024e268fedSTony Huang
5034e268fedSTony Huang stop.opcode = MMC_STOP_TRANSMISSION;
5044e268fedSTony Huang stop.arg = 0;
5054e268fedSTony Huang stop.flags = MMC_RSP_R1B;
5064e268fedSTony Huang spmmc_prepare_cmd(host, &stop);
5074e268fedSTony Huang value = readl(host->base + SPMMC_SD_INT_REG);
5084e268fedSTony Huang value &= ~SPMMC_SDINT_SDCMPEN;
5094e268fedSTony Huang value |= FIELD_PREP(SPMMC_SDINT_SDCMPEN, 0);
5104e268fedSTony Huang writel(value, host->base + SPMMC_SD_INT_REG);
5114e268fedSTony Huang spmmc_trigger_transaction(host);
5124e268fedSTony Huang readl_poll_timeout(host->base + SPMMC_SD_STATE_REG, value,
5134e268fedSTony Huang (value & SPMMC_SDSTATE_FINISH), 1, SPMMC_TIMEOUT_US);
5144e268fedSTony Huang }
5154e268fedSTony Huang
spmmc_check_error(struct spmmc_host * host,struct mmc_request * mrq)5164e268fedSTony Huang static int spmmc_check_error(struct spmmc_host *host, struct mmc_request *mrq)
5174e268fedSTony Huang {
5184e268fedSTony Huang int ret = 0;
5194e268fedSTony Huang struct mmc_command *cmd = mrq->cmd;
5204e268fedSTony Huang struct mmc_data *data = mrq->data;
5214e268fedSTony Huang
5224e268fedSTony Huang u32 value = readl(host->base + SPMMC_SD_STATE_REG);
5234e268fedSTony Huang u32 crc_token = FIELD_GET(SPMMC_CRCTOKEN_CHECK_RESULT, value);
5244e268fedSTony Huang
5254e268fedSTony Huang if (value & SPMMC_SDSTATE_ERROR) {
5264e268fedSTony Huang u32 timing_cfg0 = 0;
5274e268fedSTony Huang
5284e268fedSTony Huang value = readl(host->base + SPMMC_SD_STATUS_REG);
5294e268fedSTony Huang
5304e268fedSTony Huang if (host->tuning_info.enable_tuning) {
5314e268fedSTony Huang timing_cfg0 = readl(host->base + SPMMC_SD_TIMING_CONFIG0_REG);
5324e268fedSTony Huang host->tuning_info.rd_crc_dly = FIELD_GET(SPMMC_SD_READ_CRC_DELAY,
5334e268fedSTony Huang timing_cfg0);
5344e268fedSTony Huang host->tuning_info.rd_dat_dly = FIELD_GET(SPMMC_SD_READ_DATA_DELAY,
5354e268fedSTony Huang timing_cfg0);
5364e268fedSTony Huang host->tuning_info.rd_rsp_dly = FIELD_GET(SPMMC_SD_READ_RESPONSE_DELAY,
5374e268fedSTony Huang timing_cfg0);
5384e268fedSTony Huang host->tuning_info.wr_cmd_dly = FIELD_GET(SPMMC_SD_WRITE_COMMAND_DELAY,
5394e268fedSTony Huang timing_cfg0);
5404e268fedSTony Huang host->tuning_info.wr_dat_dly = FIELD_GET(SPMMC_SD_WRITE_DATA_DELAY,
5414e268fedSTony Huang timing_cfg0);
5424e268fedSTony Huang }
5434e268fedSTony Huang
5444e268fedSTony Huang if (value & SPMMC_SDSTATUS_RSP_TIMEOUT) {
5454e268fedSTony Huang ret = -ETIMEDOUT;
5464e268fedSTony Huang host->tuning_info.wr_cmd_dly++;
5474e268fedSTony Huang } else if (value & SPMMC_SDSTATUS_RSP_CRC7_ERROR) {
5484e268fedSTony Huang ret = -EILSEQ;
5494e268fedSTony Huang host->tuning_info.rd_rsp_dly++;
5504e268fedSTony Huang } else if (data) {
5514e268fedSTony Huang if ((value & SPMMC_SDSTATUS_STB_TIMEOUT)) {
5524e268fedSTony Huang ret = -ETIMEDOUT;
5534e268fedSTony Huang host->tuning_info.rd_dat_dly++;
5544e268fedSTony Huang } else if (value & SPMMC_SDSTATUS_RDATA_CRC16_ERROR) {
5554e268fedSTony Huang ret = -EILSEQ;
5564e268fedSTony Huang host->tuning_info.rd_dat_dly++;
5574e268fedSTony Huang } else if (value & SPMMC_SDSTATUS_CARD_CRC_CHECK_TIMEOUT) {
5584e268fedSTony Huang ret = -ETIMEDOUT;
5594e268fedSTony Huang host->tuning_info.rd_crc_dly++;
5604e268fedSTony Huang } else if (value & SPMMC_SDSTATUS_CRC_TOKEN_CHECK_ERROR) {
5614e268fedSTony Huang ret = -EILSEQ;
5624e268fedSTony Huang if (crc_token == 0x5)
5634e268fedSTony Huang host->tuning_info.wr_dat_dly++;
5644e268fedSTony Huang else
5654e268fedSTony Huang host->tuning_info.rd_crc_dly++;
5664e268fedSTony Huang }
5674e268fedSTony Huang }
5684e268fedSTony Huang cmd->error = ret;
5694e268fedSTony Huang if (data) {
5704e268fedSTony Huang data->error = ret;
5714e268fedSTony Huang data->bytes_xfered = 0;
5724e268fedSTony Huang }
5734e268fedSTony Huang if (!host->tuning_info.need_tuning && host->tuning_info.enable_tuning)
5744e268fedSTony Huang cmd->retries = SPMMC_MAX_RETRIES;
5754e268fedSTony Huang spmmc_sw_reset(host);
5764e268fedSTony Huang
5774e268fedSTony Huang if (host->tuning_info.enable_tuning) {
5784e268fedSTony Huang timing_cfg0 &= ~SPMMC_SD_READ_CRC_DELAY;
5794e268fedSTony Huang timing_cfg0 |= FIELD_PREP(SPMMC_SD_READ_CRC_DELAY,
5804e268fedSTony Huang host->tuning_info.rd_crc_dly);
5814e268fedSTony Huang timing_cfg0 &= ~SPMMC_SD_READ_DATA_DELAY;
5824e268fedSTony Huang timing_cfg0 |= FIELD_PREP(SPMMC_SD_READ_DATA_DELAY,
5834e268fedSTony Huang host->tuning_info.rd_dat_dly);
5844e268fedSTony Huang timing_cfg0 &= ~SPMMC_SD_READ_RESPONSE_DELAY;
5854e268fedSTony Huang timing_cfg0 |= FIELD_PREP(SPMMC_SD_READ_RESPONSE_DELAY,
5864e268fedSTony Huang host->tuning_info.rd_rsp_dly);
5874e268fedSTony Huang timing_cfg0 &= ~SPMMC_SD_WRITE_COMMAND_DELAY;
5884e268fedSTony Huang timing_cfg0 |= FIELD_PREP(SPMMC_SD_WRITE_COMMAND_DELAY,
5894e268fedSTony Huang host->tuning_info.wr_cmd_dly);
5904e268fedSTony Huang timing_cfg0 &= ~SPMMC_SD_WRITE_DATA_DELAY;
5914e268fedSTony Huang timing_cfg0 |= FIELD_PREP(SPMMC_SD_WRITE_DATA_DELAY,
5924e268fedSTony Huang host->tuning_info.wr_dat_dly);
5934e268fedSTony Huang writel(timing_cfg0, host->base + SPMMC_SD_TIMING_CONFIG0_REG);
5944e268fedSTony Huang }
5954e268fedSTony Huang } else if (data) {
5964e268fedSTony Huang data->error = 0;
5974e268fedSTony Huang data->bytes_xfered = data->blocks * data->blksz;
5984e268fedSTony Huang }
5994e268fedSTony Huang host->tuning_info.need_tuning = ret;
6004e268fedSTony Huang
6014e268fedSTony Huang return ret;
6024e268fedSTony Huang }
6034e268fedSTony Huang
6044e268fedSTony Huang /*
6054e268fedSTony Huang * the strategy is:
6064e268fedSTony Huang * 1. if several continuous delays are acceptable, we choose a middle one;
6074e268fedSTony Huang * 2. otherwise, we choose the first one.
6084e268fedSTony Huang */
spmmc_find_best_delay(u8 candidate_dly)6094e268fedSTony Huang static inline int spmmc_find_best_delay(u8 candidate_dly)
6104e268fedSTony Huang {
6114e268fedSTony Huang int f, w, value;
6124e268fedSTony Huang
6134e268fedSTony Huang if (!candidate_dly)
6144e268fedSTony Huang return 0;
6154e268fedSTony Huang f = ffs(candidate_dly) - 1;
6164e268fedSTony Huang w = hweight8(candidate_dly);
6174e268fedSTony Huang value = ((1 << w) - 1) << f;
6184e268fedSTony Huang if (0xff == (value & ~candidate_dly))
6194e268fedSTony Huang return (f + w / 2);
6204e268fedSTony Huang else
6214e268fedSTony Huang return (f);
6224e268fedSTony Huang }
6234e268fedSTony Huang
spmmc_xfer_data_pio(struct spmmc_host * host,struct mmc_data * data)6244e268fedSTony Huang static void spmmc_xfer_data_pio(struct spmmc_host *host, struct mmc_data *data)
6254e268fedSTony Huang {
6264e268fedSTony Huang u32 *buf;
6274e268fedSTony Huang int data_left = data->blocks * data->blksz;
6284e268fedSTony Huang int consumed, remain;
6294e268fedSTony Huang
6304e268fedSTony Huang struct sg_mapping_iter sg_miter;
6314e268fedSTony Huang unsigned int flags = 0;
6324e268fedSTony Huang
6334e268fedSTony Huang if (data->flags & MMC_DATA_WRITE)
6344e268fedSTony Huang flags |= SG_MITER_FROM_SG;
6354e268fedSTony Huang else
6364e268fedSTony Huang flags |= SG_MITER_TO_SG;
6374e268fedSTony Huang sg_miter_start(&sg_miter, data->sg, data->sg_len, flags);
6384e268fedSTony Huang while (data_left > 0) {
6394e268fedSTony Huang consumed = 0;
6404e268fedSTony Huang if (!sg_miter_next(&sg_miter))
6414e268fedSTony Huang break;
6424e268fedSTony Huang buf = sg_miter.addr;
6434e268fedSTony Huang remain = sg_miter.length;
6444e268fedSTony Huang do {
6454e268fedSTony Huang if (data->flags & MMC_DATA_WRITE) {
6464e268fedSTony Huang if (spmmc_wait_txbuf_empty(host))
6474e268fedSTony Huang goto done;
6484e268fedSTony Huang writel(*buf, host->base + SPMMC_SD_PIODATATX_REG);
6494e268fedSTony Huang } else {
6504e268fedSTony Huang if (spmmc_wait_rxbuf_full(host))
6514e268fedSTony Huang goto done;
6524e268fedSTony Huang *buf = readl(host->base + SPMMC_SD_PIODATARX_REG);
6534e268fedSTony Huang }
6544e268fedSTony Huang buf++;
6554e268fedSTony Huang /* tx/rx 4 bytes one time in pio mode */
6564e268fedSTony Huang consumed += 4;
6574e268fedSTony Huang remain -= 4;
6584e268fedSTony Huang } while (remain);
6594e268fedSTony Huang sg_miter.consumed = consumed;
6604e268fedSTony Huang data_left -= consumed;
6614e268fedSTony Huang }
6624e268fedSTony Huang done:
6634e268fedSTony Huang sg_miter_stop(&sg_miter);
6644e268fedSTony Huang }
6654e268fedSTony Huang
spmmc_controller_init(struct spmmc_host * host)6664e268fedSTony Huang static void spmmc_controller_init(struct spmmc_host *host)
6674e268fedSTony Huang {
6684e268fedSTony Huang u32 value;
6694e268fedSTony Huang int ret = reset_control_assert(host->rstc);
6704e268fedSTony Huang
6714e268fedSTony Huang if (!ret) {
6724e268fedSTony Huang usleep_range(1000, 1250);
6734e268fedSTony Huang ret = reset_control_deassert(host->rstc);
6744e268fedSTony Huang }
6754e268fedSTony Huang
6764e268fedSTony Huang value = readl(host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG);
6774e268fedSTony Huang value &= ~SPMMC_MEDIA_TYPE;
6784e268fedSTony Huang value |= FIELD_PREP(SPMMC_MEDIA_TYPE, SPMMC_MEDIA_SD);
6794e268fedSTony Huang writel(value, host->base + SPMMC_CARD_MEDIATYPE_SRCDST_REG);
6804e268fedSTony Huang }
6814e268fedSTony Huang
6824e268fedSTony Huang /*
6834e268fedSTony Huang * 1. unmap scatterlist if needed;
6844e268fedSTony Huang * 2. get response & check error conditions;
6854e268fedSTony Huang * 3. notify mmc layer the request is done
6864e268fedSTony Huang */
spmmc_finish_request(struct spmmc_host * host,struct mmc_request * mrq)6874e268fedSTony Huang static void spmmc_finish_request(struct spmmc_host *host, struct mmc_request *mrq)
6884e268fedSTony Huang {
6894e268fedSTony Huang struct mmc_command *cmd;
6904e268fedSTony Huang struct mmc_data *data;
6914e268fedSTony Huang
6924e268fedSTony Huang if (!mrq)
6934e268fedSTony Huang return;
6944e268fedSTony Huang
6954e268fedSTony Huang cmd = mrq->cmd;
6964e268fedSTony Huang data = mrq->data;
6974e268fedSTony Huang
6984e268fedSTony Huang if (data && SPMMC_DMA_MODE == host->dmapio_mode) {
6994e268fedSTony Huang dma_unmap_sg(host->mmc->parent, data->sg, data->sg_len, mmc_get_dma_dir(data));
7004e268fedSTony Huang host->dma_use_int = 0;
7014e268fedSTony Huang }
7024e268fedSTony Huang
7034e268fedSTony Huang spmmc_get_rsp(host, cmd);
7044e268fedSTony Huang spmmc_check_error(host, mrq);
7054e268fedSTony Huang if (mrq->stop)
7064e268fedSTony Huang spmmc_send_stop_cmd(host);
7074e268fedSTony Huang
7084e268fedSTony Huang host->mrq = NULL;
7094e268fedSTony Huang mmc_request_done(host->mmc, mrq);
7104e268fedSTony Huang }
7114e268fedSTony Huang
7124e268fedSTony Huang /* Interrupt Service Routine */
spmmc_irq(int irq,void * dev_id)7134e268fedSTony Huang static irqreturn_t spmmc_irq(int irq, void *dev_id)
7144e268fedSTony Huang {
7154e268fedSTony Huang struct spmmc_host *host = dev_id;
7164e268fedSTony Huang u32 value = readl(host->base + SPMMC_SD_INT_REG);
7174e268fedSTony Huang
7184e268fedSTony Huang if ((value & SPMMC_SDINT_SDCMP) && (value & SPMMC_SDINT_SDCMPEN)) {
7194e268fedSTony Huang value &= ~SPMMC_SDINT_SDCMPEN;
7204e268fedSTony Huang value |= SPMMC_SDINT_SDCMPCLR;
7214e268fedSTony Huang writel(value, host->base + SPMMC_SD_INT_REG);
7224e268fedSTony Huang return IRQ_WAKE_THREAD;
7234e268fedSTony Huang }
7244e268fedSTony Huang return IRQ_HANDLED;
7254e268fedSTony Huang }
7264e268fedSTony Huang
spmmc_request(struct mmc_host * mmc,struct mmc_request * mrq)7274e268fedSTony Huang static void spmmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
7284e268fedSTony Huang {
7294e268fedSTony Huang struct spmmc_host *host = mmc_priv(mmc);
7304e268fedSTony Huang struct mmc_data *data;
7314e268fedSTony Huang struct mmc_command *cmd;
7324e268fedSTony Huang
7334e268fedSTony Huang host->mrq = mrq;
7344e268fedSTony Huang data = mrq->data;
7354e268fedSTony Huang cmd = mrq->cmd;
7364e268fedSTony Huang
7374e268fedSTony Huang spmmc_prepare_cmd(host, cmd);
7384e268fedSTony Huang /* we need manually read response R2. */
7394e268fedSTony Huang if (cmd->flags & MMC_RSP_136) {
7404e268fedSTony Huang spmmc_trigger_transaction(host);
7414e268fedSTony Huang spmmc_get_rsp(host, cmd);
7424e268fedSTony Huang spmmc_wait_finish(host);
7434e268fedSTony Huang spmmc_check_error(host, mrq);
7444e268fedSTony Huang host->mrq = NULL;
7454e268fedSTony Huang mmc_request_done(host->mmc, mrq);
7464e268fedSTony Huang } else {
7474e268fedSTony Huang if (data)
7484e268fedSTony Huang spmmc_prepare_data(host, data);
7494e268fedSTony Huang
7504e268fedSTony Huang if (host->dmapio_mode == SPMMC_PIO_MODE && data) {
7514e268fedSTony Huang u32 value;
7524e268fedSTony Huang /* pio data transfer do not use interrupt */
7534e268fedSTony Huang value = readl(host->base + SPMMC_SD_INT_REG);
7544e268fedSTony Huang value &= ~SPMMC_SDINT_SDCMPEN;
7554e268fedSTony Huang writel(value, host->base + SPMMC_SD_INT_REG);
7564e268fedSTony Huang spmmc_trigger_transaction(host);
7574e268fedSTony Huang spmmc_xfer_data_pio(host, data);
7584e268fedSTony Huang spmmc_wait_finish(host);
7594e268fedSTony Huang spmmc_finish_request(host, mrq);
7604e268fedSTony Huang } else {
7614e268fedSTony Huang if (host->dma_use_int) {
7624e268fedSTony Huang spmmc_trigger_transaction(host);
7634e268fedSTony Huang } else {
7644e268fedSTony Huang spmmc_trigger_transaction(host);
7654e268fedSTony Huang spmmc_wait_finish(host);
7664e268fedSTony Huang spmmc_finish_request(host, mrq);
7674e268fedSTony Huang }
7684e268fedSTony Huang }
7694e268fedSTony Huang }
7704e268fedSTony Huang }
7714e268fedSTony Huang
spmmc_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)7724e268fedSTony Huang static void spmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
7734e268fedSTony Huang {
7744e268fedSTony Huang struct spmmc_host *host = (struct spmmc_host *)mmc_priv(mmc);
7754e268fedSTony Huang
7764e268fedSTony Huang spmmc_set_bus_clk(host, ios->clock);
7774e268fedSTony Huang spmmc_set_bus_timing(host, ios->timing);
7784e268fedSTony Huang spmmc_set_bus_width(host, ios->bus_width);
7794e268fedSTony Huang /* ensure mode is correct, because we might have hw reset the controller */
7804e268fedSTony Huang spmmc_set_sdmmc_mode(host);
7814e268fedSTony Huang }
7824e268fedSTony Huang
7834e268fedSTony Huang /*
7844e268fedSTony Huang * Return values for the get_cd callback should be:
7854e268fedSTony Huang * 0 for a absent card
7864e268fedSTony Huang * 1 for a present card
7874e268fedSTony Huang * -ENOSYS when not supported (equal to NULL callback)
7884e268fedSTony Huang * or a negative errno value when something bad happened
7894e268fedSTony Huang */
spmmc_get_cd(struct mmc_host * mmc)7904e268fedSTony Huang static int spmmc_get_cd(struct mmc_host *mmc)
7914e268fedSTony Huang {
7924e268fedSTony Huang int ret = 0;
7934e268fedSTony Huang
7944e268fedSTony Huang if (mmc_can_gpio_cd(mmc))
7954e268fedSTony Huang ret = mmc_gpio_get_cd(mmc);
7964e268fedSTony Huang
7974e268fedSTony Huang if (ret < 0)
7984e268fedSTony Huang ret = 0;
7994e268fedSTony Huang
8004e268fedSTony Huang return ret;
8014e268fedSTony Huang }
8024e268fedSTony Huang
spmmc_execute_tuning(struct mmc_host * mmc,u32 opcode)8034e268fedSTony Huang static int spmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
8044e268fedSTony Huang {
8054e268fedSTony Huang struct spmmc_host *host = mmc_priv(mmc);
8064e268fedSTony Huang u8 smpl_dly = 0, candidate_dly = 0;
8074e268fedSTony Huang u32 value;
8084e268fedSTony Huang
8094e268fedSTony Huang host->tuning_info.enable_tuning = 0;
8104e268fedSTony Huang do {
8114e268fedSTony Huang value = readl(host->base + SPMMC_SD_TIMING_CONFIG0_REG);
8124e268fedSTony Huang value &= ~SPMMC_SD_READ_RESPONSE_DELAY;
8134e268fedSTony Huang value |= FIELD_PREP(SPMMC_SD_READ_RESPONSE_DELAY, smpl_dly);
8144e268fedSTony Huang value &= ~SPMMC_SD_READ_DATA_DELAY;
8154e268fedSTony Huang value |= FIELD_PREP(SPMMC_SD_READ_DATA_DELAY, smpl_dly);
8164e268fedSTony Huang value &= ~SPMMC_SD_READ_CRC_DELAY;
8174e268fedSTony Huang value |= FIELD_PREP(SPMMC_SD_READ_CRC_DELAY, smpl_dly);
8184e268fedSTony Huang writel(value, host->base + SPMMC_SD_TIMING_CONFIG0_REG);
8194e268fedSTony Huang
8204e268fedSTony Huang if (!mmc_send_tuning(mmc, opcode, NULL)) {
8214e268fedSTony Huang candidate_dly |= (1 << smpl_dly);
8224e268fedSTony Huang break;
8234e268fedSTony Huang }
8244e268fedSTony Huang } while (smpl_dly++ <= SPMMC_MAX_TUNABLE_DLY);
8254e268fedSTony Huang host->tuning_info.enable_tuning = 1;
8264e268fedSTony Huang
8274e268fedSTony Huang if (candidate_dly) {
8284e268fedSTony Huang smpl_dly = spmmc_find_best_delay(candidate_dly);
8294e268fedSTony Huang value = readl(host->base + SPMMC_SD_TIMING_CONFIG0_REG);
8304e268fedSTony Huang value &= ~SPMMC_SD_READ_RESPONSE_DELAY;
8314e268fedSTony Huang value |= FIELD_PREP(SPMMC_SD_READ_RESPONSE_DELAY, smpl_dly);
8324e268fedSTony Huang value &= ~SPMMC_SD_READ_DATA_DELAY;
8334e268fedSTony Huang value |= FIELD_PREP(SPMMC_SD_READ_DATA_DELAY, smpl_dly);
8344e268fedSTony Huang value &= ~SPMMC_SD_READ_CRC_DELAY;
8354e268fedSTony Huang value |= FIELD_PREP(SPMMC_SD_READ_CRC_DELAY, smpl_dly);
8364e268fedSTony Huang writel(value, host->base + SPMMC_SD_TIMING_CONFIG0_REG);
8374e268fedSTony Huang return 0;
8384e268fedSTony Huang }
8394e268fedSTony Huang
8404e268fedSTony Huang return -EIO;
8414e268fedSTony Huang }
8424e268fedSTony Huang
8434e268fedSTony Huang static const struct mmc_host_ops spmmc_ops = {
8444e268fedSTony Huang .request = spmmc_request,
8454e268fedSTony Huang .set_ios = spmmc_set_ios,
8464e268fedSTony Huang .get_cd = spmmc_get_cd,
8474e268fedSTony Huang .execute_tuning = spmmc_execute_tuning,
8484e268fedSTony Huang };
8494e268fedSTony Huang
spmmc_func_finish_req(int irq,void * dev_id)8504e268fedSTony Huang static irqreturn_t spmmc_func_finish_req(int irq, void *dev_id)
8514e268fedSTony Huang {
8524e268fedSTony Huang struct spmmc_host *host = dev_id;
8534e268fedSTony Huang
8544e268fedSTony Huang spmmc_finish_request(host, host->mrq);
8554e268fedSTony Huang
8564e268fedSTony Huang return IRQ_HANDLED;
8574e268fedSTony Huang }
8584e268fedSTony Huang
spmmc_drv_probe(struct platform_device * pdev)8594e268fedSTony Huang static int spmmc_drv_probe(struct platform_device *pdev)
8604e268fedSTony Huang {
8614e268fedSTony Huang struct mmc_host *mmc;
8624e268fedSTony Huang struct resource *res;
8634e268fedSTony Huang struct spmmc_host *host;
8644e268fedSTony Huang int ret = 0;
8654e268fedSTony Huang
866cf3f15b8SHarshit Mogalapalli mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(struct spmmc_host));
867cf3f15b8SHarshit Mogalapalli if (!mmc)
868cf3f15b8SHarshit Mogalapalli return -ENOMEM;
8694e268fedSTony Huang
8704e268fedSTony Huang host = mmc_priv(mmc);
8714e268fedSTony Huang host->mmc = mmc;
8724e268fedSTony Huang host->dmapio_mode = SPMMC_DMA_MODE;
8734e268fedSTony Huang host->dma_int_threshold = 1024;
8744e268fedSTony Huang
8754e268fedSTony Huang host->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
8764e268fedSTony Huang if (IS_ERR(host->base))
8774e268fedSTony Huang return PTR_ERR(host->base);
8784e268fedSTony Huang
8794e268fedSTony Huang host->clk = devm_clk_get(&pdev->dev, NULL);
8804e268fedSTony Huang if (IS_ERR(host->clk))
8814e268fedSTony Huang return dev_err_probe(&pdev->dev, PTR_ERR(host->clk), "clk get fail\n");
8824e268fedSTony Huang
8834e268fedSTony Huang host->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
8844e268fedSTony Huang if (IS_ERR(host->rstc))
8854e268fedSTony Huang return dev_err_probe(&pdev->dev, PTR_ERR(host->rstc), "rst get fail\n");
8864e268fedSTony Huang
8874e268fedSTony Huang host->irq = platform_get_irq(pdev, 0);
888117d73b1SHarshit Mogalapalli if (host->irq < 0)
8894e268fedSTony Huang return host->irq;
8904e268fedSTony Huang
8914e268fedSTony Huang ret = devm_request_threaded_irq(&pdev->dev, host->irq,
8924e268fedSTony Huang spmmc_irq, spmmc_func_finish_req, IRQF_SHARED,
8934e268fedSTony Huang NULL, host);
8944e268fedSTony Huang if (ret)
8954e268fedSTony Huang return ret;
8964e268fedSTony Huang
8974e268fedSTony Huang ret = clk_prepare_enable(host->clk);
8984e268fedSTony Huang if (ret)
8994e268fedSTony Huang return dev_err_probe(&pdev->dev, ret, "failed to enable clk\n");
9004e268fedSTony Huang
9014e268fedSTony Huang ret = mmc_of_parse(mmc);
9024e268fedSTony Huang if (ret)
903dce6d8f9SWei Chen goto clk_disable;
9044e268fedSTony Huang
9054e268fedSTony Huang mmc->ops = &spmmc_ops;
9064e268fedSTony Huang mmc->f_min = SPMMC_MIN_CLK;
9074e268fedSTony Huang if (mmc->f_max > SPMMC_MAX_CLK)
9084e268fedSTony Huang mmc->f_max = SPMMC_MAX_CLK;
9094e268fedSTony Huang
9104e268fedSTony Huang ret = mmc_regulator_get_supply(mmc);
9114e268fedSTony Huang if (ret)
912dce6d8f9SWei Chen goto clk_disable;
9134e268fedSTony Huang
9144e268fedSTony Huang if (!mmc->ocr_avail)
9154e268fedSTony Huang mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
9164e268fedSTony Huang mmc->max_seg_size = SPMMC_MAX_BLK_COUNT * 512;
9174e268fedSTony Huang mmc->max_segs = SPMMC_MAX_DMA_MEMORY_SECTORS;
9184e268fedSTony Huang mmc->max_req_size = SPMMC_MAX_BLK_COUNT * 512;
9194e268fedSTony Huang mmc->max_blk_size = 512;
9204e268fedSTony Huang mmc->max_blk_count = SPMMC_MAX_BLK_COUNT;
9214e268fedSTony Huang
9224e268fedSTony Huang dev_set_drvdata(&pdev->dev, host);
9234e268fedSTony Huang spmmc_controller_init(host);
9244e268fedSTony Huang spmmc_set_sdmmc_mode(host);
9254e268fedSTony Huang host->tuning_info.enable_tuning = 1;
9264e268fedSTony Huang pm_runtime_set_active(&pdev->dev);
9274e268fedSTony Huang pm_runtime_enable(&pdev->dev);
928dce6d8f9SWei Chen ret = mmc_add_host(mmc);
929dce6d8f9SWei Chen if (ret)
930dce6d8f9SWei Chen goto pm_disable;
9314e268fedSTony Huang
932dce6d8f9SWei Chen return 0;
933dce6d8f9SWei Chen
934dce6d8f9SWei Chen pm_disable:
935dce6d8f9SWei Chen pm_runtime_disable(&pdev->dev);
936dce6d8f9SWei Chen
937dce6d8f9SWei Chen clk_disable:
938dce6d8f9SWei Chen clk_disable_unprepare(host->clk);
9394e268fedSTony Huang return ret;
9404e268fedSTony Huang }
9414e268fedSTony Huang
spmmc_drv_remove(struct platform_device * dev)942*3ed9c648SYangtao Li static void spmmc_drv_remove(struct platform_device *dev)
9434e268fedSTony Huang {
9444e268fedSTony Huang struct spmmc_host *host = platform_get_drvdata(dev);
9454e268fedSTony Huang
9464e268fedSTony Huang mmc_remove_host(host->mmc);
9474e268fedSTony Huang pm_runtime_get_sync(&dev->dev);
9484e268fedSTony Huang clk_disable_unprepare(host->clk);
9494e268fedSTony Huang pm_runtime_put_noidle(&dev->dev);
9504e268fedSTony Huang pm_runtime_disable(&dev->dev);
9514e268fedSTony Huang }
9524e268fedSTony Huang
spmmc_pm_runtime_suspend(struct device * dev)9534e268fedSTony Huang static int spmmc_pm_runtime_suspend(struct device *dev)
9544e268fedSTony Huang {
9554e268fedSTony Huang struct spmmc_host *host;
9564e268fedSTony Huang
9574e268fedSTony Huang host = dev_get_drvdata(dev);
9584e268fedSTony Huang clk_disable_unprepare(host->clk);
9594e268fedSTony Huang
9604e268fedSTony Huang return 0;
9614e268fedSTony Huang }
9624e268fedSTony Huang
spmmc_pm_runtime_resume(struct device * dev)9634e268fedSTony Huang static int spmmc_pm_runtime_resume(struct device *dev)
9644e268fedSTony Huang {
9654e268fedSTony Huang struct spmmc_host *host;
9664e268fedSTony Huang
9674e268fedSTony Huang host = dev_get_drvdata(dev);
9684e268fedSTony Huang
9694e268fedSTony Huang return clk_prepare_enable(host->clk);
9704e268fedSTony Huang }
9714e268fedSTony Huang
9724e268fedSTony Huang static DEFINE_RUNTIME_DEV_PM_OPS(spmmc_pm_ops, spmmc_pm_runtime_suspend,
9734e268fedSTony Huang spmmc_pm_runtime_resume, NULL);
9744e268fedSTony Huang
9754e268fedSTony Huang static const struct of_device_id spmmc_of_table[] = {
9764e268fedSTony Huang {
9774e268fedSTony Huang .compatible = "sunplus,sp7021-mmc",
9784e268fedSTony Huang },
9794e268fedSTony Huang {/* sentinel */}
9804e268fedSTony Huang };
9814e268fedSTony Huang MODULE_DEVICE_TABLE(of, spmmc_of_table);
9824e268fedSTony Huang
9834e268fedSTony Huang static struct platform_driver spmmc_driver = {
9844e268fedSTony Huang .probe = spmmc_drv_probe,
985*3ed9c648SYangtao Li .remove_new = spmmc_drv_remove,
9864e268fedSTony Huang .driver = {
9874e268fedSTony Huang .name = "spmmc",
9884e268fedSTony Huang .pm = pm_ptr(&spmmc_pm_ops),
9894e268fedSTony Huang .of_match_table = spmmc_of_table,
9904e268fedSTony Huang },
9914e268fedSTony Huang };
9924e268fedSTony Huang module_platform_driver(spmmc_driver);
9934e268fedSTony Huang
9944e268fedSTony Huang MODULE_AUTHOR("Tony Huang <tonyhuang.sunplus@gmail.com>");
9954e268fedSTony Huang MODULE_AUTHOR("Li-hao Kuo <lhjeff911@gmail.com>");
9964e268fedSTony Huang MODULE_DESCRIPTION("Sunplus MMC controller driver");
9974e268fedSTony Huang MODULE_LICENSE("GPL");
998