Lines Matching +full:12 +full:bit +full:- +full:clkdiv +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2010 Freescale Semiconductor.
30 #include "../common/pq-mds-pib.h"
52 {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
88 {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
109 {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
131 {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
139 /* UART1 is muxed with QE PortF bit [9-12].*/
140 {5, 12, 2, 0, 3}, /* UART1_SIN */
188 gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK; in board_early_init_f()
189 gur->plppar1 |= PLPPAR1_I2C2_VAL; in board_early_init_f()
190 gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK; in board_early_init_f()
191 gur->plpdir1 |= PLPDIR1_I2C2_VAL; in board_early_init_f()
205 * Remap Boot flash to caching-inhibited in board_early_init_r()
209 /* Flush d-cache and invalidate i-cache of any FLASH data */ in board_early_init_r()
238 out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); in fixed_sdram()
239 out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); in fixed_sdram()
240 out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); in fixed_sdram()
241 out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); in fixed_sdram()
242 out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
243 out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
244 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); in fixed_sdram()
245 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2); in fixed_sdram()
246 out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE); in fixed_sdram()
247 out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2); in fixed_sdram()
248 out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL); in fixed_sdram()
249 out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); in fixed_sdram()
250 out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); in fixed_sdram()
251 out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); in fixed_sdram()
252 out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); in fixed_sdram()
253 out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL); in fixed_sdram()
254 out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL); in fixed_sdram()
255 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2); in fixed_sdram()
257 out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN); in fixed_sdram()
258 out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS); in fixed_sdram()
259 out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE); in fixed_sdram()
263 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL); in fixed_sdram()
266 debug("DDR - 1st controller: memory initializing\n"); in fixed_sdram()
271 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) { in fixed_sdram()
290 uint clkdiv; in local_bus_init() local
294 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2; in local_bus_init()
296 out_be32(&gur->lbiuiplldcr1, 0x00078080); in local_bus_init()
297 if (clkdiv == 16) in local_bus_init()
298 out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0); in local_bus_init()
299 else if (clkdiv == 8) in local_bus_init()
300 out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0); in local_bus_init()
301 else if (clkdiv == 4) in local_bus_init()
302 out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0); in local_bus_init()
304 out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000); in local_bus_init()
332 * U-Boot anylonger).
349 hwconfig_subarg_cmp("esdhc", "mode", "4-bits"); in esdhc_disables_uart0()
359 int off = -1; in fdt_board_fixup_qe_uart()
382 idx = fdt_getprop(blob, off, "cell-index", &len); in fdt_board_fixup_qe_uart()
390 fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1); in fdt_board_fixup_qe_uart()
391 fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1); in fdt_board_fixup_qe_uart()
392 fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum)); in fdt_board_fixup_qe_uart()
419 clrsetbits_be32(&gur->plppar1, PLPPAR1_UART0_BIT_MASK, in board_mmc_init()
421 clrsetbits_be32(&gur->plpdir1, PLPDIR1_UART0_BIT_MASK, in board_mmc_init()
429 clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK, in board_mmc_init()
431 clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK, in board_mmc_init()
443 int off = -1; in fdt_board_fixup_esdhc()
455 off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c"); in fdt_board_fixup_esdhc()
459 idx = fdt_getprop(blob, off, "cell-index", &len); in fdt_board_fixup_esdhc()
470 if (hwconfig_subarg_cmp("esdhc", "mode", "4-bits")) { in fdt_board_fixup_esdhc()
471 off = fdt_node_offset_by_compatible(blob, -1, "fsl,esdhc"); in fdt_board_fixup_esdhc()
476 fdt_delprop(blob, off, "sdhci,1-bit-only"); in fdt_board_fixup_esdhc()
492 if (hwconfig_subarg_cmp("qe_usb", "mode", "peripheral")) { in fdt_board_fixup_qe_usb()
495 do_fixup_by_compat(blob, "fsl,mpc8569-qe-usb", "mode", in fdt_board_fixup_qe_usb()
525 /* fixup device tree for supporting rmii mode */ in ft_board_setup()
526 nodeoff = -1; in ft_board_setup()
529 err = fdt_setprop_string(blob, nodeoff, "tx-clock-name", in ft_board_setup()
532 printf("WARNING: could not set tx-clock-name %s.\n", in ft_board_setup()
541 printf("WARNING: could not set phy-connection-type " in ft_board_setup()
546 index = fdt_getprop(blob, nodeoff, "cell-index", 0); in ft_board_setup()
548 printf("WARNING: could not get cell-index of ucc\n"); in ft_board_setup()
552 ph = fdt_getprop(blob, nodeoff, "phy-handle", 0); in ft_board_setup()
554 printf("WARNING: could not get phy-handle of ucc\n"); in ft_board_setup()
569 printf("WARNING: could not set reg for phy-handle " in ft_board_setup()