1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
27d2be074SHaavard Skinnemoen /*
37d2be074SHaavard Skinnemoen * Atmel MultiMedia Card Interface driver
47d2be074SHaavard Skinnemoen *
57d2be074SHaavard Skinnemoen * Copyright (C) 2004-2008 Atmel Corporation
67d2be074SHaavard Skinnemoen */
77d2be074SHaavard Skinnemoen #include <linux/blkdev.h>
87d2be074SHaavard Skinnemoen #include <linux/clk.h>
9deec9ae3SHaavard Skinnemoen #include <linux/debugfs.h>
107d2be074SHaavard Skinnemoen #include <linux/device.h>
1165e8b083SHaavard Skinnemoen #include <linux/dmaengine.h>
1265e8b083SHaavard Skinnemoen #include <linux/dma-mapping.h>
13fbfca4b8SBen Nizette #include <linux/err.h>
147d2be074SHaavard Skinnemoen #include <linux/init.h>
157d2be074SHaavard Skinnemoen #include <linux/interrupt.h>
167bca646eSPramod Gurav #include <linux/io.h>
177d2be074SHaavard Skinnemoen #include <linux/ioport.h>
187d2be074SHaavard Skinnemoen #include <linux/module.h>
19e919fd20SLudovic Desroches #include <linux/of.h>
20ce6e9472SBalamanikandan Gunasundar #include <linux/irq.h>
21ce6e9472SBalamanikandan Gunasundar #include <linux/gpio/consumer.h>
227d2be074SHaavard Skinnemoen #include <linux/platform_device.h>
237d2be074SHaavard Skinnemoen #include <linux/scatterlist.h>
24deec9ae3SHaavard Skinnemoen #include <linux/seq_file.h>
255a0e3ad6STejun Heo #include <linux/slab.h>
26deec9ae3SHaavard Skinnemoen #include <linux/stat.h>
27e2b35f3dSViresh Kumar #include <linux/types.h>
287d2be074SHaavard Skinnemoen
297d2be074SHaavard Skinnemoen #include <linux/mmc/host.h>
302f1d7918SNicolas Ferre #include <linux/mmc/sdio.h>
312635d1baSNicolas Ferre
32796211b7SLudovic Desroches #include <linux/atmel_pdc.h>
33ae552ab0SWenyou Yang #include <linux/pm.h>
34ae552ab0SWenyou Yang #include <linux/pm_runtime.h>
35b5b64fa6SWenyou Yang #include <linux/pinctrl/consumer.h>
367d2be074SHaavard Skinnemoen
37bf614c7aSArnd Bergmann #include <asm/cacheflush.h>
387d2be074SHaavard Skinnemoen #include <asm/io.h>
397d2be074SHaavard Skinnemoen #include <asm/unaligned.h>
407d2be074SHaavard Skinnemoen
41d2c6d518SBalamanikandan Gunasundar #define ATMCI_MAX_NR_SLOTS 2
42d2c6d518SBalamanikandan Gunasundar
43ec8fc9cfSludovic.desroches@atmel.com /*
44ef4b160fSAndy Shevchenko * Superset of MCI IP registers integrated in Atmel AT91 Processor
45ec8fc9cfSludovic.desroches@atmel.com * Registers and bitfields marked with [2] are only available in MCI2
46ec8fc9cfSludovic.desroches@atmel.com */
47ec8fc9cfSludovic.desroches@atmel.com
48ec8fc9cfSludovic.desroches@atmel.com /* MCI Register Definitions */
49ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CR 0x0000 /* Control */
50ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CR_MCIEN BIT(0) /* MCI Enable */
51ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CR_MCIDIS BIT(1) /* MCI Disable */
52ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CR_PWSEN BIT(2) /* Power Save Enable */
53ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CR_PWSDIS BIT(3) /* Power Save Disable */
54ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CR_SWRST BIT(7) /* Software Reset */
55ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_MR 0x0004 /* Mode */
56ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_MR_CLKDIV(x) ((x) << 0) /* Clock Divider */
57ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_MR_PWSDIV(x) ((x) << 8) /* Power Saving Divider */
58ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_MR_RDPROOF BIT(11) /* Read Proof */
59ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_MR_WRPROOF BIT(12) /* Write Proof */
60ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_MR_PDCFBYTE BIT(13) /* Force Byte Transfer */
61ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_MR_PDCPADV BIT(14) /* Padding Value */
62ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_MR_PDCMODE BIT(15) /* PDC-oriented Mode */
63ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_MR_CLKODD(x) ((x) << 16) /* LSB of Clock Divider */
64ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_DTOR 0x0008 /* Data Timeout */
65ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_DTOCYC(x) ((x) << 0) /* Data Timeout Cycles */
66ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_DTOMUL(x) ((x) << 4) /* Data Timeout Multiplier */
67ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_SDCR 0x000c /* SD Card / SDIO */
68ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_SDCSEL_SLOT_A (0 << 0) /* Select SD slot A */
69ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_SDCSEL_SLOT_B (1 << 0) /* Select SD slot A */
70ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_SDCSEL_MASK (3 << 0)
71ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_SDCBUS_1BIT (0 << 6) /* 1-bit data bus */
72ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_SDCBUS_4BIT (2 << 6) /* 4-bit data bus */
73ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_SDCBUS_8BIT (3 << 6) /* 8-bit data bus[2] */
74ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_SDCBUS_MASK (3 << 6)
75ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_ARGR 0x0010 /* Command Argument */
76ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CMDR 0x0014 /* Command */
77ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CMDR_CMDNB(x) ((x) << 0) /* Command Opcode */
78ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CMDR_RSPTYP_NONE (0 << 6) /* No response */
79ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CMDR_RSPTYP_48BIT (1 << 6) /* 48-bit response */
80ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CMDR_RSPTYP_136BIT (2 << 6) /* 136-bit response */
81ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CMDR_SPCMD_INIT (1 << 8) /* Initialization command */
82ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CMDR_SPCMD_SYNC (2 << 8) /* Synchronized command */
83ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CMDR_SPCMD_INT (4 << 8) /* Interrupt command */
84ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CMDR_SPCMD_INTRESP (5 << 8) /* Interrupt response */
85ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CMDR_OPDCMD (1 << 11) /* Open Drain */
86ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CMDR_MAXLAT_5CYC (0 << 12) /* Max latency 5 cycles */
87ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CMDR_MAXLAT_64CYC (1 << 12) /* Max latency 64 cycles */
88ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CMDR_START_XFER (1 << 16) /* Start data transfer */
89ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CMDR_STOP_XFER (2 << 16) /* Stop data transfer */
90ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CMDR_TRDIR_WRITE (0 << 18) /* Write data */
91ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CMDR_TRDIR_READ (1 << 18) /* Read data */
92ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CMDR_BLOCK (0 << 19) /* Single-block transfer */
93ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CMDR_MULTI_BLOCK (1 << 19) /* Multi-block transfer */
94ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CMDR_STREAM (2 << 19) /* MMC Stream transfer */
95ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CMDR_SDIO_BYTE (4 << 19) /* SDIO Byte transfer */
96ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CMDR_SDIO_BLOCK (5 << 19) /* SDIO Block transfer */
97ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CMDR_SDIO_SUSPEND (1 << 24) /* SDIO Suspend Command */
98ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CMDR_SDIO_RESUME (2 << 24) /* SDIO Resume Command */
99ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_BLKR 0x0018 /* Block */
100ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_BCNT(x) ((x) << 0) /* Data Block Count */
101ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_BLKLEN(x) ((x) << 16) /* Data Block Length */
102ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CSTOR 0x001c /* Completion Signal Timeout[2] */
103ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CSTOCYC(x) ((x) << 0) /* CST cycles */
104ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CSTOMUL(x) ((x) << 4) /* CST multiplier */
105ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_RSPR 0x0020 /* Response 0 */
106ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_RSPR1 0x0024 /* Response 1 */
107ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_RSPR2 0x0028 /* Response 2 */
108ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_RSPR3 0x002c /* Response 3 */
109ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_RDR 0x0030 /* Receive Data */
110ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_TDR 0x0034 /* Transmit Data */
111ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_SR 0x0040 /* Status */
112ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_IER 0x0044 /* Interrupt Enable */
113ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_IDR 0x0048 /* Interrupt Disable */
114ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_IMR 0x004c /* Interrupt Mask */
115ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CMDRDY BIT(0) /* Command Ready */
116ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_RXRDY BIT(1) /* Receiver Ready */
117ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_TXRDY BIT(2) /* Transmitter Ready */
118ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_BLKE BIT(3) /* Data Block Ended */
119ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_DTIP BIT(4) /* Data Transfer In Progress */
120ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_NOTBUSY BIT(5) /* Data Not Busy */
121ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_ENDRX BIT(6) /* End of RX Buffer */
122ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_ENDTX BIT(7) /* End of TX Buffer */
123ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_SDIOIRQA BIT(8) /* SDIO IRQ in slot A */
124ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_SDIOIRQB BIT(9) /* SDIO IRQ in slot B */
125ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_SDIOWAIT BIT(12) /* SDIO Read Wait Operation Status */
126ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CSRCV BIT(13) /* CE-ATA Completion Signal Received */
127ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_RXBUFF BIT(14) /* RX Buffer Full */
128ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_TXBUFE BIT(15) /* TX Buffer Empty */
129ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_RINDE BIT(16) /* Response Index Error */
130ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_RDIRE BIT(17) /* Response Direction Error */
131ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_RCRCE BIT(18) /* Response CRC Error */
132ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_RENDE BIT(19) /* Response End Bit Error */
133ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_RTOE BIT(20) /* Response Time-Out Error */
134ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_DCRCE BIT(21) /* Data CRC Error */
135ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_DTOE BIT(22) /* Data Time-Out Error */
136ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CSTOE BIT(23) /* Completion Signal Time-out Error */
137ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_BLKOVRE BIT(24) /* DMA Block Overrun Error */
138ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_DMADONE BIT(25) /* DMA Transfer Done */
139ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_FIFOEMPTY BIT(26) /* FIFO Empty Flag */
140ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_XFRDONE BIT(27) /* Transfer Done Flag */
141ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_ACKRCV BIT(28) /* Boot Operation Acknowledge Received */
142ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_ACKRCVE BIT(29) /* Boot Operation Acknowledge Error */
143ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_OVRE BIT(30) /* RX Overrun Error */
144ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_UNRE BIT(31) /* TX Underrun Error */
145ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_DMA 0x0050 /* DMA Configuration[2] */
146ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_DMA_OFFSET(x) ((x) << 0) /* DMA Write Buffer Offset */
147ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_DMA_CHKSIZE(x) ((x) << 4) /* DMA Channel Read and Write Chunk Size */
148ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_DMAEN BIT(8) /* DMA Hardware Handshaking Enable */
149ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CFG 0x0054 /* Configuration[2] */
150ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CFG_FIFOMODE_1DATA BIT(0) /* MCI Internal FIFO control mode */
151ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CFG_FERRCTRL_COR BIT(4) /* Flow Error flag reset control mode */
152ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CFG_HSMODE BIT(8) /* High Speed Mode */
153ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_CFG_LSYNC BIT(12) /* Synchronize on the last block */
154ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_WPMR 0x00e4 /* Write Protection Mode[2] */
155ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_WP_EN BIT(0) /* WP Enable */
156ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_WP_KEY (0x4d4349 << 8) /* WP Key */
157ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_WPSR 0x00e8 /* Write Protection Status[2] */
158ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_GET_WP_VS(x) ((x) & 0x0f)
159ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_GET_WP_VSRC(x) (((x) >> 8) & 0xffff)
160ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_VERSION 0x00FC /* Version */
161ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_FIFO_APERTURE 0x0200 /* FIFO Aperture[2] */
162ec8fc9cfSludovic.desroches@atmel.com
163ec8fc9cfSludovic.desroches@atmel.com /* This is not including the FIFO Aperture on MCI2 */
164ec8fc9cfSludovic.desroches@atmel.com #define ATMCI_REGS_SIZE 0x100
165ec8fc9cfSludovic.desroches@atmel.com
166ec8fc9cfSludovic.desroches@atmel.com /* Register access macros */
167ec8fc9cfSludovic.desroches@atmel.com #define atmci_readl(port, reg) \
168ec8fc9cfSludovic.desroches@atmel.com __raw_readl((port)->regs + reg)
169ec8fc9cfSludovic.desroches@atmel.com #define atmci_writel(port, reg, value) \
170ec8fc9cfSludovic.desroches@atmel.com __raw_writel((value), (port)->regs + reg)
171ec8fc9cfSludovic.desroches@atmel.com
172ab5d94f7SUlf Hansson #define ATMCI_CMD_TIMEOUT_MS 2000
173ae552ab0SWenyou Yang #define AUTOSUSPEND_DELAY 50
174ae552ab0SWenyou Yang
1752c96a293SLudovic Desroches #define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
17665e8b083SHaavard Skinnemoen #define ATMCI_DMA_THRESHOLD 16
1777d2be074SHaavard Skinnemoen
1787d2be074SHaavard Skinnemoen enum {
179f5177547SLudovic Desroches EVENT_CMD_RDY = 0,
1807d2be074SHaavard Skinnemoen EVENT_XFER_COMPLETE,
181f5177547SLudovic Desroches EVENT_NOTBUSY,
182c06ad258SHaavard Skinnemoen EVENT_DATA_ERROR,
183c06ad258SHaavard Skinnemoen };
184c06ad258SHaavard Skinnemoen
185c06ad258SHaavard Skinnemoen enum atmel_mci_state {
186965ebf33SHaavard Skinnemoen STATE_IDLE = 0,
187965ebf33SHaavard Skinnemoen STATE_SENDING_CMD,
188f5177547SLudovic Desroches STATE_DATA_XFER,
189f5177547SLudovic Desroches STATE_WAITING_NOTBUSY,
190c06ad258SHaavard Skinnemoen STATE_SENDING_STOP,
191f5177547SLudovic Desroches STATE_END_REQUEST,
1927d2be074SHaavard Skinnemoen };
1937d2be074SHaavard Skinnemoen
194796211b7SLudovic Desroches enum atmci_xfer_dir {
195796211b7SLudovic Desroches XFER_RECEIVE = 0,
196796211b7SLudovic Desroches XFER_TRANSMIT,
197796211b7SLudovic Desroches };
198796211b7SLudovic Desroches
199796211b7SLudovic Desroches enum atmci_pdc_buf {
200796211b7SLudovic Desroches PDC_FIRST_BUF = 0,
201796211b7SLudovic Desroches PDC_SECOND_BUF,
202796211b7SLudovic Desroches };
203796211b7SLudovic Desroches
204d2c6d518SBalamanikandan Gunasundar /**
205d2c6d518SBalamanikandan Gunasundar * struct mci_slot_pdata - board-specific per-slot configuration
206d2c6d518SBalamanikandan Gunasundar * @bus_width: Number of data lines wired up the slot
207d2c6d518SBalamanikandan Gunasundar * @detect_pin: GPIO pin wired to the card detect switch
208d2c6d518SBalamanikandan Gunasundar * @wp_pin: GPIO pin wired to the write protect sensor
209d2c6d518SBalamanikandan Gunasundar * @non_removable: The slot is not removable, only detect once
210d2c6d518SBalamanikandan Gunasundar *
211d2c6d518SBalamanikandan Gunasundar * If a given slot is not present on the board, @bus_width should be
212d2c6d518SBalamanikandan Gunasundar * set to 0. The other fields are ignored in this case.
213d2c6d518SBalamanikandan Gunasundar *
214d2c6d518SBalamanikandan Gunasundar * Any pins that aren't available should be set to a negative value.
215d2c6d518SBalamanikandan Gunasundar *
216d2c6d518SBalamanikandan Gunasundar * Note that support for multiple slots is experimental -- some cards
217d2c6d518SBalamanikandan Gunasundar * might get upset if we don't get the clock management exactly right.
218d2c6d518SBalamanikandan Gunasundar * But in most cases, it should work just fine.
219d2c6d518SBalamanikandan Gunasundar */
220d2c6d518SBalamanikandan Gunasundar struct mci_slot_pdata {
221d2c6d518SBalamanikandan Gunasundar unsigned int bus_width;
222d2c6d518SBalamanikandan Gunasundar struct gpio_desc *detect_pin;
223d2c6d518SBalamanikandan Gunasundar struct gpio_desc *wp_pin;
224d2c6d518SBalamanikandan Gunasundar bool non_removable;
225d2c6d518SBalamanikandan Gunasundar };
226d2c6d518SBalamanikandan Gunasundar
227d2c6d518SBalamanikandan Gunasundar /**
228d2c6d518SBalamanikandan Gunasundar * struct mci_platform_data - board-specific MMC/SDcard configuration
229d2c6d518SBalamanikandan Gunasundar * @dma_slave: DMA slave interface to use in data transfers.
230d2c6d518SBalamanikandan Gunasundar * @slot: Per-slot configuration data.
231d2c6d518SBalamanikandan Gunasundar */
232d2c6d518SBalamanikandan Gunasundar struct mci_platform_data {
233d2c6d518SBalamanikandan Gunasundar void *dma_slave;
234d2c6d518SBalamanikandan Gunasundar dma_filter_fn dma_filter;
235d2c6d518SBalamanikandan Gunasundar struct mci_slot_pdata slot[ATMCI_MAX_NR_SLOTS];
236d2c6d518SBalamanikandan Gunasundar };
237d2c6d518SBalamanikandan Gunasundar
238796211b7SLudovic Desroches struct atmel_mci_caps {
239ccdfe612SHein_Tibosch bool has_dma_conf_reg;
240796211b7SLudovic Desroches bool has_pdc;
241796211b7SLudovic Desroches bool has_cfg_reg;
242796211b7SLudovic Desroches bool has_cstor_reg;
243796211b7SLudovic Desroches bool has_highspeed;
244796211b7SLudovic Desroches bool has_rwproof;
245faf8180bSLudovic Desroches bool has_odd_clk_div;
24624011f34SLudovic Desroches bool has_bad_data_ordering;
24724011f34SLudovic Desroches bool need_reset_after_xfer;
24824011f34SLudovic Desroches bool need_blksz_mul_4;
249077d4073SLudovic Desroches bool need_notbusy_for_read_ops;
250796211b7SLudovic Desroches };
251796211b7SLudovic Desroches
25265e8b083SHaavard Skinnemoen struct atmel_mci_dma {
25365e8b083SHaavard Skinnemoen struct dma_chan *chan;
25465e8b083SHaavard Skinnemoen struct dma_async_tx_descriptor *data_desc;
25565e8b083SHaavard Skinnemoen };
25665e8b083SHaavard Skinnemoen
257965ebf33SHaavard Skinnemoen /**
258965ebf33SHaavard Skinnemoen * struct atmel_mci - MMC controller state shared between all slots
259965ebf33SHaavard Skinnemoen * @lock: Spinlock protecting the queue and associated data.
260965ebf33SHaavard Skinnemoen * @regs: Pointer to MMIO registers.
261796211b7SLudovic Desroches * @sg: Scatterlist entry currently being processed by PIO or PDC code.
262f51874b7SLee Jones * @sg_len: Size of the scatterlist
263965ebf33SHaavard Skinnemoen * @pio_offset: Offset into the current scatterlist entry.
2647a90dcc2SLudovic Desroches * @buffer: Buffer used if we don't have the r/w proof capability. We
2657a90dcc2SLudovic Desroches * don't have the time to switch pdc buffers so we have to use only
2667a90dcc2SLudovic Desroches * one buffer for the full transaction.
2677a90dcc2SLudovic Desroches * @buf_size: size of the buffer.
268f51874b7SLee Jones * @buf_phys_addr: buffer address needed for pdc.
269965ebf33SHaavard Skinnemoen * @cur_slot: The slot which is currently using the controller.
270965ebf33SHaavard Skinnemoen * @mrq: The request currently being processed on @cur_slot,
271965ebf33SHaavard Skinnemoen * or NULL if the controller is idle.
272965ebf33SHaavard Skinnemoen * @cmd: The command currently being sent to the card, or NULL.
273965ebf33SHaavard Skinnemoen * @data: The data currently being transferred, or NULL if no data
274965ebf33SHaavard Skinnemoen * transfer is in progress.
275796211b7SLudovic Desroches * @data_size: just data->blocks * data->blksz.
27665e8b083SHaavard Skinnemoen * @dma: DMA client state.
27765e8b083SHaavard Skinnemoen * @data_chan: DMA channel being used for the current data transfer.
278f51874b7SLee Jones * @dma_conf: Configuration for the DMA slave
279965ebf33SHaavard Skinnemoen * @cmd_status: Snapshot of SR taken upon completion of the current
280965ebf33SHaavard Skinnemoen * command. Only valid when EVENT_CMD_COMPLETE is pending.
281965ebf33SHaavard Skinnemoen * @data_status: Snapshot of SR taken upon completion of the current
282965ebf33SHaavard Skinnemoen * data transfer. Only valid when EVENT_DATA_COMPLETE or
283965ebf33SHaavard Skinnemoen * EVENT_DATA_ERROR is pending.
284965ebf33SHaavard Skinnemoen * @stop_cmdr: Value to be loaded into CMDR when the stop command is
285965ebf33SHaavard Skinnemoen * to be sent.
286965ebf33SHaavard Skinnemoen * @tasklet: Tasklet running the request state machine.
287965ebf33SHaavard Skinnemoen * @pending_events: Bitmask of events flagged by the interrupt handler
288965ebf33SHaavard Skinnemoen * to be processed by the tasklet.
289965ebf33SHaavard Skinnemoen * @completed_events: Bitmask of events which the state machine has
290965ebf33SHaavard Skinnemoen * processed.
291965ebf33SHaavard Skinnemoen * @state: Tasklet state.
292965ebf33SHaavard Skinnemoen * @queue: List of slots waiting for access to the controller.
293965ebf33SHaavard Skinnemoen * @need_clock_update: Update the clock rate before the next request.
294965ebf33SHaavard Skinnemoen * @need_reset: Reset controller before next request.
29524011f34SLudovic Desroches * @timer: Timer to balance the data timeout error flag which cannot rise.
296965ebf33SHaavard Skinnemoen * @mode_reg: Value of the MR register.
29774791a2dSNicolas Ferre * @cfg_reg: Value of the CFG register.
298965ebf33SHaavard Skinnemoen * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
299965ebf33SHaavard Skinnemoen * rate and timeout calculations.
300965ebf33SHaavard Skinnemoen * @mapbase: Physical address of the MMIO registers.
301965ebf33SHaavard Skinnemoen * @mck: The peripheral bus clock hooked up to the MMC controller.
302965ebf33SHaavard Skinnemoen * @pdev: Platform device associated with the MMC controller.
303965ebf33SHaavard Skinnemoen * @slot: Slots sharing this MMC controller.
304796211b7SLudovic Desroches * @caps: MCI capabilities depending on MCI version.
305796211b7SLudovic Desroches * @prepare_data: function to setup MCI before data transfer which
306796211b7SLudovic Desroches * depends on MCI capabilities.
307796211b7SLudovic Desroches * @submit_data: function to start data transfer which depends on MCI
308796211b7SLudovic Desroches * capabilities.
309796211b7SLudovic Desroches * @stop_transfer: function to stop data transfer which depends on MCI
310796211b7SLudovic Desroches * capabilities.
311965ebf33SHaavard Skinnemoen *
312965ebf33SHaavard Skinnemoen * Locking
313965ebf33SHaavard Skinnemoen * =======
314965ebf33SHaavard Skinnemoen *
315965ebf33SHaavard Skinnemoen * @lock is a softirq-safe spinlock protecting @queue as well as
316965ebf33SHaavard Skinnemoen * @cur_slot, @mrq and @state. These must always be updated
317965ebf33SHaavard Skinnemoen * at the same time while holding @lock.
318965ebf33SHaavard Skinnemoen *
319965ebf33SHaavard Skinnemoen * @lock also protects mode_reg and need_clock_update since these are
320965ebf33SHaavard Skinnemoen * used to synchronize mode register updates with the queue
321965ebf33SHaavard Skinnemoen * processing.
322965ebf33SHaavard Skinnemoen *
323965ebf33SHaavard Skinnemoen * The @mrq field of struct atmel_mci_slot is also protected by @lock,
324965ebf33SHaavard Skinnemoen * and must always be written at the same time as the slot is added to
325965ebf33SHaavard Skinnemoen * @queue.
326965ebf33SHaavard Skinnemoen *
327965ebf33SHaavard Skinnemoen * @pending_events and @completed_events are accessed using atomic bit
328965ebf33SHaavard Skinnemoen * operations, so they don't need any locking.
329965ebf33SHaavard Skinnemoen *
330965ebf33SHaavard Skinnemoen * None of the fields touched by the interrupt handler need any
331965ebf33SHaavard Skinnemoen * locking. However, ordering is important: Before EVENT_DATA_ERROR or
332965ebf33SHaavard Skinnemoen * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
333965ebf33SHaavard Skinnemoen * interrupts must be disabled and @data_status updated with a
334965ebf33SHaavard Skinnemoen * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
33525985edcSLucas De Marchi * CMDRDY interrupt must be disabled and @cmd_status updated with a
336965ebf33SHaavard Skinnemoen * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
337965ebf33SHaavard Skinnemoen * bytes_xfered field of @data must be written. This is ensured by
338965ebf33SHaavard Skinnemoen * using barriers.
339965ebf33SHaavard Skinnemoen */
3407d2be074SHaavard Skinnemoen struct atmel_mci {
341965ebf33SHaavard Skinnemoen spinlock_t lock;
3427d2be074SHaavard Skinnemoen void __iomem *regs;
3437d2be074SHaavard Skinnemoen
3447d2be074SHaavard Skinnemoen struct scatterlist *sg;
345bdbc5d0cSTerry Barnaby unsigned int sg_len;
3467d2be074SHaavard Skinnemoen unsigned int pio_offset;
3477a90dcc2SLudovic Desroches unsigned int *buffer;
3487a90dcc2SLudovic Desroches unsigned int buf_size;
3497a90dcc2SLudovic Desroches dma_addr_t buf_phys_addr;
3507d2be074SHaavard Skinnemoen
351965ebf33SHaavard Skinnemoen struct atmel_mci_slot *cur_slot;
3527d2be074SHaavard Skinnemoen struct mmc_request *mrq;
3537d2be074SHaavard Skinnemoen struct mmc_command *cmd;
3547d2be074SHaavard Skinnemoen struct mmc_data *data;
355796211b7SLudovic Desroches unsigned int data_size;
3567d2be074SHaavard Skinnemoen
35765e8b083SHaavard Skinnemoen struct atmel_mci_dma dma;
35865e8b083SHaavard Skinnemoen struct dma_chan *data_chan;
359e2b35f3dSViresh Kumar struct dma_slave_config dma_conf;
36065e8b083SHaavard Skinnemoen
3617d2be074SHaavard Skinnemoen u32 cmd_status;
3627d2be074SHaavard Skinnemoen u32 data_status;
3637d2be074SHaavard Skinnemoen u32 stop_cmdr;
3647d2be074SHaavard Skinnemoen
3657d2be074SHaavard Skinnemoen struct tasklet_struct tasklet;
3667d2be074SHaavard Skinnemoen unsigned long pending_events;
3677d2be074SHaavard Skinnemoen unsigned long completed_events;
368c06ad258SHaavard Skinnemoen enum atmel_mci_state state;
369965ebf33SHaavard Skinnemoen struct list_head queue;
3707d2be074SHaavard Skinnemoen
371965ebf33SHaavard Skinnemoen bool need_clock_update;
372965ebf33SHaavard Skinnemoen bool need_reset;
37324011f34SLudovic Desroches struct timer_list timer;
374965ebf33SHaavard Skinnemoen u32 mode_reg;
37574791a2dSNicolas Ferre u32 cfg_reg;
3767d2be074SHaavard Skinnemoen unsigned long bus_hz;
3777d2be074SHaavard Skinnemoen unsigned long mapbase;
3787d2be074SHaavard Skinnemoen struct clk *mck;
3797d2be074SHaavard Skinnemoen struct platform_device *pdev;
380965ebf33SHaavard Skinnemoen
3812c96a293SLudovic Desroches struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS];
382796211b7SLudovic Desroches
383796211b7SLudovic Desroches struct atmel_mci_caps caps;
384796211b7SLudovic Desroches
385796211b7SLudovic Desroches u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
386796211b7SLudovic Desroches void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
387796211b7SLudovic Desroches void (*stop_transfer)(struct atmel_mci *host);
388965ebf33SHaavard Skinnemoen };
389965ebf33SHaavard Skinnemoen
390965ebf33SHaavard Skinnemoen /**
391965ebf33SHaavard Skinnemoen * struct atmel_mci_slot - MMC slot state
392965ebf33SHaavard Skinnemoen * @mmc: The mmc_host representing this slot.
393965ebf33SHaavard Skinnemoen * @host: The MMC controller this slot is using.
394965ebf33SHaavard Skinnemoen * @sdc_reg: Value of SDCR to be written before using this slot.
39588ff82edSAnders Grahn * @sdio_irq: SDIO irq mask for this slot.
396965ebf33SHaavard Skinnemoen * @mrq: mmc_request currently being processed or waiting to be
397965ebf33SHaavard Skinnemoen * processed, or NULL when the slot is idle.
398965ebf33SHaavard Skinnemoen * @queue_node: List node for placing this node in the @queue list of
399965ebf33SHaavard Skinnemoen * &struct atmel_mci.
400965ebf33SHaavard Skinnemoen * @clock: Clock rate configured by set_ios(). Protected by host->lock.
401965ebf33SHaavard Skinnemoen * @flags: Random state bits associated with the slot.
402965ebf33SHaavard Skinnemoen * @detect_pin: GPIO pin used for card detection, or negative if not
403965ebf33SHaavard Skinnemoen * available.
404965ebf33SHaavard Skinnemoen * @wp_pin: GPIO pin used for card write protect sending, or negative
405965ebf33SHaavard Skinnemoen * if not available.
406965ebf33SHaavard Skinnemoen * @detect_timer: Timer used for debouncing @detect_pin interrupts.
407965ebf33SHaavard Skinnemoen */
408965ebf33SHaavard Skinnemoen struct atmel_mci_slot {
409965ebf33SHaavard Skinnemoen struct mmc_host *mmc;
410965ebf33SHaavard Skinnemoen struct atmel_mci *host;
411965ebf33SHaavard Skinnemoen
412965ebf33SHaavard Skinnemoen u32 sdc_reg;
41388ff82edSAnders Grahn u32 sdio_irq;
414965ebf33SHaavard Skinnemoen
415965ebf33SHaavard Skinnemoen struct mmc_request *mrq;
416965ebf33SHaavard Skinnemoen struct list_head queue_node;
417965ebf33SHaavard Skinnemoen
418965ebf33SHaavard Skinnemoen unsigned int clock;
419965ebf33SHaavard Skinnemoen unsigned long flags;
420965ebf33SHaavard Skinnemoen #define ATMCI_CARD_PRESENT 0
421965ebf33SHaavard Skinnemoen #define ATMCI_CARD_NEED_INIT 1
422965ebf33SHaavard Skinnemoen #define ATMCI_SHUTDOWN 2
423965ebf33SHaavard Skinnemoen
424ce6e9472SBalamanikandan Gunasundar struct gpio_desc *detect_pin;
425ce6e9472SBalamanikandan Gunasundar struct gpio_desc *wp_pin;
426965ebf33SHaavard Skinnemoen
427965ebf33SHaavard Skinnemoen struct timer_list detect_timer;
4287d2be074SHaavard Skinnemoen };
4297d2be074SHaavard Skinnemoen
4307d2be074SHaavard Skinnemoen #define atmci_test_and_clear_pending(host, event) \
4317d2be074SHaavard Skinnemoen test_and_clear_bit(event, &host->pending_events)
4327d2be074SHaavard Skinnemoen #define atmci_set_completed(host, event) \
4337d2be074SHaavard Skinnemoen set_bit(event, &host->completed_events)
4347d2be074SHaavard Skinnemoen #define atmci_set_pending(host, event) \
4357d2be074SHaavard Skinnemoen set_bit(event, &host->pending_events)
4367d2be074SHaavard Skinnemoen
437deec9ae3SHaavard Skinnemoen /*
438deec9ae3SHaavard Skinnemoen * The debugfs stuff below is mostly optimized away when
439deec9ae3SHaavard Skinnemoen * CONFIG_DEBUG_FS is not set.
440deec9ae3SHaavard Skinnemoen */
atmci_req_show(struct seq_file * s,void * v)441deec9ae3SHaavard Skinnemoen static int atmci_req_show(struct seq_file *s, void *v)
442deec9ae3SHaavard Skinnemoen {
443965ebf33SHaavard Skinnemoen struct atmel_mci_slot *slot = s->private;
444965ebf33SHaavard Skinnemoen struct mmc_request *mrq;
445deec9ae3SHaavard Skinnemoen struct mmc_command *cmd;
446deec9ae3SHaavard Skinnemoen struct mmc_command *stop;
447deec9ae3SHaavard Skinnemoen struct mmc_data *data;
448deec9ae3SHaavard Skinnemoen
449deec9ae3SHaavard Skinnemoen /* Make sure we get a consistent snapshot */
450965ebf33SHaavard Skinnemoen spin_lock_bh(&slot->host->lock);
451965ebf33SHaavard Skinnemoen mrq = slot->mrq;
452deec9ae3SHaavard Skinnemoen
453deec9ae3SHaavard Skinnemoen if (mrq) {
454deec9ae3SHaavard Skinnemoen cmd = mrq->cmd;
455deec9ae3SHaavard Skinnemoen data = mrq->data;
456deec9ae3SHaavard Skinnemoen stop = mrq->stop;
457deec9ae3SHaavard Skinnemoen
458deec9ae3SHaavard Skinnemoen if (cmd)
459deec9ae3SHaavard Skinnemoen seq_printf(s,
460deec9ae3SHaavard Skinnemoen "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
461deec9ae3SHaavard Skinnemoen cmd->opcode, cmd->arg, cmd->flags,
462deec9ae3SHaavard Skinnemoen cmd->resp[0], cmd->resp[1], cmd->resp[2],
463d586ebbbSNicolas Ferre cmd->resp[3], cmd->error);
464deec9ae3SHaavard Skinnemoen if (data)
465deec9ae3SHaavard Skinnemoen seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
466deec9ae3SHaavard Skinnemoen data->bytes_xfered, data->blocks,
467deec9ae3SHaavard Skinnemoen data->blksz, data->flags, data->error);
468deec9ae3SHaavard Skinnemoen if (stop)
469deec9ae3SHaavard Skinnemoen seq_printf(s,
470deec9ae3SHaavard Skinnemoen "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
471deec9ae3SHaavard Skinnemoen stop->opcode, stop->arg, stop->flags,
472deec9ae3SHaavard Skinnemoen stop->resp[0], stop->resp[1], stop->resp[2],
473d586ebbbSNicolas Ferre stop->resp[3], stop->error);
474deec9ae3SHaavard Skinnemoen }
475deec9ae3SHaavard Skinnemoen
476965ebf33SHaavard Skinnemoen spin_unlock_bh(&slot->host->lock);
477deec9ae3SHaavard Skinnemoen
478deec9ae3SHaavard Skinnemoen return 0;
479deec9ae3SHaavard Skinnemoen }
480deec9ae3SHaavard Skinnemoen
4818ceb2943SYangtao Li DEFINE_SHOW_ATTRIBUTE(atmci_req);
482deec9ae3SHaavard Skinnemoen
atmci_show_status_reg(struct seq_file * s,const char * regname,u32 value)483deec9ae3SHaavard Skinnemoen static void atmci_show_status_reg(struct seq_file *s,
484deec9ae3SHaavard Skinnemoen const char *regname, u32 value)
485deec9ae3SHaavard Skinnemoen {
486deec9ae3SHaavard Skinnemoen static const char *sr_bit[] = {
487deec9ae3SHaavard Skinnemoen [0] = "CMDRDY",
488deec9ae3SHaavard Skinnemoen [1] = "RXRDY",
489deec9ae3SHaavard Skinnemoen [2] = "TXRDY",
490deec9ae3SHaavard Skinnemoen [3] = "BLKE",
491deec9ae3SHaavard Skinnemoen [4] = "DTIP",
492deec9ae3SHaavard Skinnemoen [5] = "NOTBUSY",
49304d699c3SRob Emanuele [6] = "ENDRX",
49404d699c3SRob Emanuele [7] = "ENDTX",
495deec9ae3SHaavard Skinnemoen [8] = "SDIOIRQA",
496deec9ae3SHaavard Skinnemoen [9] = "SDIOIRQB",
49704d699c3SRob Emanuele [12] = "SDIOWAIT",
49804d699c3SRob Emanuele [14] = "RXBUFF",
49904d699c3SRob Emanuele [15] = "TXBUFE",
500deec9ae3SHaavard Skinnemoen [16] = "RINDE",
501deec9ae3SHaavard Skinnemoen [17] = "RDIRE",
502deec9ae3SHaavard Skinnemoen [18] = "RCRCE",
503deec9ae3SHaavard Skinnemoen [19] = "RENDE",
504deec9ae3SHaavard Skinnemoen [20] = "RTOE",
505deec9ae3SHaavard Skinnemoen [21] = "DCRCE",
506deec9ae3SHaavard Skinnemoen [22] = "DTOE",
50704d699c3SRob Emanuele [23] = "CSTOE",
50804d699c3SRob Emanuele [24] = "BLKOVRE",
50904d699c3SRob Emanuele [25] = "DMADONE",
51004d699c3SRob Emanuele [26] = "FIFOEMPTY",
51104d699c3SRob Emanuele [27] = "XFRDONE",
512deec9ae3SHaavard Skinnemoen [30] = "OVRE",
513deec9ae3SHaavard Skinnemoen [31] = "UNRE",
514deec9ae3SHaavard Skinnemoen };
515deec9ae3SHaavard Skinnemoen unsigned int i;
516deec9ae3SHaavard Skinnemoen
517deec9ae3SHaavard Skinnemoen seq_printf(s, "%s:\t0x%08x", regname, value);
518deec9ae3SHaavard Skinnemoen for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
519deec9ae3SHaavard Skinnemoen if (value & (1 << i)) {
520deec9ae3SHaavard Skinnemoen if (sr_bit[i])
521deec9ae3SHaavard Skinnemoen seq_printf(s, " %s", sr_bit[i]);
522deec9ae3SHaavard Skinnemoen else
523deec9ae3SHaavard Skinnemoen seq_puts(s, " UNKNOWN");
524deec9ae3SHaavard Skinnemoen }
525deec9ae3SHaavard Skinnemoen }
526deec9ae3SHaavard Skinnemoen seq_putc(s, '\n');
527deec9ae3SHaavard Skinnemoen }
528deec9ae3SHaavard Skinnemoen
atmci_regs_show(struct seq_file * s,void * v)529deec9ae3SHaavard Skinnemoen static int atmci_regs_show(struct seq_file *s, void *v)
530deec9ae3SHaavard Skinnemoen {
531deec9ae3SHaavard Skinnemoen struct atmel_mci *host = s->private;
532deec9ae3SHaavard Skinnemoen u32 *buf;
533b3894f26SBoris BREZILLON int ret = 0;
534b3894f26SBoris BREZILLON
535deec9ae3SHaavard Skinnemoen
5362c96a293SLudovic Desroches buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
537deec9ae3SHaavard Skinnemoen if (!buf)
538deec9ae3SHaavard Skinnemoen return -ENOMEM;
539deec9ae3SHaavard Skinnemoen
540ae552ab0SWenyou Yang pm_runtime_get_sync(&host->pdev->dev);
541ae552ab0SWenyou Yang
542965ebf33SHaavard Skinnemoen /*
543965ebf33SHaavard Skinnemoen * Grab a more or less consistent snapshot. Note that we're
544965ebf33SHaavard Skinnemoen * not disabling interrupts, so IMR and SR may not be
545965ebf33SHaavard Skinnemoen * consistent.
546965ebf33SHaavard Skinnemoen */
547965ebf33SHaavard Skinnemoen spin_lock_bh(&host->lock);
5482c96a293SLudovic Desroches memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
549965ebf33SHaavard Skinnemoen spin_unlock_bh(&host->lock);
550deec9ae3SHaavard Skinnemoen
551ae552ab0SWenyou Yang pm_runtime_mark_last_busy(&host->pdev->dev);
552ae552ab0SWenyou Yang pm_runtime_put_autosuspend(&host->pdev->dev);
553b3894f26SBoris BREZILLON
5548a4de07eSNicolas Ferre seq_printf(s, "MR:\t0x%08x%s%s ",
5552c96a293SLudovic Desroches buf[ATMCI_MR / 4],
5562c96a293SLudovic Desroches buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
5578a4de07eSNicolas Ferre buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "");
5588a4de07eSNicolas Ferre if (host->caps.has_odd_clk_div)
5598a4de07eSNicolas Ferre seq_printf(s, "{CLKDIV,CLKODD}=%u\n",
5608a4de07eSNicolas Ferre ((buf[ATMCI_MR / 4] & 0xff) << 1)
5618a4de07eSNicolas Ferre | ((buf[ATMCI_MR / 4] >> 16) & 1));
5628a4de07eSNicolas Ferre else
5638a4de07eSNicolas Ferre seq_printf(s, "CLKDIV=%u\n",
5648a4de07eSNicolas Ferre (buf[ATMCI_MR / 4] & 0xff));
5652c96a293SLudovic Desroches seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
5662c96a293SLudovic Desroches seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
5672c96a293SLudovic Desroches seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
568deec9ae3SHaavard Skinnemoen seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
5692c96a293SLudovic Desroches buf[ATMCI_BLKR / 4],
5702c96a293SLudovic Desroches buf[ATMCI_BLKR / 4] & 0xffff,
5712c96a293SLudovic Desroches (buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
572796211b7SLudovic Desroches if (host->caps.has_cstor_reg)
5732c96a293SLudovic Desroches seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
574deec9ae3SHaavard Skinnemoen
575deec9ae3SHaavard Skinnemoen /* Don't read RSPR and RDR; it will consume the data there */
576deec9ae3SHaavard Skinnemoen
5772c96a293SLudovic Desroches atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
5782c96a293SLudovic Desroches atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
579deec9ae3SHaavard Skinnemoen
580ccdfe612SHein_Tibosch if (host->caps.has_dma_conf_reg) {
58174791a2dSNicolas Ferre u32 val;
58274791a2dSNicolas Ferre
5832c96a293SLudovic Desroches val = buf[ATMCI_DMA / 4];
58474791a2dSNicolas Ferre seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
58574791a2dSNicolas Ferre val, val & 3,
58674791a2dSNicolas Ferre ((val >> 4) & 3) ?
58774791a2dSNicolas Ferre 1 << (((val >> 4) & 3) + 1) : 1,
5882c96a293SLudovic Desroches val & ATMCI_DMAEN ? " DMAEN" : "");
589796211b7SLudovic Desroches }
590796211b7SLudovic Desroches if (host->caps.has_cfg_reg) {
591796211b7SLudovic Desroches u32 val;
59274791a2dSNicolas Ferre
5932c96a293SLudovic Desroches val = buf[ATMCI_CFG / 4];
59474791a2dSNicolas Ferre seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
59574791a2dSNicolas Ferre val,
5962c96a293SLudovic Desroches val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
5972c96a293SLudovic Desroches val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
5982c96a293SLudovic Desroches val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
5992c96a293SLudovic Desroches val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
60074791a2dSNicolas Ferre }
60174791a2dSNicolas Ferre
602b17339a1SHaavard Skinnemoen kfree(buf);
603b17339a1SHaavard Skinnemoen
604b3894f26SBoris BREZILLON return ret;
605deec9ae3SHaavard Skinnemoen }
606deec9ae3SHaavard Skinnemoen
6078ceb2943SYangtao Li DEFINE_SHOW_ATTRIBUTE(atmci_regs);
608deec9ae3SHaavard Skinnemoen
atmci_init_debugfs(struct atmel_mci_slot * slot)609965ebf33SHaavard Skinnemoen static void atmci_init_debugfs(struct atmel_mci_slot *slot)
610deec9ae3SHaavard Skinnemoen {
611965ebf33SHaavard Skinnemoen struct mmc_host *mmc = slot->mmc;
612965ebf33SHaavard Skinnemoen struct atmel_mci *host = slot->host;
613deec9ae3SHaavard Skinnemoen struct dentry *root;
614deec9ae3SHaavard Skinnemoen
615deec9ae3SHaavard Skinnemoen root = mmc->debugfs_root;
616deec9ae3SHaavard Skinnemoen if (!root)
617deec9ae3SHaavard Skinnemoen return;
618deec9ae3SHaavard Skinnemoen
619091eb12fSGreg Kroah-Hartman debugfs_create_file("regs", S_IRUSR, root, host, &atmci_regs_fops);
620091eb12fSGreg Kroah-Hartman debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
621f1dfe70bSGeert Uytterhoeven debugfs_create_u32("state", S_IRUSR, root, &host->state);
622785bbb80SGeert Uytterhoeven debugfs_create_xul("pending_events", S_IRUSR, root,
623785bbb80SGeert Uytterhoeven &host->pending_events);
624785bbb80SGeert Uytterhoeven debugfs_create_xul("completed_events", S_IRUSR, root,
625785bbb80SGeert Uytterhoeven &host->completed_events);
626deec9ae3SHaavard Skinnemoen }
6277d2be074SHaavard Skinnemoen
628e919fd20SLudovic Desroches #if defined(CONFIG_OF)
629e919fd20SLudovic Desroches static const struct of_device_id atmci_dt_ids[] = {
630e919fd20SLudovic Desroches { .compatible = "atmel,hsmci" },
631e919fd20SLudovic Desroches { /* sentinel */ }
632e919fd20SLudovic Desroches };
633e919fd20SLudovic Desroches
634e919fd20SLudovic Desroches MODULE_DEVICE_TABLE(of, atmci_dt_ids);
635e919fd20SLudovic Desroches
636c3be1efdSBill Pemberton static struct mci_platform_data*
atmci_of_init(struct platform_device * pdev)637e919fd20SLudovic Desroches atmci_of_init(struct platform_device *pdev)
638e919fd20SLudovic Desroches {
639e919fd20SLudovic Desroches struct device_node *np = pdev->dev.of_node;
640e919fd20SLudovic Desroches struct device_node *cnp;
641e919fd20SLudovic Desroches struct mci_platform_data *pdata;
642e919fd20SLudovic Desroches u32 slot_id;
643*98ac9e4fSBalamanikandan Gunasundar int err;
644e919fd20SLudovic Desroches
645e919fd20SLudovic Desroches if (!np) {
646e919fd20SLudovic Desroches dev_err(&pdev->dev, "device node not found\n");
647e919fd20SLudovic Desroches return ERR_PTR(-EINVAL);
648e919fd20SLudovic Desroches }
649e919fd20SLudovic Desroches
650e919fd20SLudovic Desroches pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
6519b344ba4SMarkus Elfring if (!pdata)
652e919fd20SLudovic Desroches return ERR_PTR(-ENOMEM);
653e919fd20SLudovic Desroches
654e919fd20SLudovic Desroches for_each_child_of_node(np, cnp) {
655e919fd20SLudovic Desroches if (of_property_read_u32(cnp, "reg", &slot_id)) {
656bf892de9SRob Herring dev_warn(&pdev->dev, "reg property is missing for %pOF\n",
657bf892de9SRob Herring cnp);
658e919fd20SLudovic Desroches continue;
659e919fd20SLudovic Desroches }
660e919fd20SLudovic Desroches
661e919fd20SLudovic Desroches if (slot_id >= ATMCI_MAX_NR_SLOTS) {
662e919fd20SLudovic Desroches dev_warn(&pdev->dev, "can't have more than %d slots\n",
663e919fd20SLudovic Desroches ATMCI_MAX_NR_SLOTS);
6647366419bSJulia Lawall of_node_put(cnp);
665e919fd20SLudovic Desroches break;
666e919fd20SLudovic Desroches }
667e919fd20SLudovic Desroches
668e919fd20SLudovic Desroches if (of_property_read_u32(cnp, "bus-width",
669e919fd20SLudovic Desroches &pdata->slot[slot_id].bus_width))
670e919fd20SLudovic Desroches pdata->slot[slot_id].bus_width = 1;
671e919fd20SLudovic Desroches
672e919fd20SLudovic Desroches pdata->slot[slot_id].detect_pin =
673ce6e9472SBalamanikandan Gunasundar devm_fwnode_gpiod_get(&pdev->dev, of_fwnode_handle(cnp),
674ce6e9472SBalamanikandan Gunasundar "cd", GPIOD_IN, "cd-gpios");
675*98ac9e4fSBalamanikandan Gunasundar err = PTR_ERR_OR_ZERO(pdata->slot[slot_id].detect_pin);
676*98ac9e4fSBalamanikandan Gunasundar if (err) {
677*98ac9e4fSBalamanikandan Gunasundar if (err != -ENOENT)
678*98ac9e4fSBalamanikandan Gunasundar return ERR_PTR(err);
679ce6e9472SBalamanikandan Gunasundar pdata->slot[slot_id].detect_pin = NULL;
680*98ac9e4fSBalamanikandan Gunasundar }
681e919fd20SLudovic Desroches
68276d55564STimo Kokkonen pdata->slot[slot_id].non_removable =
68376d55564STimo Kokkonen of_property_read_bool(cnp, "non-removable");
68476d55564STimo Kokkonen
685e919fd20SLudovic Desroches pdata->slot[slot_id].wp_pin =
686ce6e9472SBalamanikandan Gunasundar devm_fwnode_gpiod_get(&pdev->dev, of_fwnode_handle(cnp),
687ce6e9472SBalamanikandan Gunasundar "wp", GPIOD_IN, "wp-gpios");
688*98ac9e4fSBalamanikandan Gunasundar err = PTR_ERR_OR_ZERO(pdata->slot[slot_id].wp_pin);
689*98ac9e4fSBalamanikandan Gunasundar if (err) {
690*98ac9e4fSBalamanikandan Gunasundar if (err != -ENOENT)
691*98ac9e4fSBalamanikandan Gunasundar return ERR_PTR(err);
692ce6e9472SBalamanikandan Gunasundar pdata->slot[slot_id].wp_pin = NULL;
693e919fd20SLudovic Desroches }
694*98ac9e4fSBalamanikandan Gunasundar }
695e919fd20SLudovic Desroches
696e919fd20SLudovic Desroches return pdata;
697e919fd20SLudovic Desroches }
698e919fd20SLudovic Desroches #else /* CONFIG_OF */
699e919fd20SLudovic Desroches static inline struct mci_platform_data*
atmci_of_init(struct platform_device * dev)700e919fd20SLudovic Desroches atmci_of_init(struct platform_device *dev)
701e919fd20SLudovic Desroches {
702e919fd20SLudovic Desroches return ERR_PTR(-EINVAL);
703e919fd20SLudovic Desroches }
704e919fd20SLudovic Desroches #endif
705e919fd20SLudovic Desroches
atmci_get_version(struct atmel_mci * host)7067a90dcc2SLudovic Desroches static inline unsigned int atmci_get_version(struct atmel_mci *host)
7077a90dcc2SLudovic Desroches {
7087a90dcc2SLudovic Desroches return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
7097a90dcc2SLudovic Desroches }
7107a90dcc2SLudovic Desroches
711447dc0d2Sludovic.desroches@atmel.com /*
712447dc0d2Sludovic.desroches@atmel.com * Fix sconfig's burst size according to atmel MCI. We need to convert them as:
713447dc0d2Sludovic.desroches@atmel.com * 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
714447dc0d2Sludovic.desroches@atmel.com * With version 0x600, we need to convert them as: 1 -> 0, 2 -> 1, 4 -> 2,
715447dc0d2Sludovic.desroches@atmel.com * 8 -> 3, 16 -> 4.
716447dc0d2Sludovic.desroches@atmel.com *
717447dc0d2Sludovic.desroches@atmel.com * This can be done by finding most significant bit set.
718447dc0d2Sludovic.desroches@atmel.com */
atmci_convert_chksize(struct atmel_mci * host,unsigned int maxburst)719447dc0d2Sludovic.desroches@atmel.com static inline unsigned int atmci_convert_chksize(struct atmel_mci *host,
720447dc0d2Sludovic.desroches@atmel.com unsigned int maxburst)
721447dc0d2Sludovic.desroches@atmel.com {
722447dc0d2Sludovic.desroches@atmel.com unsigned int version = atmci_get_version(host);
723447dc0d2Sludovic.desroches@atmel.com unsigned int offset = 2;
724447dc0d2Sludovic.desroches@atmel.com
725447dc0d2Sludovic.desroches@atmel.com if (version >= 0x600)
726447dc0d2Sludovic.desroches@atmel.com offset = 1;
727447dc0d2Sludovic.desroches@atmel.com
728447dc0d2Sludovic.desroches@atmel.com if (maxburst > 1)
729447dc0d2Sludovic.desroches@atmel.com return fls(maxburst) - offset;
730447dc0d2Sludovic.desroches@atmel.com else
731447dc0d2Sludovic.desroches@atmel.com return 0;
732447dc0d2Sludovic.desroches@atmel.com }
733447dc0d2Sludovic.desroches@atmel.com
atmci_timeout_timer(struct timer_list * t)7342ee4f620SKees Cook static void atmci_timeout_timer(struct timer_list *t)
73524011f34SLudovic Desroches {
73624011f34SLudovic Desroches struct atmel_mci *host;
73724011f34SLudovic Desroches
7382ee4f620SKees Cook host = from_timer(host, t, timer);
73924011f34SLudovic Desroches
74024011f34SLudovic Desroches dev_dbg(&host->pdev->dev, "software timeout\n");
74124011f34SLudovic Desroches
74224011f34SLudovic Desroches if (host->mrq->cmd->data) {
74324011f34SLudovic Desroches host->mrq->cmd->data->error = -ETIMEDOUT;
74424011f34SLudovic Desroches host->data = NULL;
745c1fa3426SLudovic Desroches /*
746c1fa3426SLudovic Desroches * With some SDIO modules, sometimes DMA transfer hangs. If
747c1fa3426SLudovic Desroches * stop_transfer() is not called then the DMA request is not
748c1fa3426SLudovic Desroches * removed, following ones are queued and never computed.
749c1fa3426SLudovic Desroches */
750c1fa3426SLudovic Desroches if (host->state == STATE_DATA_XFER)
751c1fa3426SLudovic Desroches host->stop_transfer(host);
75224011f34SLudovic Desroches } else {
75324011f34SLudovic Desroches host->mrq->cmd->error = -ETIMEDOUT;
75424011f34SLudovic Desroches host->cmd = NULL;
75524011f34SLudovic Desroches }
75624011f34SLudovic Desroches host->need_reset = 1;
75724011f34SLudovic Desroches host->state = STATE_END_REQUEST;
75824011f34SLudovic Desroches smp_wmb();
75924011f34SLudovic Desroches tasklet_schedule(&host->tasklet);
76024011f34SLudovic Desroches }
76124011f34SLudovic Desroches
atmci_ns_to_clocks(struct atmel_mci * host,unsigned int ns)7622c96a293SLudovic Desroches static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
7637d2be074SHaavard Skinnemoen unsigned int ns)
7647d2be074SHaavard Skinnemoen {
76566292ad9SLudovic Desroches /*
76666292ad9SLudovic Desroches * It is easier here to use us instead of ns for the timeout,
76766292ad9SLudovic Desroches * it prevents from overflows during calculation.
76866292ad9SLudovic Desroches */
76966292ad9SLudovic Desroches unsigned int us = DIV_ROUND_UP(ns, 1000);
77066292ad9SLudovic Desroches
77166292ad9SLudovic Desroches /* Maximum clock frequency is host->bus_hz/2 */
77266292ad9SLudovic Desroches return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
7737d2be074SHaavard Skinnemoen }
7747d2be074SHaavard Skinnemoen
atmci_set_timeout(struct atmel_mci * host,struct atmel_mci_slot * slot,struct mmc_data * data)7757d2be074SHaavard Skinnemoen static void atmci_set_timeout(struct atmel_mci *host,
776965ebf33SHaavard Skinnemoen struct atmel_mci_slot *slot, struct mmc_data *data)
7777d2be074SHaavard Skinnemoen {
7787d2be074SHaavard Skinnemoen static unsigned dtomul_to_shift[] = {
7797d2be074SHaavard Skinnemoen 0, 4, 7, 8, 10, 12, 16, 20
7807d2be074SHaavard Skinnemoen };
7817d2be074SHaavard Skinnemoen unsigned timeout;
7827d2be074SHaavard Skinnemoen unsigned dtocyc;
7837d2be074SHaavard Skinnemoen unsigned dtomul;
7847d2be074SHaavard Skinnemoen
7852c96a293SLudovic Desroches timeout = atmci_ns_to_clocks(host, data->timeout_ns)
7862c96a293SLudovic Desroches + data->timeout_clks;
7877d2be074SHaavard Skinnemoen
7887d2be074SHaavard Skinnemoen for (dtomul = 0; dtomul < 8; dtomul++) {
7897d2be074SHaavard Skinnemoen unsigned shift = dtomul_to_shift[dtomul];
7907d2be074SHaavard Skinnemoen dtocyc = (timeout + (1 << shift) - 1) >> shift;
7917d2be074SHaavard Skinnemoen if (dtocyc < 15)
7927d2be074SHaavard Skinnemoen break;
7937d2be074SHaavard Skinnemoen }
7947d2be074SHaavard Skinnemoen
7957d2be074SHaavard Skinnemoen if (dtomul >= 8) {
7967d2be074SHaavard Skinnemoen dtomul = 7;
7977d2be074SHaavard Skinnemoen dtocyc = 15;
7987d2be074SHaavard Skinnemoen }
7997d2be074SHaavard Skinnemoen
800965ebf33SHaavard Skinnemoen dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
8017d2be074SHaavard Skinnemoen dtocyc << dtomul_to_shift[dtomul]);
80203fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
8037d2be074SHaavard Skinnemoen }
8047d2be074SHaavard Skinnemoen
8057d2be074SHaavard Skinnemoen /*
8067d2be074SHaavard Skinnemoen * Return mask with command flags to be enabled for this command.
8077d2be074SHaavard Skinnemoen */
atmci_prepare_command(struct mmc_host * mmc,struct mmc_command * cmd)8087d2be074SHaavard Skinnemoen static u32 atmci_prepare_command(struct mmc_host *mmc,
8097d2be074SHaavard Skinnemoen struct mmc_command *cmd)
8107d2be074SHaavard Skinnemoen {
8117d2be074SHaavard Skinnemoen struct mmc_data *data;
8127d2be074SHaavard Skinnemoen u32 cmdr;
8137d2be074SHaavard Skinnemoen
8147d2be074SHaavard Skinnemoen cmd->error = -EINPROGRESS;
8157d2be074SHaavard Skinnemoen
8162c96a293SLudovic Desroches cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
8177d2be074SHaavard Skinnemoen
8187d2be074SHaavard Skinnemoen if (cmd->flags & MMC_RSP_PRESENT) {
8197d2be074SHaavard Skinnemoen if (cmd->flags & MMC_RSP_136)
8202c96a293SLudovic Desroches cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
8217d2be074SHaavard Skinnemoen else
8222c96a293SLudovic Desroches cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
8237d2be074SHaavard Skinnemoen }
8247d2be074SHaavard Skinnemoen
8257d2be074SHaavard Skinnemoen /*
8267d2be074SHaavard Skinnemoen * This should really be MAXLAT_5 for CMD2 and ACMD41, but
8277d2be074SHaavard Skinnemoen * it's too difficult to determine whether this is an ACMD or
8287d2be074SHaavard Skinnemoen * not. Better make it 64.
8297d2be074SHaavard Skinnemoen */
8302c96a293SLudovic Desroches cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
8317d2be074SHaavard Skinnemoen
8327d2be074SHaavard Skinnemoen if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
8332c96a293SLudovic Desroches cmdr |= ATMCI_CMDR_OPDCMD;
8347d2be074SHaavard Skinnemoen
8357d2be074SHaavard Skinnemoen data = cmd->data;
8367d2be074SHaavard Skinnemoen if (data) {
8372c96a293SLudovic Desroches cmdr |= ATMCI_CMDR_START_XFER;
8382f1d7918SNicolas Ferre
8392f1d7918SNicolas Ferre if (cmd->opcode == SD_IO_RW_EXTENDED) {
8402c96a293SLudovic Desroches cmdr |= ATMCI_CMDR_SDIO_BLOCK;
8412f1d7918SNicolas Ferre } else {
842fd551d94SJaehoon Chung if (data->blocks > 1)
8432c96a293SLudovic Desroches cmdr |= ATMCI_CMDR_MULTI_BLOCK;
8447d2be074SHaavard Skinnemoen else
8452c96a293SLudovic Desroches cmdr |= ATMCI_CMDR_BLOCK;
8462f1d7918SNicolas Ferre }
8477d2be074SHaavard Skinnemoen
8487d2be074SHaavard Skinnemoen if (data->flags & MMC_DATA_READ)
8492c96a293SLudovic Desroches cmdr |= ATMCI_CMDR_TRDIR_READ;
8507d2be074SHaavard Skinnemoen }
8517d2be074SHaavard Skinnemoen
8527d2be074SHaavard Skinnemoen return cmdr;
8537d2be074SHaavard Skinnemoen }
8547d2be074SHaavard Skinnemoen
atmci_send_command(struct atmel_mci * host,struct mmc_command * cmd,u32 cmd_flags)85511d1488bSLudovic Desroches static void atmci_send_command(struct atmel_mci *host,
856965ebf33SHaavard Skinnemoen struct mmc_command *cmd, u32 cmd_flags)
8577d2be074SHaavard Skinnemoen {
858ef5053bdSUlf Hansson unsigned int timeout_ms = cmd->busy_timeout ? cmd->busy_timeout :
859ef5053bdSUlf Hansson ATMCI_CMD_TIMEOUT_MS;
860ef5053bdSUlf Hansson
8617d2be074SHaavard Skinnemoen WARN_ON(host->cmd);
8627d2be074SHaavard Skinnemoen host->cmd = cmd;
8637d2be074SHaavard Skinnemoen
864965ebf33SHaavard Skinnemoen dev_vdbg(&host->pdev->dev,
8657d2be074SHaavard Skinnemoen "start command: ARGR=0x%08x CMDR=0x%08x\n",
8667d2be074SHaavard Skinnemoen cmd->arg, cmd_flags);
8677d2be074SHaavard Skinnemoen
86803fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_ARGR, cmd->arg);
86903fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_CMDR, cmd_flags);
870ab5d94f7SUlf Hansson
871ef5053bdSUlf Hansson mod_timer(&host->timer, jiffies + msecs_to_jiffies(timeout_ms));
8727d2be074SHaavard Skinnemoen }
8737d2be074SHaavard Skinnemoen
atmci_send_stop_cmd(struct atmel_mci * host,struct mmc_data * data)8742c96a293SLudovic Desroches static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
8757d2be074SHaavard Skinnemoen {
8766801c41aSLudovic Desroches dev_dbg(&host->pdev->dev, "send stop command\n");
87711d1488bSLudovic Desroches atmci_send_command(host, data->stop, host->stop_cmdr);
87803fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
8797d2be074SHaavard Skinnemoen }
8807d2be074SHaavard Skinnemoen
881796211b7SLudovic Desroches /*
882796211b7SLudovic Desroches * Configure given PDC buffer taking care of alignement issues.
883796211b7SLudovic Desroches * Update host->data_size and host->sg.
884796211b7SLudovic Desroches */
atmci_pdc_set_single_buf(struct atmel_mci * host,enum atmci_xfer_dir dir,enum atmci_pdc_buf buf_nb)885796211b7SLudovic Desroches static void atmci_pdc_set_single_buf(struct atmel_mci *host,
886796211b7SLudovic Desroches enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
887796211b7SLudovic Desroches {
888796211b7SLudovic Desroches u32 pointer_reg, counter_reg;
8897a90dcc2SLudovic Desroches unsigned int buf_size;
890796211b7SLudovic Desroches
891796211b7SLudovic Desroches if (dir == XFER_RECEIVE) {
892796211b7SLudovic Desroches pointer_reg = ATMEL_PDC_RPR;
893796211b7SLudovic Desroches counter_reg = ATMEL_PDC_RCR;
894796211b7SLudovic Desroches } else {
895796211b7SLudovic Desroches pointer_reg = ATMEL_PDC_TPR;
896796211b7SLudovic Desroches counter_reg = ATMEL_PDC_TCR;
897796211b7SLudovic Desroches }
898796211b7SLudovic Desroches
899796211b7SLudovic Desroches if (buf_nb == PDC_SECOND_BUF) {
9001ebbe3d3SLudovic Desroches pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
9011ebbe3d3SLudovic Desroches counter_reg += ATMEL_PDC_SCND_BUF_OFF;
902796211b7SLudovic Desroches }
903796211b7SLudovic Desroches
9047a90dcc2SLudovic Desroches if (!host->caps.has_rwproof) {
9057a90dcc2SLudovic Desroches buf_size = host->buf_size;
9067a90dcc2SLudovic Desroches atmci_writel(host, pointer_reg, host->buf_phys_addr);
9077a90dcc2SLudovic Desroches } else {
9087a90dcc2SLudovic Desroches buf_size = sg_dma_len(host->sg);
909796211b7SLudovic Desroches atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
9107a90dcc2SLudovic Desroches }
9117a90dcc2SLudovic Desroches
9127a90dcc2SLudovic Desroches if (host->data_size <= buf_size) {
913796211b7SLudovic Desroches if (host->data_size & 0x3) {
914796211b7SLudovic Desroches /* If size is different from modulo 4, transfer bytes */
915796211b7SLudovic Desroches atmci_writel(host, counter_reg, host->data_size);
916796211b7SLudovic Desroches atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
917796211b7SLudovic Desroches } else {
918796211b7SLudovic Desroches /* Else transfer 32-bits words */
919796211b7SLudovic Desroches atmci_writel(host, counter_reg, host->data_size / 4);
920796211b7SLudovic Desroches }
921796211b7SLudovic Desroches host->data_size = 0;
922796211b7SLudovic Desroches } else {
923796211b7SLudovic Desroches /* We assume the size of a page is 32-bits aligned */
924341fa4c3SLudovic Desroches atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
925341fa4c3SLudovic Desroches host->data_size -= sg_dma_len(host->sg);
926796211b7SLudovic Desroches if (host->data_size)
927796211b7SLudovic Desroches host->sg = sg_next(host->sg);
928796211b7SLudovic Desroches }
929796211b7SLudovic Desroches }
930796211b7SLudovic Desroches
931796211b7SLudovic Desroches /*
932796211b7SLudovic Desroches * Configure PDC buffer according to the data size ie configuring one or two
933796211b7SLudovic Desroches * buffers. Don't use this function if you want to configure only the second
934796211b7SLudovic Desroches * buffer. In this case, use atmci_pdc_set_single_buf.
935796211b7SLudovic Desroches */
atmci_pdc_set_both_buf(struct atmel_mci * host,int dir)936796211b7SLudovic Desroches static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
937796211b7SLudovic Desroches {
938796211b7SLudovic Desroches atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
939796211b7SLudovic Desroches if (host->data_size)
940796211b7SLudovic Desroches atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
941796211b7SLudovic Desroches }
942796211b7SLudovic Desroches
943796211b7SLudovic Desroches /*
944796211b7SLudovic Desroches * Unmap sg lists, called when transfer is finished.
945796211b7SLudovic Desroches */
atmci_pdc_cleanup(struct atmel_mci * host)946796211b7SLudovic Desroches static void atmci_pdc_cleanup(struct atmel_mci *host)
947796211b7SLudovic Desroches {
948796211b7SLudovic Desroches struct mmc_data *data = host->data;
949796211b7SLudovic Desroches
950796211b7SLudovic Desroches if (data)
951796211b7SLudovic Desroches dma_unmap_sg(&host->pdev->dev,
952796211b7SLudovic Desroches data->sg, data->sg_len,
953feeef096SHeiner Kallweit mmc_get_dma_dir(data));
954796211b7SLudovic Desroches }
955796211b7SLudovic Desroches
956796211b7SLudovic Desroches /*
957796211b7SLudovic Desroches * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
958796211b7SLudovic Desroches * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
959796211b7SLudovic Desroches * interrupt needed for both transfer directions.
960796211b7SLudovic Desroches */
atmci_pdc_complete(struct atmel_mci * host)961796211b7SLudovic Desroches static void atmci_pdc_complete(struct atmel_mci *host)
962796211b7SLudovic Desroches {
9637a90dcc2SLudovic Desroches int transfer_size = host->data->blocks * host->data->blksz;
96424011f34SLudovic Desroches int i;
9657a90dcc2SLudovic Desroches
966796211b7SLudovic Desroches atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
9677a90dcc2SLudovic Desroches
9687a90dcc2SLudovic Desroches if ((!host->caps.has_rwproof)
96924011f34SLudovic Desroches && (host->data->flags & MMC_DATA_READ)) {
97024011f34SLudovic Desroches if (host->caps.has_bad_data_ordering)
97124011f34SLudovic Desroches for (i = 0; i < transfer_size; i++)
97224011f34SLudovic Desroches host->buffer[i] = swab32(host->buffer[i]);
9737a90dcc2SLudovic Desroches sg_copy_from_buffer(host->data->sg, host->data->sg_len,
9747a90dcc2SLudovic Desroches host->buffer, transfer_size);
97524011f34SLudovic Desroches }
9767a90dcc2SLudovic Desroches
977796211b7SLudovic Desroches atmci_pdc_cleanup(host);
978796211b7SLudovic Desroches
9796e9e4062SAlexandre Belloni dev_dbg(&host->pdev->dev, "(%s) set pending xfer complete\n", __func__);
980796211b7SLudovic Desroches atmci_set_pending(host, EVENT_XFER_COMPLETE);
981796211b7SLudovic Desroches tasklet_schedule(&host->tasklet);
982796211b7SLudovic Desroches }
983796211b7SLudovic Desroches
atmci_dma_cleanup(struct atmel_mci * host)98465e8b083SHaavard Skinnemoen static void atmci_dma_cleanup(struct atmel_mci *host)
98565e8b083SHaavard Skinnemoen {
98665e8b083SHaavard Skinnemoen struct mmc_data *data = host->data;
98765e8b083SHaavard Skinnemoen
988009a891bSNicolas Ferre if (data)
989266ac3f2SLinus Walleij dma_unmap_sg(host->dma.chan->device->dev,
990266ac3f2SLinus Walleij data->sg, data->sg_len,
991feeef096SHeiner Kallweit mmc_get_dma_dir(data));
99265e8b083SHaavard Skinnemoen }
99365e8b083SHaavard Skinnemoen
994796211b7SLudovic Desroches /*
995796211b7SLudovic Desroches * This function is called by the DMA driver from tasklet context.
996796211b7SLudovic Desroches */
atmci_dma_complete(void * arg)99765e8b083SHaavard Skinnemoen static void atmci_dma_complete(void *arg)
99865e8b083SHaavard Skinnemoen {
99965e8b083SHaavard Skinnemoen struct atmel_mci *host = arg;
100065e8b083SHaavard Skinnemoen struct mmc_data *data = host->data;
100165e8b083SHaavard Skinnemoen
100265e8b083SHaavard Skinnemoen dev_vdbg(&host->pdev->dev, "DMA complete\n");
100365e8b083SHaavard Skinnemoen
1004ccdfe612SHein_Tibosch if (host->caps.has_dma_conf_reg)
100574791a2dSNicolas Ferre /* Disable DMA hardware handshaking on MCI */
100603fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
100774791a2dSNicolas Ferre
100865e8b083SHaavard Skinnemoen atmci_dma_cleanup(host);
100965e8b083SHaavard Skinnemoen
101065e8b083SHaavard Skinnemoen /*
101165e8b083SHaavard Skinnemoen * If the card was removed, data will be NULL. No point trying
101265e8b083SHaavard Skinnemoen * to send the stop command or waiting for NBUSY in this case.
101365e8b083SHaavard Skinnemoen */
101465e8b083SHaavard Skinnemoen if (data) {
10156801c41aSLudovic Desroches dev_dbg(&host->pdev->dev,
10166801c41aSLudovic Desroches "(%s) set pending xfer complete\n", __func__);
101765e8b083SHaavard Skinnemoen atmci_set_pending(host, EVENT_XFER_COMPLETE);
101865e8b083SHaavard Skinnemoen tasklet_schedule(&host->tasklet);
101965e8b083SHaavard Skinnemoen
102065e8b083SHaavard Skinnemoen /*
102165e8b083SHaavard Skinnemoen * Regardless of what the documentation says, we have
102265e8b083SHaavard Skinnemoen * to wait for NOTBUSY even after block read
102365e8b083SHaavard Skinnemoen * operations.
102465e8b083SHaavard Skinnemoen *
102565e8b083SHaavard Skinnemoen * When the DMA transfer is complete, the controller
102665e8b083SHaavard Skinnemoen * may still be reading the CRC from the card, i.e.
102765e8b083SHaavard Skinnemoen * the data transfer is still in progress and we
102865e8b083SHaavard Skinnemoen * haven't seen all the potential error bits yet.
102965e8b083SHaavard Skinnemoen *
103065e8b083SHaavard Skinnemoen * The interrupt handler will schedule a different
103165e8b083SHaavard Skinnemoen * tasklet to finish things up when the data transfer
103265e8b083SHaavard Skinnemoen * is completely done.
103365e8b083SHaavard Skinnemoen *
103465e8b083SHaavard Skinnemoen * We may not complete the mmc request here anyway
103565e8b083SHaavard Skinnemoen * because the mmc layer may call back and cause us to
103665e8b083SHaavard Skinnemoen * violate the "don't submit new operations from the
103765e8b083SHaavard Skinnemoen * completion callback" rule of the dma engine
103865e8b083SHaavard Skinnemoen * framework.
103965e8b083SHaavard Skinnemoen */
104003fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
104165e8b083SHaavard Skinnemoen }
104265e8b083SHaavard Skinnemoen }
104365e8b083SHaavard Skinnemoen
1044796211b7SLudovic Desroches /*
1045796211b7SLudovic Desroches * Returns a mask of interrupt flags to be enabled after the whole
1046796211b7SLudovic Desroches * request has been prepared.
1047796211b7SLudovic Desroches */
atmci_prepare_data(struct atmel_mci * host,struct mmc_data * data)1048796211b7SLudovic Desroches static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
1049796211b7SLudovic Desroches {
1050796211b7SLudovic Desroches u32 iflags;
1051796211b7SLudovic Desroches
1052796211b7SLudovic Desroches data->error = -EINPROGRESS;
1053796211b7SLudovic Desroches
1054796211b7SLudovic Desroches host->sg = data->sg;
1055bdbc5d0cSTerry Barnaby host->sg_len = data->sg_len;
1056796211b7SLudovic Desroches host->data = data;
1057796211b7SLudovic Desroches host->data_chan = NULL;
1058796211b7SLudovic Desroches
1059796211b7SLudovic Desroches iflags = ATMCI_DATA_ERROR_FLAGS;
1060796211b7SLudovic Desroches
1061796211b7SLudovic Desroches /*
1062796211b7SLudovic Desroches * Errata: MMC data write operation with less than 12
1063796211b7SLudovic Desroches * bytes is impossible.
1064796211b7SLudovic Desroches *
1065796211b7SLudovic Desroches * Errata: MCI Transmit Data Register (TDR) FIFO
1066796211b7SLudovic Desroches * corruption when length is not multiple of 4.
1067796211b7SLudovic Desroches */
1068796211b7SLudovic Desroches if (data->blocks * data->blksz < 12
1069796211b7SLudovic Desroches || (data->blocks * data->blksz) & 3)
1070796211b7SLudovic Desroches host->need_reset = true;
1071796211b7SLudovic Desroches
1072796211b7SLudovic Desroches host->pio_offset = 0;
1073796211b7SLudovic Desroches if (data->flags & MMC_DATA_READ)
1074796211b7SLudovic Desroches iflags |= ATMCI_RXRDY;
1075796211b7SLudovic Desroches else
1076796211b7SLudovic Desroches iflags |= ATMCI_TXRDY;
1077796211b7SLudovic Desroches
1078796211b7SLudovic Desroches return iflags;
1079796211b7SLudovic Desroches }
1080796211b7SLudovic Desroches
1081796211b7SLudovic Desroches /*
1082796211b7SLudovic Desroches * Set interrupt flags and set block length into the MCI mode register even
1083796211b7SLudovic Desroches * if this value is also accessible in the MCI block register. It seems to be
1084796211b7SLudovic Desroches * necessary before the High Speed MCI version. It also map sg and configure
1085796211b7SLudovic Desroches * PDC registers.
1086796211b7SLudovic Desroches */
1087796211b7SLudovic Desroches static u32
atmci_prepare_data_pdc(struct atmel_mci * host,struct mmc_data * data)1088796211b7SLudovic Desroches atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1089796211b7SLudovic Desroches {
1090796211b7SLudovic Desroches u32 iflags, tmp;
109124011f34SLudovic Desroches int i;
1092796211b7SLudovic Desroches
1093796211b7SLudovic Desroches data->error = -EINPROGRESS;
1094796211b7SLudovic Desroches
1095796211b7SLudovic Desroches host->data = data;
1096796211b7SLudovic Desroches host->sg = data->sg;
1097796211b7SLudovic Desroches iflags = ATMCI_DATA_ERROR_FLAGS;
1098796211b7SLudovic Desroches
1099796211b7SLudovic Desroches /* Enable pdc mode */
1100796211b7SLudovic Desroches atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
1101796211b7SLudovic Desroches
1102feeef096SHeiner Kallweit if (data->flags & MMC_DATA_READ)
1103796211b7SLudovic Desroches iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
1104feeef096SHeiner Kallweit else
1105f5177547SLudovic Desroches iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE;
1106796211b7SLudovic Desroches
1107796211b7SLudovic Desroches /* Set BLKLEN */
1108796211b7SLudovic Desroches tmp = atmci_readl(host, ATMCI_MR);
1109796211b7SLudovic Desroches tmp &= 0x0000ffff;
1110796211b7SLudovic Desroches tmp |= ATMCI_BLKLEN(data->blksz);
1111796211b7SLudovic Desroches atmci_writel(host, ATMCI_MR, tmp);
1112796211b7SLudovic Desroches
1113796211b7SLudovic Desroches /* Configure PDC */
1114796211b7SLudovic Desroches host->data_size = data->blocks * data->blksz;
1115f98e0d5aSShawn Lin dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
1116feeef096SHeiner Kallweit mmc_get_dma_dir(data));
11177a90dcc2SLudovic Desroches
11187a90dcc2SLudovic Desroches if ((!host->caps.has_rwproof)
111924011f34SLudovic Desroches && (host->data->flags & MMC_DATA_WRITE)) {
11207a90dcc2SLudovic Desroches sg_copy_to_buffer(host->data->sg, host->data->sg_len,
11217a90dcc2SLudovic Desroches host->buffer, host->data_size);
112224011f34SLudovic Desroches if (host->caps.has_bad_data_ordering)
112324011f34SLudovic Desroches for (i = 0; i < host->data_size; i++)
112424011f34SLudovic Desroches host->buffer[i] = swab32(host->buffer[i]);
112524011f34SLudovic Desroches }
11267a90dcc2SLudovic Desroches
1127796211b7SLudovic Desroches if (host->data_size)
1128feeef096SHeiner Kallweit atmci_pdc_set_both_buf(host, data->flags & MMC_DATA_READ ?
1129feeef096SHeiner Kallweit XFER_RECEIVE : XFER_TRANSMIT);
1130796211b7SLudovic Desroches return iflags;
1131796211b7SLudovic Desroches }
1132796211b7SLudovic Desroches
1133796211b7SLudovic Desroches static u32
atmci_prepare_data_dma(struct atmel_mci * host,struct mmc_data * data)113474791a2dSNicolas Ferre atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
113565e8b083SHaavard Skinnemoen {
113665e8b083SHaavard Skinnemoen struct dma_chan *chan;
113765e8b083SHaavard Skinnemoen struct dma_async_tx_descriptor *desc;
113865e8b083SHaavard Skinnemoen struct scatterlist *sg;
113965e8b083SHaavard Skinnemoen unsigned int i;
114005f5799cSVinod Koul enum dma_transfer_direction slave_dirn;
1141657a77faSAtsushi Nemoto unsigned int sglen;
1142693e5e20SNicolas Ferre u32 maxburst;
1143796211b7SLudovic Desroches u32 iflags;
1144796211b7SLudovic Desroches
1145796211b7SLudovic Desroches data->error = -EINPROGRESS;
1146796211b7SLudovic Desroches
1147796211b7SLudovic Desroches WARN_ON(host->data);
1148796211b7SLudovic Desroches host->sg = NULL;
1149796211b7SLudovic Desroches host->data = data;
1150796211b7SLudovic Desroches
1151796211b7SLudovic Desroches iflags = ATMCI_DATA_ERROR_FLAGS;
115265e8b083SHaavard Skinnemoen
115365e8b083SHaavard Skinnemoen /*
115465e8b083SHaavard Skinnemoen * We don't do DMA on "complex" transfers, i.e. with
115565e8b083SHaavard Skinnemoen * non-word-aligned buffers or lengths. Also, we don't bother
115665e8b083SHaavard Skinnemoen * with all the DMA setup overhead for short transfers.
115765e8b083SHaavard Skinnemoen */
1158796211b7SLudovic Desroches if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
1159796211b7SLudovic Desroches return atmci_prepare_data(host, data);
116065e8b083SHaavard Skinnemoen if (data->blksz & 3)
1161796211b7SLudovic Desroches return atmci_prepare_data(host, data);
116265e8b083SHaavard Skinnemoen
116365e8b083SHaavard Skinnemoen for_each_sg(data->sg, sg, data->sg_len, i) {
116465e8b083SHaavard Skinnemoen if (sg->offset & 3 || sg->length & 3)
1165796211b7SLudovic Desroches return atmci_prepare_data(host, data);
116665e8b083SHaavard Skinnemoen }
116765e8b083SHaavard Skinnemoen
116865e8b083SHaavard Skinnemoen /* If we don't have a channel, we can't do DMA */
116983961aacSWan Jiabing if (!host->dma.chan)
117065e8b083SHaavard Skinnemoen return -ENODEV;
117165e8b083SHaavard Skinnemoen
117283961aacSWan Jiabing chan = host->dma.chan;
117383961aacSWan Jiabing host->data_chan = chan;
117483961aacSWan Jiabing
117505f5799cSVinod Koul if (data->flags & MMC_DATA_READ) {
1176e2b35f3dSViresh Kumar host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
1177447dc0d2Sludovic.desroches@atmel.com maxburst = atmci_convert_chksize(host,
1178447dc0d2Sludovic.desroches@atmel.com host->dma_conf.src_maxburst);
117905f5799cSVinod Koul } else {
1180e2b35f3dSViresh Kumar host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
1181447dc0d2Sludovic.desroches@atmel.com maxburst = atmci_convert_chksize(host,
1182447dc0d2Sludovic.desroches@atmel.com host->dma_conf.dst_maxburst);
118305f5799cSVinod Koul }
118465e8b083SHaavard Skinnemoen
1185ccdfe612SHein_Tibosch if (host->caps.has_dma_conf_reg)
1186ccdfe612SHein_Tibosch atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) |
1187ccdfe612SHein_Tibosch ATMCI_DMAEN);
1188693e5e20SNicolas Ferre
1189266ac3f2SLinus Walleij sglen = dma_map_sg(chan->device->dev, data->sg,
1190feeef096SHeiner Kallweit data->sg_len, mmc_get_dma_dir(data));
119188ce4db3SLinus Walleij
1192e2b35f3dSViresh Kumar dmaengine_slave_config(chan, &host->dma_conf);
119316052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan,
119405f5799cSVinod Koul data->sg, sglen, slave_dirn,
119565e8b083SHaavard Skinnemoen DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
119665e8b083SHaavard Skinnemoen if (!desc)
1197657a77faSAtsushi Nemoto goto unmap_exit;
119865e8b083SHaavard Skinnemoen
119965e8b083SHaavard Skinnemoen host->dma.data_desc = desc;
120065e8b083SHaavard Skinnemoen desc->callback = atmci_dma_complete;
120165e8b083SHaavard Skinnemoen desc->callback_param = host;
120265e8b083SHaavard Skinnemoen
1203796211b7SLudovic Desroches return iflags;
1204657a77faSAtsushi Nemoto unmap_exit:
1205feeef096SHeiner Kallweit dma_unmap_sg(chan->device->dev, data->sg, data->sg_len,
1206feeef096SHeiner Kallweit mmc_get_dma_dir(data));
1207657a77faSAtsushi Nemoto return -ENOMEM;
120865e8b083SHaavard Skinnemoen }
120965e8b083SHaavard Skinnemoen
1210796211b7SLudovic Desroches static void
atmci_submit_data(struct atmel_mci * host,struct mmc_data * data)1211796211b7SLudovic Desroches atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
1212796211b7SLudovic Desroches {
1213796211b7SLudovic Desroches return;
1214796211b7SLudovic Desroches }
1215796211b7SLudovic Desroches
1216796211b7SLudovic Desroches /*
1217796211b7SLudovic Desroches * Start PDC according to transfer direction.
1218796211b7SLudovic Desroches */
1219796211b7SLudovic Desroches static void
atmci_submit_data_pdc(struct atmel_mci * host,struct mmc_data * data)1220796211b7SLudovic Desroches atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
1221796211b7SLudovic Desroches {
1222796211b7SLudovic Desroches if (data->flags & MMC_DATA_READ)
1223796211b7SLudovic Desroches atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1224796211b7SLudovic Desroches else
1225796211b7SLudovic Desroches atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1226796211b7SLudovic Desroches }
1227796211b7SLudovic Desroches
1228796211b7SLudovic Desroches static void
atmci_submit_data_dma(struct atmel_mci * host,struct mmc_data * data)1229796211b7SLudovic Desroches atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
123074791a2dSNicolas Ferre {
123174791a2dSNicolas Ferre struct dma_chan *chan = host->data_chan;
123274791a2dSNicolas Ferre struct dma_async_tx_descriptor *desc = host->dma.data_desc;
123374791a2dSNicolas Ferre
123474791a2dSNicolas Ferre if (chan) {
12355328906aSLinus Walleij dmaengine_submit(desc);
12365328906aSLinus Walleij dma_async_issue_pending(chan);
123774791a2dSNicolas Ferre }
123874791a2dSNicolas Ferre }
123974791a2dSNicolas Ferre
atmci_stop_transfer(struct atmel_mci * host)1240796211b7SLudovic Desroches static void atmci_stop_transfer(struct atmel_mci *host)
124165e8b083SHaavard Skinnemoen {
12426801c41aSLudovic Desroches dev_dbg(&host->pdev->dev,
12436801c41aSLudovic Desroches "(%s) set pending xfer complete\n", __func__);
124465e8b083SHaavard Skinnemoen atmci_set_pending(host, EVENT_XFER_COMPLETE);
124503fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
124665e8b083SHaavard Skinnemoen }
124765e8b083SHaavard Skinnemoen
12487d2be074SHaavard Skinnemoen /*
12497122bbb0SMasanari Iida * Stop data transfer because error(s) occurred.
12507d2be074SHaavard Skinnemoen */
atmci_stop_transfer_pdc(struct atmel_mci * host)1251796211b7SLudovic Desroches static void atmci_stop_transfer_pdc(struct atmel_mci *host)
12527d2be074SHaavard Skinnemoen {
1253f5177547SLudovic Desroches atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
1254796211b7SLudovic Desroches }
12557d2be074SHaavard Skinnemoen
atmci_stop_transfer_dma(struct atmel_mci * host)1256796211b7SLudovic Desroches static void atmci_stop_transfer_dma(struct atmel_mci *host)
1257796211b7SLudovic Desroches {
1258796211b7SLudovic Desroches struct dma_chan *chan = host->data_chan;
12597d2be074SHaavard Skinnemoen
1260796211b7SLudovic Desroches if (chan) {
1261796211b7SLudovic Desroches dmaengine_terminate_all(chan);
1262796211b7SLudovic Desroches atmci_dma_cleanup(host);
1263796211b7SLudovic Desroches } else {
1264796211b7SLudovic Desroches /* Data transfer was stopped by the interrupt handler */
12656801c41aSLudovic Desroches dev_dbg(&host->pdev->dev,
12666801c41aSLudovic Desroches "(%s) set pending xfer complete\n", __func__);
1267796211b7SLudovic Desroches atmci_set_pending(host, EVENT_XFER_COMPLETE);
1268796211b7SLudovic Desroches atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1269796211b7SLudovic Desroches }
1270796211b7SLudovic Desroches }
1271965ebf33SHaavard Skinnemoen
1272965ebf33SHaavard Skinnemoen /*
1273796211b7SLudovic Desroches * Start a request: prepare data if needed, prepare the command and activate
1274796211b7SLudovic Desroches * interrupts.
1275965ebf33SHaavard Skinnemoen */
atmci_start_request(struct atmel_mci * host,struct atmel_mci_slot * slot)1276965ebf33SHaavard Skinnemoen static void atmci_start_request(struct atmel_mci *host,
1277965ebf33SHaavard Skinnemoen struct atmel_mci_slot *slot)
12787d2be074SHaavard Skinnemoen {
1279965ebf33SHaavard Skinnemoen struct mmc_request *mrq;
12807d2be074SHaavard Skinnemoen struct mmc_command *cmd;
1281965ebf33SHaavard Skinnemoen struct mmc_data *data;
12827d2be074SHaavard Skinnemoen u32 iflags;
1283965ebf33SHaavard Skinnemoen u32 cmdflags;
1284965ebf33SHaavard Skinnemoen
1285965ebf33SHaavard Skinnemoen mrq = slot->mrq;
1286965ebf33SHaavard Skinnemoen host->cur_slot = slot;
1287965ebf33SHaavard Skinnemoen host->mrq = mrq;
1288965ebf33SHaavard Skinnemoen
1289965ebf33SHaavard Skinnemoen host->pending_events = 0;
1290965ebf33SHaavard Skinnemoen host->completed_events = 0;
1291f5177547SLudovic Desroches host->cmd_status = 0;
1292ca55f46eSHaavard Skinnemoen host->data_status = 0;
1293965ebf33SHaavard Skinnemoen
12946801c41aSLudovic Desroches dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode);
12956801c41aSLudovic Desroches
129624011f34SLudovic Desroches if (host->need_reset || host->caps.need_reset_after_xfer) {
129718ee684bSLudovic Desroches iflags = atmci_readl(host, ATMCI_IMR);
129818ee684bSLudovic Desroches iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
129903fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
130003fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
130103fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_MR, host->mode_reg);
1302796211b7SLudovic Desroches if (host->caps.has_cfg_reg)
130303fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_CFG, host->cfg_reg);
130418ee684bSLudovic Desroches atmci_writel(host, ATMCI_IER, iflags);
1305965ebf33SHaavard Skinnemoen host->need_reset = false;
1306965ebf33SHaavard Skinnemoen }
130703fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
13087d2be074SHaavard Skinnemoen
130903fc9a7fSLudovic Desroches iflags = atmci_readl(host, ATMCI_IMR);
13102c96a293SLudovic Desroches if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
1311f5177547SLudovic Desroches dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
1312965ebf33SHaavard Skinnemoen iflags);
13137d2be074SHaavard Skinnemoen
1314965ebf33SHaavard Skinnemoen if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
1315965ebf33SHaavard Skinnemoen /* Send init sequence (74 clock cycles) */
131603fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
131703fc9a7fSLudovic Desroches while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
1318965ebf33SHaavard Skinnemoen cpu_relax();
13197d2be074SHaavard Skinnemoen }
132074791a2dSNicolas Ferre iflags = 0;
13217d2be074SHaavard Skinnemoen data = mrq->data;
13227d2be074SHaavard Skinnemoen if (data) {
1323965ebf33SHaavard Skinnemoen atmci_set_timeout(host, slot, data);
1324a252e3e3SHaavard Skinnemoen
1325a252e3e3SHaavard Skinnemoen /* Must set block count/size before sending command */
132603fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
13272c96a293SLudovic Desroches | ATMCI_BLKLEN(data->blksz));
1328965ebf33SHaavard Skinnemoen dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
13292c96a293SLudovic Desroches ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
133074791a2dSNicolas Ferre
1331796211b7SLudovic Desroches iflags |= host->prepare_data(host, data);
13327d2be074SHaavard Skinnemoen }
13337d2be074SHaavard Skinnemoen
13342c96a293SLudovic Desroches iflags |= ATMCI_CMDRDY;
13357d2be074SHaavard Skinnemoen cmd = mrq->cmd;
1336965ebf33SHaavard Skinnemoen cmdflags = atmci_prepare_command(slot->mmc, cmd);
133766b512edSLudovic Desroches
133866b512edSLudovic Desroches /*
133966b512edSLudovic Desroches * DMA transfer should be started before sending the command to avoid
134066b512edSLudovic Desroches * unexpected errors especially for read operations in SDIO mode.
134166b512edSLudovic Desroches * Unfortunately, in PDC mode, command has to be sent before starting
134266b512edSLudovic Desroches * the transfer.
134366b512edSLudovic Desroches */
134466b512edSLudovic Desroches if (host->submit_data != &atmci_submit_data_dma)
134511d1488bSLudovic Desroches atmci_send_command(host, cmd, cmdflags);
13467d2be074SHaavard Skinnemoen
13477d2be074SHaavard Skinnemoen if (data)
1348796211b7SLudovic Desroches host->submit_data(host, data);
13497d2be074SHaavard Skinnemoen
135066b512edSLudovic Desroches if (host->submit_data == &atmci_submit_data_dma)
135166b512edSLudovic Desroches atmci_send_command(host, cmd, cmdflags);
135266b512edSLudovic Desroches
13537d2be074SHaavard Skinnemoen if (mrq->stop) {
1354965ebf33SHaavard Skinnemoen host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
13552c96a293SLudovic Desroches host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
13567d2be074SHaavard Skinnemoen if (!(data->flags & MMC_DATA_WRITE))
13572c96a293SLudovic Desroches host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
13582c96a293SLudovic Desroches host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
13597d2be074SHaavard Skinnemoen }
13607d2be074SHaavard Skinnemoen
13617d2be074SHaavard Skinnemoen /*
13627d2be074SHaavard Skinnemoen * We could have enabled interrupts earlier, but I suspect
13637d2be074SHaavard Skinnemoen * that would open up a nice can of interesting race
13647d2be074SHaavard Skinnemoen * conditions (e.g. command and data complete, but stop not
13657d2be074SHaavard Skinnemoen * prepared yet.)
13667d2be074SHaavard Skinnemoen */
136703fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_IER, iflags);
1368965ebf33SHaavard Skinnemoen }
13697d2be074SHaavard Skinnemoen
atmci_queue_request(struct atmel_mci * host,struct atmel_mci_slot * slot,struct mmc_request * mrq)1370965ebf33SHaavard Skinnemoen static void atmci_queue_request(struct atmel_mci *host,
1371965ebf33SHaavard Skinnemoen struct atmel_mci_slot *slot, struct mmc_request *mrq)
1372965ebf33SHaavard Skinnemoen {
1373965ebf33SHaavard Skinnemoen dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1374965ebf33SHaavard Skinnemoen host->state);
1375965ebf33SHaavard Skinnemoen
1376965ebf33SHaavard Skinnemoen spin_lock_bh(&host->lock);
1377965ebf33SHaavard Skinnemoen slot->mrq = mrq;
1378965ebf33SHaavard Skinnemoen if (host->state == STATE_IDLE) {
1379965ebf33SHaavard Skinnemoen host->state = STATE_SENDING_CMD;
1380965ebf33SHaavard Skinnemoen atmci_start_request(host, slot);
1381965ebf33SHaavard Skinnemoen } else {
13826801c41aSLudovic Desroches dev_dbg(&host->pdev->dev, "queue request\n");
1383965ebf33SHaavard Skinnemoen list_add_tail(&slot->queue_node, &host->queue);
1384965ebf33SHaavard Skinnemoen }
1385965ebf33SHaavard Skinnemoen spin_unlock_bh(&host->lock);
1386965ebf33SHaavard Skinnemoen }
1387965ebf33SHaavard Skinnemoen
atmci_request(struct mmc_host * mmc,struct mmc_request * mrq)1388965ebf33SHaavard Skinnemoen static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1389965ebf33SHaavard Skinnemoen {
1390965ebf33SHaavard Skinnemoen struct atmel_mci_slot *slot = mmc_priv(mmc);
1391965ebf33SHaavard Skinnemoen struct atmel_mci *host = slot->host;
1392965ebf33SHaavard Skinnemoen struct mmc_data *data;
1393965ebf33SHaavard Skinnemoen
1394965ebf33SHaavard Skinnemoen WARN_ON(slot->mrq);
13956801c41aSLudovic Desroches dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode);
1396965ebf33SHaavard Skinnemoen
1397965ebf33SHaavard Skinnemoen /*
1398965ebf33SHaavard Skinnemoen * We may "know" the card is gone even though there's still an
1399965ebf33SHaavard Skinnemoen * electrical connection. If so, we really need to communicate
1400965ebf33SHaavard Skinnemoen * this to the MMC core since there won't be any more
1401965ebf33SHaavard Skinnemoen * interrupts as the card is completely removed. Otherwise,
1402965ebf33SHaavard Skinnemoen * the MMC core might believe the card is still there even
1403965ebf33SHaavard Skinnemoen * though the card was just removed very slowly.
1404965ebf33SHaavard Skinnemoen */
1405965ebf33SHaavard Skinnemoen if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
1406965ebf33SHaavard Skinnemoen mrq->cmd->error = -ENOMEDIUM;
1407965ebf33SHaavard Skinnemoen mmc_request_done(mmc, mrq);
14087d2be074SHaavard Skinnemoen return;
1409965ebf33SHaavard Skinnemoen }
14107d2be074SHaavard Skinnemoen
1411965ebf33SHaavard Skinnemoen /* We don't support multiple blocks of weird lengths. */
1412965ebf33SHaavard Skinnemoen data = mrq->data;
1413965ebf33SHaavard Skinnemoen if (data && data->blocks > 1 && data->blksz & 3) {
14147d2be074SHaavard Skinnemoen mrq->cmd->error = -EINVAL;
14157d2be074SHaavard Skinnemoen mmc_request_done(mmc, mrq);
14167d2be074SHaavard Skinnemoen }
14177d2be074SHaavard Skinnemoen
1418965ebf33SHaavard Skinnemoen atmci_queue_request(host, slot, mrq);
1419965ebf33SHaavard Skinnemoen }
1420965ebf33SHaavard Skinnemoen
atmci_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)14217d2be074SHaavard Skinnemoen static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
14227d2be074SHaavard Skinnemoen {
1423965ebf33SHaavard Skinnemoen struct atmel_mci_slot *slot = mmc_priv(mmc);
1424965ebf33SHaavard Skinnemoen struct atmel_mci *host = slot->host;
1425965ebf33SHaavard Skinnemoen unsigned int i;
1426ae552ab0SWenyou Yang
14272c96a293SLudovic Desroches slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
1428945533b5SHaavard Skinnemoen switch (ios->bus_width) {
1429945533b5SHaavard Skinnemoen case MMC_BUS_WIDTH_1:
14302c96a293SLudovic Desroches slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
1431945533b5SHaavard Skinnemoen break;
1432945533b5SHaavard Skinnemoen case MMC_BUS_WIDTH_4:
14332c96a293SLudovic Desroches slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
1434945533b5SHaavard Skinnemoen break;
1435b1d14045SNicolas Ferre case MMC_BUS_WIDTH_8:
1436b1d14045SNicolas Ferre slot->sdc_reg |= ATMCI_SDCBUS_8BIT;
1437b1d14045SNicolas Ferre break;
1438945533b5SHaavard Skinnemoen }
1439945533b5SHaavard Skinnemoen
14407d2be074SHaavard Skinnemoen if (ios->clock) {
1441965ebf33SHaavard Skinnemoen unsigned int clock_min = ~0U;
144260c8f783SLudovic Desroches int clkdiv;
14437d2be074SHaavard Skinnemoen
1444965ebf33SHaavard Skinnemoen spin_lock_bh(&host->lock);
1445965ebf33SHaavard Skinnemoen if (!host->mode_reg) {
144603fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
144703fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1448796211b7SLudovic Desroches if (host->caps.has_cfg_reg)
144903fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1450965ebf33SHaavard Skinnemoen }
1451945533b5SHaavard Skinnemoen
1452965ebf33SHaavard Skinnemoen /*
1453965ebf33SHaavard Skinnemoen * Use mirror of ios->clock to prevent race with mmc
1454965ebf33SHaavard Skinnemoen * core ios update when finding the minimum.
1455965ebf33SHaavard Skinnemoen */
1456965ebf33SHaavard Skinnemoen slot->clock = ios->clock;
14572c96a293SLudovic Desroches for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1458965ebf33SHaavard Skinnemoen if (host->slot[i] && host->slot[i]->clock
1459965ebf33SHaavard Skinnemoen && host->slot[i]->clock < clock_min)
1460965ebf33SHaavard Skinnemoen clock_min = host->slot[i]->clock;
1461965ebf33SHaavard Skinnemoen }
1462965ebf33SHaavard Skinnemoen
1463965ebf33SHaavard Skinnemoen /* Calculate clock divider */
1464faf8180bSLudovic Desroches if (host->caps.has_odd_clk_div) {
1465faf8180bSLudovic Desroches clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
146660c8f783SLudovic Desroches if (clkdiv < 0) {
146760c8f783SLudovic Desroches dev_warn(&mmc->class_dev,
146860c8f783SLudovic Desroches "clock %u too fast; using %lu\n",
146960c8f783SLudovic Desroches clock_min, host->bus_hz / 2);
147060c8f783SLudovic Desroches clkdiv = 0;
147160c8f783SLudovic Desroches } else if (clkdiv > 511) {
1472faf8180bSLudovic Desroches dev_warn(&mmc->class_dev,
1473faf8180bSLudovic Desroches "clock %u too slow; using %lu\n",
1474faf8180bSLudovic Desroches clock_min, host->bus_hz / (511 + 2));
1475faf8180bSLudovic Desroches clkdiv = 511;
1476faf8180bSLudovic Desroches }
1477faf8180bSLudovic Desroches host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)
1478faf8180bSLudovic Desroches | ATMCI_MR_CLKODD(clkdiv & 1);
1479faf8180bSLudovic Desroches } else {
1480965ebf33SHaavard Skinnemoen clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
14817d2be074SHaavard Skinnemoen if (clkdiv > 255) {
14827d2be074SHaavard Skinnemoen dev_warn(&mmc->class_dev,
14837d2be074SHaavard Skinnemoen "clock %u too slow; using %lu\n",
1484965ebf33SHaavard Skinnemoen clock_min, host->bus_hz / (2 * 256));
14857d2be074SHaavard Skinnemoen clkdiv = 255;
14867d2be074SHaavard Skinnemoen }
14872c96a293SLudovic Desroches host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
1488faf8180bSLudovic Desroches }
148904d699c3SRob Emanuele
1490965ebf33SHaavard Skinnemoen /*
1491965ebf33SHaavard Skinnemoen * WRPROOF and RDPROOF prevent overruns/underruns by
1492965ebf33SHaavard Skinnemoen * stopping the clock when the FIFO is full/empty.
1493965ebf33SHaavard Skinnemoen * This state is not expected to last for long.
1494965ebf33SHaavard Skinnemoen */
1495796211b7SLudovic Desroches if (host->caps.has_rwproof)
14962c96a293SLudovic Desroches host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
14977d2be074SHaavard Skinnemoen
1498796211b7SLudovic Desroches if (host->caps.has_cfg_reg) {
149999ddffd8SNicolas Ferre /* setup High Speed mode in relation with card capacity */
150099ddffd8SNicolas Ferre if (ios->timing == MMC_TIMING_SD_HS)
15012c96a293SLudovic Desroches host->cfg_reg |= ATMCI_CFG_HSMODE;
1502965ebf33SHaavard Skinnemoen else
15032c96a293SLudovic Desroches host->cfg_reg &= ~ATMCI_CFG_HSMODE;
150499ddffd8SNicolas Ferre }
150599ddffd8SNicolas Ferre
150699ddffd8SNicolas Ferre if (list_empty(&host->queue)) {
150703fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_MR, host->mode_reg);
1508796211b7SLudovic Desroches if (host->caps.has_cfg_reg)
150903fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_CFG, host->cfg_reg);
151099ddffd8SNicolas Ferre } else {
1511965ebf33SHaavard Skinnemoen host->need_clock_update = true;
151299ddffd8SNicolas Ferre }
1513965ebf33SHaavard Skinnemoen
1514965ebf33SHaavard Skinnemoen spin_unlock_bh(&host->lock);
1515945533b5SHaavard Skinnemoen } else {
1516965ebf33SHaavard Skinnemoen bool any_slot_active = false;
1517965ebf33SHaavard Skinnemoen
1518965ebf33SHaavard Skinnemoen spin_lock_bh(&host->lock);
1519965ebf33SHaavard Skinnemoen slot->clock = 0;
15202c96a293SLudovic Desroches for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1521965ebf33SHaavard Skinnemoen if (host->slot[i] && host->slot[i]->clock) {
1522965ebf33SHaavard Skinnemoen any_slot_active = true;
1523965ebf33SHaavard Skinnemoen break;
1524965ebf33SHaavard Skinnemoen }
1525965ebf33SHaavard Skinnemoen }
1526965ebf33SHaavard Skinnemoen if (!any_slot_active) {
152703fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
1528945533b5SHaavard Skinnemoen if (host->mode_reg) {
152903fc9a7fSLudovic Desroches atmci_readl(host, ATMCI_MR);
1530945533b5SHaavard Skinnemoen }
1531945533b5SHaavard Skinnemoen host->mode_reg = 0;
15327d2be074SHaavard Skinnemoen }
1533965ebf33SHaavard Skinnemoen spin_unlock_bh(&host->lock);
1534965ebf33SHaavard Skinnemoen }
15357d2be074SHaavard Skinnemoen
15367d2be074SHaavard Skinnemoen switch (ios->power_mode) {
15379e7861f5SAlexandre Belloni case MMC_POWER_OFF:
15389e7861f5SAlexandre Belloni if (!IS_ERR(mmc->supply.vmmc))
15399e7861f5SAlexandre Belloni mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
15409e7861f5SAlexandre Belloni break;
1541965ebf33SHaavard Skinnemoen case MMC_POWER_UP:
1542965ebf33SHaavard Skinnemoen set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
15439e7861f5SAlexandre Belloni if (!IS_ERR(mmc->supply.vmmc))
15449e7861f5SAlexandre Belloni mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1545965ebf33SHaavard Skinnemoen break;
15467d2be074SHaavard Skinnemoen default:
15477d2be074SHaavard Skinnemoen break;
15487d2be074SHaavard Skinnemoen }
15497d2be074SHaavard Skinnemoen }
15507d2be074SHaavard Skinnemoen
atmci_get_ro(struct mmc_host * mmc)15517d2be074SHaavard Skinnemoen static int atmci_get_ro(struct mmc_host *mmc)
15527d2be074SHaavard Skinnemoen {
1553965ebf33SHaavard Skinnemoen int read_only = -ENOSYS;
1554965ebf33SHaavard Skinnemoen struct atmel_mci_slot *slot = mmc_priv(mmc);
15557d2be074SHaavard Skinnemoen
1556ce6e9472SBalamanikandan Gunasundar if (slot->wp_pin) {
1557ce6e9472SBalamanikandan Gunasundar read_only = gpiod_get_value(slot->wp_pin);
15587d2be074SHaavard Skinnemoen dev_dbg(&mmc->class_dev, "card is %s\n",
15597d2be074SHaavard Skinnemoen read_only ? "read-only" : "read-write");
15607d2be074SHaavard Skinnemoen }
15617d2be074SHaavard Skinnemoen
15627d2be074SHaavard Skinnemoen return read_only;
15637d2be074SHaavard Skinnemoen }
15647d2be074SHaavard Skinnemoen
atmci_get_cd(struct mmc_host * mmc)1565965ebf33SHaavard Skinnemoen static int atmci_get_cd(struct mmc_host *mmc)
1566965ebf33SHaavard Skinnemoen {
1567965ebf33SHaavard Skinnemoen int present = -ENOSYS;
1568965ebf33SHaavard Skinnemoen struct atmel_mci_slot *slot = mmc_priv(mmc);
1569965ebf33SHaavard Skinnemoen
1570ce6e9472SBalamanikandan Gunasundar if (slot->detect_pin) {
1571*98ac9e4fSBalamanikandan Gunasundar present = gpiod_get_value_cansleep(slot->detect_pin);
1572965ebf33SHaavard Skinnemoen dev_dbg(&mmc->class_dev, "card is %spresent\n",
1573965ebf33SHaavard Skinnemoen present ? "" : "not ");
1574965ebf33SHaavard Skinnemoen }
1575965ebf33SHaavard Skinnemoen
1576965ebf33SHaavard Skinnemoen return present;
1577965ebf33SHaavard Skinnemoen }
1578965ebf33SHaavard Skinnemoen
atmci_enable_sdio_irq(struct mmc_host * mmc,int enable)157988ff82edSAnders Grahn static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
158088ff82edSAnders Grahn {
158188ff82edSAnders Grahn struct atmel_mci_slot *slot = mmc_priv(mmc);
158288ff82edSAnders Grahn struct atmel_mci *host = slot->host;
158388ff82edSAnders Grahn
158488ff82edSAnders Grahn if (enable)
158503fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_IER, slot->sdio_irq);
158688ff82edSAnders Grahn else
158703fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
158888ff82edSAnders Grahn }
158988ff82edSAnders Grahn
1590965ebf33SHaavard Skinnemoen static const struct mmc_host_ops atmci_ops = {
15917d2be074SHaavard Skinnemoen .request = atmci_request,
15927d2be074SHaavard Skinnemoen .set_ios = atmci_set_ios,
15937d2be074SHaavard Skinnemoen .get_ro = atmci_get_ro,
1594965ebf33SHaavard Skinnemoen .get_cd = atmci_get_cd,
159588ff82edSAnders Grahn .enable_sdio_irq = atmci_enable_sdio_irq,
15967d2be074SHaavard Skinnemoen };
15977d2be074SHaavard Skinnemoen
1598965ebf33SHaavard Skinnemoen /* Called with host->lock held */
atmci_request_end(struct atmel_mci * host,struct mmc_request * mrq)1599965ebf33SHaavard Skinnemoen static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1600965ebf33SHaavard Skinnemoen __releases(&host->lock)
1601965ebf33SHaavard Skinnemoen __acquires(&host->lock)
1602965ebf33SHaavard Skinnemoen {
1603965ebf33SHaavard Skinnemoen struct atmel_mci_slot *slot = NULL;
1604965ebf33SHaavard Skinnemoen struct mmc_host *prev_mmc = host->cur_slot->mmc;
1605965ebf33SHaavard Skinnemoen
1606965ebf33SHaavard Skinnemoen WARN_ON(host->cmd || host->data);
1607965ebf33SHaavard Skinnemoen
1608740e6499SUlf Hansson del_timer(&host->timer);
1609740e6499SUlf Hansson
1610965ebf33SHaavard Skinnemoen /*
1611965ebf33SHaavard Skinnemoen * Update the MMC clock rate if necessary. This may be
1612965ebf33SHaavard Skinnemoen * necessary if set_ios() is called when a different slot is
161325985edcSLucas De Marchi * busy transferring data.
1614965ebf33SHaavard Skinnemoen */
161599ddffd8SNicolas Ferre if (host->need_clock_update) {
161603fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_MR, host->mode_reg);
1617796211b7SLudovic Desroches if (host->caps.has_cfg_reg)
161803fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_CFG, host->cfg_reg);
161999ddffd8SNicolas Ferre }
1620965ebf33SHaavard Skinnemoen
1621965ebf33SHaavard Skinnemoen host->cur_slot->mrq = NULL;
1622965ebf33SHaavard Skinnemoen host->mrq = NULL;
1623965ebf33SHaavard Skinnemoen if (!list_empty(&host->queue)) {
1624965ebf33SHaavard Skinnemoen slot = list_entry(host->queue.next,
1625965ebf33SHaavard Skinnemoen struct atmel_mci_slot, queue_node);
1626965ebf33SHaavard Skinnemoen list_del(&slot->queue_node);
1627965ebf33SHaavard Skinnemoen dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1628965ebf33SHaavard Skinnemoen mmc_hostname(slot->mmc));
1629965ebf33SHaavard Skinnemoen host->state = STATE_SENDING_CMD;
1630965ebf33SHaavard Skinnemoen atmci_start_request(host, slot);
1631965ebf33SHaavard Skinnemoen } else {
1632965ebf33SHaavard Skinnemoen dev_vdbg(&host->pdev->dev, "list empty\n");
1633965ebf33SHaavard Skinnemoen host->state = STATE_IDLE;
1634965ebf33SHaavard Skinnemoen }
1635965ebf33SHaavard Skinnemoen
1636965ebf33SHaavard Skinnemoen spin_unlock(&host->lock);
1637965ebf33SHaavard Skinnemoen mmc_request_done(prev_mmc, mrq);
1638965ebf33SHaavard Skinnemoen spin_lock(&host->lock);
1639965ebf33SHaavard Skinnemoen }
1640965ebf33SHaavard Skinnemoen
atmci_command_complete(struct atmel_mci * host,struct mmc_command * cmd)16417d2be074SHaavard Skinnemoen static void atmci_command_complete(struct atmel_mci *host,
1642c06ad258SHaavard Skinnemoen struct mmc_command *cmd)
16437d2be074SHaavard Skinnemoen {
1644c06ad258SHaavard Skinnemoen u32 status = host->cmd_status;
1645c06ad258SHaavard Skinnemoen
16467d2be074SHaavard Skinnemoen /* Read the response from the card (up to 16 bytes) */
164703fc9a7fSLudovic Desroches cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
164803fc9a7fSLudovic Desroches cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
164903fc9a7fSLudovic Desroches cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
165003fc9a7fSLudovic Desroches cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
16517d2be074SHaavard Skinnemoen
16522c96a293SLudovic Desroches if (status & ATMCI_RTOE)
16537d2be074SHaavard Skinnemoen cmd->error = -ETIMEDOUT;
16542c96a293SLudovic Desroches else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
16557d2be074SHaavard Skinnemoen cmd->error = -EILSEQ;
16562c96a293SLudovic Desroches else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
16577d2be074SHaavard Skinnemoen cmd->error = -EIO;
165824011f34SLudovic Desroches else if (host->mrq->data && (host->mrq->data->blksz & 3)) {
165924011f34SLudovic Desroches if (host->caps.need_blksz_mul_4) {
166024011f34SLudovic Desroches cmd->error = -EINVAL;
166124011f34SLudovic Desroches host->need_reset = 1;
166224011f34SLudovic Desroches }
166324011f34SLudovic Desroches } else
16647d2be074SHaavard Skinnemoen cmd->error = 0;
16657d2be074SHaavard Skinnemoen }
16667d2be074SHaavard Skinnemoen
atmci_detect_change(struct timer_list * t)16672ee4f620SKees Cook static void atmci_detect_change(struct timer_list *t)
16687d2be074SHaavard Skinnemoen {
16692ee4f620SKees Cook struct atmel_mci_slot *slot = from_timer(slot, t, detect_timer);
1670965ebf33SHaavard Skinnemoen bool present;
1671965ebf33SHaavard Skinnemoen bool present_old;
16727d2be074SHaavard Skinnemoen
16737d2be074SHaavard Skinnemoen /*
1674965ebf33SHaavard Skinnemoen * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1675965ebf33SHaavard Skinnemoen * freeing the interrupt. We must not re-enable the interrupt
1676965ebf33SHaavard Skinnemoen * if it has been freed, and if we're shutting down, it
1677965ebf33SHaavard Skinnemoen * doesn't really matter whether the card is present or not.
16787d2be074SHaavard Skinnemoen */
16797d2be074SHaavard Skinnemoen smp_rmb();
1680965ebf33SHaavard Skinnemoen if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
16817d2be074SHaavard Skinnemoen return;
16827d2be074SHaavard Skinnemoen
1683ce6e9472SBalamanikandan Gunasundar enable_irq(gpiod_to_irq(slot->detect_pin));
1684*98ac9e4fSBalamanikandan Gunasundar present = gpiod_get_value_cansleep(slot->detect_pin);
1685965ebf33SHaavard Skinnemoen present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
16867d2be074SHaavard Skinnemoen
1687965ebf33SHaavard Skinnemoen dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1688965ebf33SHaavard Skinnemoen present, present_old);
16897d2be074SHaavard Skinnemoen
1690965ebf33SHaavard Skinnemoen if (present != present_old) {
1691965ebf33SHaavard Skinnemoen struct atmel_mci *host = slot->host;
1692965ebf33SHaavard Skinnemoen struct mmc_request *mrq;
1693965ebf33SHaavard Skinnemoen
1694965ebf33SHaavard Skinnemoen dev_dbg(&slot->mmc->class_dev, "card %s\n",
16957d2be074SHaavard Skinnemoen present ? "inserted" : "removed");
16967d2be074SHaavard Skinnemoen
1697965ebf33SHaavard Skinnemoen spin_lock(&host->lock);
1698965ebf33SHaavard Skinnemoen
1699965ebf33SHaavard Skinnemoen if (!present)
1700965ebf33SHaavard Skinnemoen clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1701965ebf33SHaavard Skinnemoen else
1702965ebf33SHaavard Skinnemoen set_bit(ATMCI_CARD_PRESENT, &slot->flags);
17037d2be074SHaavard Skinnemoen
17047d2be074SHaavard Skinnemoen /* Clean up queue if present */
1705965ebf33SHaavard Skinnemoen mrq = slot->mrq;
17067d2be074SHaavard Skinnemoen if (mrq) {
1707965ebf33SHaavard Skinnemoen if (mrq == host->mrq) {
17087d2be074SHaavard Skinnemoen /*
17097d2be074SHaavard Skinnemoen * Reset controller to terminate any ongoing
17107d2be074SHaavard Skinnemoen * commands or data transfers.
17117d2be074SHaavard Skinnemoen */
171203fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
171303fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
171403fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_MR, host->mode_reg);
1715796211b7SLudovic Desroches if (host->caps.has_cfg_reg)
171603fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_CFG, host->cfg_reg);
17177d2be074SHaavard Skinnemoen
17187d2be074SHaavard Skinnemoen host->data = NULL;
17197d2be074SHaavard Skinnemoen host->cmd = NULL;
1720c06ad258SHaavard Skinnemoen
1721c06ad258SHaavard Skinnemoen switch (host->state) {
1722965ebf33SHaavard Skinnemoen case STATE_IDLE:
1723965ebf33SHaavard Skinnemoen break;
1724c06ad258SHaavard Skinnemoen case STATE_SENDING_CMD:
1725c06ad258SHaavard Skinnemoen mrq->cmd->error = -ENOMEDIUM;
1726f5177547SLudovic Desroches if (mrq->data)
1727f5177547SLudovic Desroches host->stop_transfer(host);
1728c06ad258SHaavard Skinnemoen break;
1729f5177547SLudovic Desroches case STATE_DATA_XFER:
1730c06ad258SHaavard Skinnemoen mrq->data->error = -ENOMEDIUM;
1731796211b7SLudovic Desroches host->stop_transfer(host);
1732c06ad258SHaavard Skinnemoen break;
1733f5177547SLudovic Desroches case STATE_WAITING_NOTBUSY:
1734c06ad258SHaavard Skinnemoen mrq->data->error = -ENOMEDIUM;
1735c06ad258SHaavard Skinnemoen break;
1736c06ad258SHaavard Skinnemoen case STATE_SENDING_STOP:
1737c06ad258SHaavard Skinnemoen mrq->stop->error = -ENOMEDIUM;
1738c06ad258SHaavard Skinnemoen break;
1739f5177547SLudovic Desroches case STATE_END_REQUEST:
1740f5177547SLudovic Desroches break;
1741c06ad258SHaavard Skinnemoen }
1742c06ad258SHaavard Skinnemoen
1743965ebf33SHaavard Skinnemoen atmci_request_end(host, mrq);
1744965ebf33SHaavard Skinnemoen } else {
1745965ebf33SHaavard Skinnemoen list_del(&slot->queue_node);
1746965ebf33SHaavard Skinnemoen mrq->cmd->error = -ENOMEDIUM;
1747965ebf33SHaavard Skinnemoen if (mrq->data)
1748965ebf33SHaavard Skinnemoen mrq->data->error = -ENOMEDIUM;
1749965ebf33SHaavard Skinnemoen if (mrq->stop)
1750965ebf33SHaavard Skinnemoen mrq->stop->error = -ENOMEDIUM;
17517d2be074SHaavard Skinnemoen
1752965ebf33SHaavard Skinnemoen spin_unlock(&host->lock);
1753965ebf33SHaavard Skinnemoen mmc_request_done(slot->mmc, mrq);
1754965ebf33SHaavard Skinnemoen spin_lock(&host->lock);
1755965ebf33SHaavard Skinnemoen }
1756965ebf33SHaavard Skinnemoen }
1757965ebf33SHaavard Skinnemoen spin_unlock(&host->lock);
1758965ebf33SHaavard Skinnemoen
1759965ebf33SHaavard Skinnemoen mmc_detect_change(slot->mmc, 0);
17607d2be074SHaavard Skinnemoen }
17617d2be074SHaavard Skinnemoen }
17627d2be074SHaavard Skinnemoen
atmci_tasklet_func(struct tasklet_struct * t)176382a5d372SEmil Renner Berthing static void atmci_tasklet_func(struct tasklet_struct *t)
17647d2be074SHaavard Skinnemoen {
176582a5d372SEmil Renner Berthing struct atmel_mci *host = from_tasklet(host, t, tasklet);
17667d2be074SHaavard Skinnemoen struct mmc_request *mrq = host->mrq;
17677d2be074SHaavard Skinnemoen struct mmc_data *data = host->data;
1768c06ad258SHaavard Skinnemoen enum atmel_mci_state state = host->state;
1769c06ad258SHaavard Skinnemoen enum atmel_mci_state prev_state;
1770c06ad258SHaavard Skinnemoen u32 status;
1771c06ad258SHaavard Skinnemoen
1772965ebf33SHaavard Skinnemoen spin_lock(&host->lock);
1773965ebf33SHaavard Skinnemoen
1774c06ad258SHaavard Skinnemoen state = host->state;
17757d2be074SHaavard Skinnemoen
1776965ebf33SHaavard Skinnemoen dev_vdbg(&host->pdev->dev,
1777c06ad258SHaavard Skinnemoen "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1778c06ad258SHaavard Skinnemoen state, host->pending_events, host->completed_events,
177903fc9a7fSLudovic Desroches atmci_readl(host, ATMCI_IMR));
17807d2be074SHaavard Skinnemoen
1781c06ad258SHaavard Skinnemoen do {
1782c06ad258SHaavard Skinnemoen prev_state = state;
17836801c41aSLudovic Desroches dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state);
1784c06ad258SHaavard Skinnemoen
1785c06ad258SHaavard Skinnemoen switch (state) {
1786965ebf33SHaavard Skinnemoen case STATE_IDLE:
1787965ebf33SHaavard Skinnemoen break;
1788965ebf33SHaavard Skinnemoen
1789c06ad258SHaavard Skinnemoen case STATE_SENDING_CMD:
1790f5177547SLudovic Desroches /*
1791f5177547SLudovic Desroches * Command has been sent, we are waiting for command
1792f5177547SLudovic Desroches * ready. Then we have three next states possible:
1793f5177547SLudovic Desroches * END_REQUEST by default, WAITING_NOTBUSY if it's a
1794f5177547SLudovic Desroches * command needing it or DATA_XFER if there is data.
1795f5177547SLudovic Desroches */
17966801c41aSLudovic Desroches dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1797c06ad258SHaavard Skinnemoen if (!atmci_test_and_clear_pending(host,
1798f5177547SLudovic Desroches EVENT_CMD_RDY))
1799c06ad258SHaavard Skinnemoen break;
1800c06ad258SHaavard Skinnemoen
18016801c41aSLudovic Desroches dev_dbg(&host->pdev->dev, "set completed cmd ready\n");
18027d2be074SHaavard Skinnemoen host->cmd = NULL;
1803f5177547SLudovic Desroches atmci_set_completed(host, EVENT_CMD_RDY);
1804c06ad258SHaavard Skinnemoen atmci_command_complete(host, mrq->cmd);
1805f5177547SLudovic Desroches if (mrq->data) {
18066801c41aSLudovic Desroches dev_dbg(&host->pdev->dev,
18076801c41aSLudovic Desroches "command with data transfer");
1808f5177547SLudovic Desroches /*
1809f5177547SLudovic Desroches * If there is a command error don't start
1810f5177547SLudovic Desroches * data transfer.
1811f5177547SLudovic Desroches */
1812f5177547SLudovic Desroches if (mrq->cmd->error) {
1813f5177547SLudovic Desroches host->stop_transfer(host);
1814f5177547SLudovic Desroches host->data = NULL;
1815f5177547SLudovic Desroches atmci_writel(host, ATMCI_IDR,
1816f5177547SLudovic Desroches ATMCI_TXRDY | ATMCI_RXRDY
1817f5177547SLudovic Desroches | ATMCI_DATA_ERROR_FLAGS);
1818f5177547SLudovic Desroches state = STATE_END_REQUEST;
1819f5177547SLudovic Desroches } else
1820f5177547SLudovic Desroches state = STATE_DATA_XFER;
1821f5177547SLudovic Desroches } else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) {
18226801c41aSLudovic Desroches dev_dbg(&host->pdev->dev,
18236801c41aSLudovic Desroches "command response need waiting notbusy");
1824f5177547SLudovic Desroches atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1825f5177547SLudovic Desroches state = STATE_WAITING_NOTBUSY;
1826f5177547SLudovic Desroches } else
1827f5177547SLudovic Desroches state = STATE_END_REQUEST;
1828c06ad258SHaavard Skinnemoen
1829f5177547SLudovic Desroches break;
1830c06ad258SHaavard Skinnemoen
1831f5177547SLudovic Desroches case STATE_DATA_XFER:
1832c06ad258SHaavard Skinnemoen if (atmci_test_and_clear_pending(host,
1833c06ad258SHaavard Skinnemoen EVENT_DATA_ERROR)) {
18346801c41aSLudovic Desroches dev_dbg(&host->pdev->dev, "set completed data error\n");
1835f5177547SLudovic Desroches atmci_set_completed(host, EVENT_DATA_ERROR);
1836f5177547SLudovic Desroches state = STATE_END_REQUEST;
1837c06ad258SHaavard Skinnemoen break;
18387d2be074SHaavard Skinnemoen }
18397d2be074SHaavard Skinnemoen
1840f5177547SLudovic Desroches /*
1841f5177547SLudovic Desroches * A data transfer is in progress. The event expected
1842f5177547SLudovic Desroches * to move to the next state depends of data transfer
1843f5177547SLudovic Desroches * type (PDC or DMA). Once transfer done we can move
1844f5177547SLudovic Desroches * to the next step which is WAITING_NOTBUSY in write
1845f5177547SLudovic Desroches * case and directly SENDING_STOP in read case.
1846f5177547SLudovic Desroches */
18476801c41aSLudovic Desroches dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n");
1848c06ad258SHaavard Skinnemoen if (!atmci_test_and_clear_pending(host,
1849c06ad258SHaavard Skinnemoen EVENT_XFER_COMPLETE))
1850c06ad258SHaavard Skinnemoen break;
18517d2be074SHaavard Skinnemoen
18526801c41aSLudovic Desroches dev_dbg(&host->pdev->dev,
18536801c41aSLudovic Desroches "(%s) set completed xfer complete\n",
18546801c41aSLudovic Desroches __func__);
1855c06ad258SHaavard Skinnemoen atmci_set_completed(host, EVENT_XFER_COMPLETE);
1856c06ad258SHaavard Skinnemoen
1857077d4073SLudovic Desroches if (host->caps.need_notbusy_for_read_ops ||
1858077d4073SLudovic Desroches (host->data->flags & MMC_DATA_WRITE)) {
1859f5177547SLudovic Desroches atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1860f5177547SLudovic Desroches state = STATE_WAITING_NOTBUSY;
1861f5177547SLudovic Desroches } else if (host->mrq->stop) {
1862f5177547SLudovic Desroches atmci_send_stop_cmd(host, data);
1863f5177547SLudovic Desroches state = STATE_SENDING_STOP;
1864f5177547SLudovic Desroches } else {
1865c06ad258SHaavard Skinnemoen host->data = NULL;
18667d2be074SHaavard Skinnemoen data->bytes_xfered = data->blocks * data->blksz;
18677d2be074SHaavard Skinnemoen data->error = 0;
1868f5177547SLudovic Desroches state = STATE_END_REQUEST;
18697d2be074SHaavard Skinnemoen }
1870f5177547SLudovic Desroches break;
18717d2be074SHaavard Skinnemoen
1872f5177547SLudovic Desroches case STATE_WAITING_NOTBUSY:
1873f5177547SLudovic Desroches /*
1874f5177547SLudovic Desroches * We can be in the state for two reasons: a command
1875f5177547SLudovic Desroches * requiring waiting not busy signal (stop command
1876f5177547SLudovic Desroches * included) or a write operation. In the latest case,
1877f5177547SLudovic Desroches * we need to send a stop command.
1878f5177547SLudovic Desroches */
18796801c41aSLudovic Desroches dev_dbg(&host->pdev->dev, "FSM: not busy?\n");
1880f5177547SLudovic Desroches if (!atmci_test_and_clear_pending(host,
1881f5177547SLudovic Desroches EVENT_NOTBUSY))
1882f5177547SLudovic Desroches break;
18837d2be074SHaavard Skinnemoen
18846801c41aSLudovic Desroches dev_dbg(&host->pdev->dev, "set completed not busy\n");
1885f5177547SLudovic Desroches atmci_set_completed(host, EVENT_NOTBUSY);
1886f5177547SLudovic Desroches
1887f5177547SLudovic Desroches if (host->data) {
1888f5177547SLudovic Desroches /*
1889f5177547SLudovic Desroches * For some commands such as CMD53, even if
1890f5177547SLudovic Desroches * there is data transfer, there is no stop
1891f5177547SLudovic Desroches * command to send.
1892f5177547SLudovic Desroches */
1893f5177547SLudovic Desroches if (host->mrq->stop) {
18942c96a293SLudovic Desroches atmci_send_stop_cmd(host, data);
1895f5177547SLudovic Desroches state = STATE_SENDING_STOP;
1896f5177547SLudovic Desroches } else {
1897f5177547SLudovic Desroches host->data = NULL;
1898f5177547SLudovic Desroches data->bytes_xfered = data->blocks
1899f5177547SLudovic Desroches * data->blksz;
1900f5177547SLudovic Desroches data->error = 0;
1901f5177547SLudovic Desroches state = STATE_END_REQUEST;
1902f5177547SLudovic Desroches }
1903f5177547SLudovic Desroches } else
1904f5177547SLudovic Desroches state = STATE_END_REQUEST;
1905f5177547SLudovic Desroches break;
1906c06ad258SHaavard Skinnemoen
1907c06ad258SHaavard Skinnemoen case STATE_SENDING_STOP:
1908f5177547SLudovic Desroches /*
1909f5177547SLudovic Desroches * In this state, it is important to set host->data to
1910f5177547SLudovic Desroches * NULL (which is tested in the waiting notbusy state)
1911f5177547SLudovic Desroches * in order to go to the end request state instead of
1912f5177547SLudovic Desroches * sending stop again.
1913f5177547SLudovic Desroches */
19146801c41aSLudovic Desroches dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
1915c06ad258SHaavard Skinnemoen if (!atmci_test_and_clear_pending(host,
1916f5177547SLudovic Desroches EVENT_CMD_RDY))
1917c06ad258SHaavard Skinnemoen break;
1918c06ad258SHaavard Skinnemoen
19196801c41aSLudovic Desroches dev_dbg(&host->pdev->dev, "FSM: cmd ready\n");
1920c06ad258SHaavard Skinnemoen host->cmd = NULL;
1921f5177547SLudovic Desroches data->bytes_xfered = data->blocks * data->blksz;
1922f5177547SLudovic Desroches data->error = 0;
1923c06ad258SHaavard Skinnemoen atmci_command_complete(host, mrq->stop);
1924f5177547SLudovic Desroches if (mrq->stop->error) {
1925f5177547SLudovic Desroches host->stop_transfer(host);
1926f5177547SLudovic Desroches atmci_writel(host, ATMCI_IDR,
1927f5177547SLudovic Desroches ATMCI_TXRDY | ATMCI_RXRDY
1928f5177547SLudovic Desroches | ATMCI_DATA_ERROR_FLAGS);
1929f5177547SLudovic Desroches state = STATE_END_REQUEST;
1930f5177547SLudovic Desroches } else {
1931f5177547SLudovic Desroches atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1932f5177547SLudovic Desroches state = STATE_WAITING_NOTBUSY;
1933f5177547SLudovic Desroches }
193441b4e9a1SNicolas Ferre host->data = NULL;
1935c06ad258SHaavard Skinnemoen break;
1936c06ad258SHaavard Skinnemoen
1937f5177547SLudovic Desroches case STATE_END_REQUEST:
1938f5177547SLudovic Desroches atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY
1939f5177547SLudovic Desroches | ATMCI_DATA_ERROR_FLAGS);
1940f5177547SLudovic Desroches status = host->data_status;
1941f5177547SLudovic Desroches if (unlikely(status)) {
1942f5177547SLudovic Desroches host->stop_transfer(host);
1943f5177547SLudovic Desroches host->data = NULL;
1944fbd986cdSRodolfo Giometti if (data) {
1945f5177547SLudovic Desroches if (status & ATMCI_DTOE) {
1946f5177547SLudovic Desroches data->error = -ETIMEDOUT;
1947f5177547SLudovic Desroches } else if (status & ATMCI_DCRCE) {
1948f5177547SLudovic Desroches data->error = -EILSEQ;
1949f5177547SLudovic Desroches } else {
1950f5177547SLudovic Desroches data->error = -EIO;
1951f5177547SLudovic Desroches }
1952f5177547SLudovic Desroches }
1953fbd986cdSRodolfo Giometti }
1954f5177547SLudovic Desroches
1955f5177547SLudovic Desroches atmci_request_end(host, host->mrq);
1956ae460c11SJonas Danielsson goto unlock; /* atmci_request_end() sets host->state */
1957c06ad258SHaavard Skinnemoen break;
1958c06ad258SHaavard Skinnemoen }
1959c06ad258SHaavard Skinnemoen } while (state != prev_state);
1960c06ad258SHaavard Skinnemoen
1961c06ad258SHaavard Skinnemoen host->state = state;
1962965ebf33SHaavard Skinnemoen
1963ae460c11SJonas Danielsson unlock:
1964965ebf33SHaavard Skinnemoen spin_unlock(&host->lock);
19657d2be074SHaavard Skinnemoen }
19667d2be074SHaavard Skinnemoen
atmci_read_data_pio(struct atmel_mci * host)19677d2be074SHaavard Skinnemoen static void atmci_read_data_pio(struct atmel_mci *host)
19687d2be074SHaavard Skinnemoen {
19697d2be074SHaavard Skinnemoen struct scatterlist *sg = host->sg;
19707d2be074SHaavard Skinnemoen unsigned int offset = host->pio_offset;
19717d2be074SHaavard Skinnemoen struct mmc_data *data = host->data;
19727d2be074SHaavard Skinnemoen u32 value;
19737d2be074SHaavard Skinnemoen u32 status;
19747d2be074SHaavard Skinnemoen unsigned int nbytes = 0;
19757d2be074SHaavard Skinnemoen
19767d2be074SHaavard Skinnemoen do {
197703fc9a7fSLudovic Desroches value = atmci_readl(host, ATMCI_RDR);
19787d2be074SHaavard Skinnemoen if (likely(offset + 4 <= sg->length)) {
197919f5e9e0SLudovic Desroches sg_pcopy_from_buffer(sg, 1, &value, sizeof(u32), offset);
19807d2be074SHaavard Skinnemoen
19817d2be074SHaavard Skinnemoen offset += 4;
19827d2be074SHaavard Skinnemoen nbytes += 4;
19837d2be074SHaavard Skinnemoen
19847d2be074SHaavard Skinnemoen if (offset == sg->length) {
19855e7184aeSHaavard Skinnemoen flush_dcache_page(sg_page(sg));
19867d2be074SHaavard Skinnemoen host->sg = sg = sg_next(sg);
1987bdbc5d0cSTerry Barnaby host->sg_len--;
1988bdbc5d0cSTerry Barnaby if (!sg || !host->sg_len)
19897d2be074SHaavard Skinnemoen goto done;
19907d2be074SHaavard Skinnemoen
19917d2be074SHaavard Skinnemoen offset = 0;
19927d2be074SHaavard Skinnemoen }
19937d2be074SHaavard Skinnemoen } else {
19947d2be074SHaavard Skinnemoen unsigned int remaining = sg->length - offset;
19955b427781SChristoph Hellwig
199619f5e9e0SLudovic Desroches sg_pcopy_from_buffer(sg, 1, &value, remaining, offset);
19977d2be074SHaavard Skinnemoen nbytes += remaining;
19987d2be074SHaavard Skinnemoen
19997d2be074SHaavard Skinnemoen flush_dcache_page(sg_page(sg));
20007d2be074SHaavard Skinnemoen host->sg = sg = sg_next(sg);
2001bdbc5d0cSTerry Barnaby host->sg_len--;
2002bdbc5d0cSTerry Barnaby if (!sg || !host->sg_len)
20037d2be074SHaavard Skinnemoen goto done;
20047d2be074SHaavard Skinnemoen
20057d2be074SHaavard Skinnemoen offset = 4 - remaining;
200619f5e9e0SLudovic Desroches sg_pcopy_from_buffer(sg, 1, (u8 *)&value + remaining,
20075b427781SChristoph Hellwig offset, 0);
20087d2be074SHaavard Skinnemoen nbytes += offset;
20097d2be074SHaavard Skinnemoen }
20107d2be074SHaavard Skinnemoen
201103fc9a7fSLudovic Desroches status = atmci_readl(host, ATMCI_SR);
20127d2be074SHaavard Skinnemoen if (status & ATMCI_DATA_ERROR_FLAGS) {
201303fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
20147d2be074SHaavard Skinnemoen | ATMCI_DATA_ERROR_FLAGS));
20157d2be074SHaavard Skinnemoen host->data_status = status;
2016965ebf33SHaavard Skinnemoen data->bytes_xfered += nbytes;
2017965ebf33SHaavard Skinnemoen return;
20187d2be074SHaavard Skinnemoen }
20192c96a293SLudovic Desroches } while (status & ATMCI_RXRDY);
20207d2be074SHaavard Skinnemoen
20217d2be074SHaavard Skinnemoen host->pio_offset = offset;
20227d2be074SHaavard Skinnemoen data->bytes_xfered += nbytes;
20237d2be074SHaavard Skinnemoen
20247d2be074SHaavard Skinnemoen return;
20257d2be074SHaavard Skinnemoen
20267d2be074SHaavard Skinnemoen done:
202703fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
202803fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
20297d2be074SHaavard Skinnemoen data->bytes_xfered += nbytes;
2030965ebf33SHaavard Skinnemoen smp_wmb();
2031c06ad258SHaavard Skinnemoen atmci_set_pending(host, EVENT_XFER_COMPLETE);
20327d2be074SHaavard Skinnemoen }
20337d2be074SHaavard Skinnemoen
atmci_write_data_pio(struct atmel_mci * host)20347d2be074SHaavard Skinnemoen static void atmci_write_data_pio(struct atmel_mci *host)
20357d2be074SHaavard Skinnemoen {
20367d2be074SHaavard Skinnemoen struct scatterlist *sg = host->sg;
20377d2be074SHaavard Skinnemoen unsigned int offset = host->pio_offset;
20387d2be074SHaavard Skinnemoen struct mmc_data *data = host->data;
20397d2be074SHaavard Skinnemoen u32 value;
20407d2be074SHaavard Skinnemoen u32 status;
20417d2be074SHaavard Skinnemoen unsigned int nbytes = 0;
20427d2be074SHaavard Skinnemoen
20437d2be074SHaavard Skinnemoen do {
20447d2be074SHaavard Skinnemoen if (likely(offset + 4 <= sg->length)) {
204519f5e9e0SLudovic Desroches sg_pcopy_to_buffer(sg, 1, &value, sizeof(u32), offset);
204603fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_TDR, value);
20477d2be074SHaavard Skinnemoen
20487d2be074SHaavard Skinnemoen offset += 4;
20497d2be074SHaavard Skinnemoen nbytes += 4;
20507d2be074SHaavard Skinnemoen if (offset == sg->length) {
20517d2be074SHaavard Skinnemoen host->sg = sg = sg_next(sg);
2052bdbc5d0cSTerry Barnaby host->sg_len--;
2053bdbc5d0cSTerry Barnaby if (!sg || !host->sg_len)
20547d2be074SHaavard Skinnemoen goto done;
20557d2be074SHaavard Skinnemoen
20567d2be074SHaavard Skinnemoen offset = 0;
20577d2be074SHaavard Skinnemoen }
20587d2be074SHaavard Skinnemoen } else {
20597d2be074SHaavard Skinnemoen unsigned int remaining = sg->length - offset;
20607d2be074SHaavard Skinnemoen
20617d2be074SHaavard Skinnemoen value = 0;
206219f5e9e0SLudovic Desroches sg_pcopy_to_buffer(sg, 1, &value, remaining, offset);
20637d2be074SHaavard Skinnemoen nbytes += remaining;
20647d2be074SHaavard Skinnemoen
20657d2be074SHaavard Skinnemoen host->sg = sg = sg_next(sg);
2066bdbc5d0cSTerry Barnaby host->sg_len--;
2067bdbc5d0cSTerry Barnaby if (!sg || !host->sg_len) {
206803fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_TDR, value);
20697d2be074SHaavard Skinnemoen goto done;
20707d2be074SHaavard Skinnemoen }
20717d2be074SHaavard Skinnemoen
20727d2be074SHaavard Skinnemoen offset = 4 - remaining;
207319f5e9e0SLudovic Desroches sg_pcopy_to_buffer(sg, 1, (u8 *)&value + remaining,
20745b427781SChristoph Hellwig offset, 0);
207503fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_TDR, value);
20767d2be074SHaavard Skinnemoen nbytes += offset;
20777d2be074SHaavard Skinnemoen }
20787d2be074SHaavard Skinnemoen
207903fc9a7fSLudovic Desroches status = atmci_readl(host, ATMCI_SR);
20807d2be074SHaavard Skinnemoen if (status & ATMCI_DATA_ERROR_FLAGS) {
208103fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
20827d2be074SHaavard Skinnemoen | ATMCI_DATA_ERROR_FLAGS));
20837d2be074SHaavard Skinnemoen host->data_status = status;
2084965ebf33SHaavard Skinnemoen data->bytes_xfered += nbytes;
2085965ebf33SHaavard Skinnemoen return;
20867d2be074SHaavard Skinnemoen }
20872c96a293SLudovic Desroches } while (status & ATMCI_TXRDY);
20887d2be074SHaavard Skinnemoen
20897d2be074SHaavard Skinnemoen host->pio_offset = offset;
20907d2be074SHaavard Skinnemoen data->bytes_xfered += nbytes;
20917d2be074SHaavard Skinnemoen
20927d2be074SHaavard Skinnemoen return;
20937d2be074SHaavard Skinnemoen
20947d2be074SHaavard Skinnemoen done:
209503fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
209603fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
20977d2be074SHaavard Skinnemoen data->bytes_xfered += nbytes;
2098965ebf33SHaavard Skinnemoen smp_wmb();
2099c06ad258SHaavard Skinnemoen atmci_set_pending(host, EVENT_XFER_COMPLETE);
21007d2be074SHaavard Skinnemoen }
21017d2be074SHaavard Skinnemoen
atmci_sdio_interrupt(struct atmel_mci * host,u32 status)210288ff82edSAnders Grahn static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
210388ff82edSAnders Grahn {
210488ff82edSAnders Grahn int i;
210588ff82edSAnders Grahn
21062c96a293SLudovic Desroches for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
210788ff82edSAnders Grahn struct atmel_mci_slot *slot = host->slot[i];
210888ff82edSAnders Grahn if (slot && (status & slot->sdio_irq)) {
210988ff82edSAnders Grahn mmc_signal_sdio_irq(slot->mmc);
211088ff82edSAnders Grahn }
211188ff82edSAnders Grahn }
211288ff82edSAnders Grahn }
211388ff82edSAnders Grahn
211488ff82edSAnders Grahn
atmci_interrupt(int irq,void * dev_id)21157d2be074SHaavard Skinnemoen static irqreturn_t atmci_interrupt(int irq, void *dev_id)
21167d2be074SHaavard Skinnemoen {
2117965ebf33SHaavard Skinnemoen struct atmel_mci *host = dev_id;
21187d2be074SHaavard Skinnemoen u32 status, mask, pending;
21197d2be074SHaavard Skinnemoen unsigned int pass_count = 0;
21207d2be074SHaavard Skinnemoen
21217d2be074SHaavard Skinnemoen do {
212203fc9a7fSLudovic Desroches status = atmci_readl(host, ATMCI_SR);
212303fc9a7fSLudovic Desroches mask = atmci_readl(host, ATMCI_IMR);
21247d2be074SHaavard Skinnemoen pending = status & mask;
21257d2be074SHaavard Skinnemoen if (!pending)
21267d2be074SHaavard Skinnemoen break;
21277d2be074SHaavard Skinnemoen
21287d2be074SHaavard Skinnemoen if (pending & ATMCI_DATA_ERROR_FLAGS) {
21296801c41aSLudovic Desroches dev_dbg(&host->pdev->dev, "IRQ: data error\n");
213003fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
2131f5177547SLudovic Desroches | ATMCI_RXRDY | ATMCI_TXRDY
2132f5177547SLudovic Desroches | ATMCI_ENDRX | ATMCI_ENDTX
2133f5177547SLudovic Desroches | ATMCI_RXBUFF | ATMCI_TXBUFE);
2134965ebf33SHaavard Skinnemoen
21357d2be074SHaavard Skinnemoen host->data_status = status;
21366801c41aSLudovic Desroches dev_dbg(&host->pdev->dev, "set pending data error\n");
2137965ebf33SHaavard Skinnemoen smp_wmb();
21387d2be074SHaavard Skinnemoen atmci_set_pending(host, EVENT_DATA_ERROR);
21397d2be074SHaavard Skinnemoen tasklet_schedule(&host->tasklet);
21407d2be074SHaavard Skinnemoen }
2141796211b7SLudovic Desroches
2142796211b7SLudovic Desroches if (pending & ATMCI_TXBUFE) {
21436801c41aSLudovic Desroches dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n");
2144796211b7SLudovic Desroches atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
21457e8ba228SLudovic Desroches atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
2146796211b7SLudovic Desroches /*
2147796211b7SLudovic Desroches * We can receive this interruption before having configured
2148796211b7SLudovic Desroches * the second pdc buffer, so we need to reconfigure first and
2149796211b7SLudovic Desroches * second buffers again
2150796211b7SLudovic Desroches */
2151796211b7SLudovic Desroches if (host->data_size) {
2152796211b7SLudovic Desroches atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
21537e8ba228SLudovic Desroches atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
2154796211b7SLudovic Desroches atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
2155796211b7SLudovic Desroches } else {
2156796211b7SLudovic Desroches atmci_pdc_complete(host);
2157796211b7SLudovic Desroches }
21587e8ba228SLudovic Desroches } else if (pending & ATMCI_ENDTX) {
21596801c41aSLudovic Desroches dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n");
21607e8ba228SLudovic Desroches atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
21617e8ba228SLudovic Desroches
21627e8ba228SLudovic Desroches if (host->data_size) {
21637e8ba228SLudovic Desroches atmci_pdc_set_single_buf(host,
21647e8ba228SLudovic Desroches XFER_TRANSMIT, PDC_SECOND_BUF);
21657e8ba228SLudovic Desroches atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
21667e8ba228SLudovic Desroches }
2167796211b7SLudovic Desroches }
2168796211b7SLudovic Desroches
21697e8ba228SLudovic Desroches if (pending & ATMCI_RXBUFF) {
21706801c41aSLudovic Desroches dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n");
21717e8ba228SLudovic Desroches atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
21727e8ba228SLudovic Desroches atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
21737e8ba228SLudovic Desroches /*
21747e8ba228SLudovic Desroches * We can receive this interruption before having configured
21757e8ba228SLudovic Desroches * the second pdc buffer, so we need to reconfigure first and
21767e8ba228SLudovic Desroches * second buffers again
21777e8ba228SLudovic Desroches */
21787e8ba228SLudovic Desroches if (host->data_size) {
21797e8ba228SLudovic Desroches atmci_pdc_set_both_buf(host, XFER_RECEIVE);
21807e8ba228SLudovic Desroches atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
21817e8ba228SLudovic Desroches atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
21827e8ba228SLudovic Desroches } else {
21837e8ba228SLudovic Desroches atmci_pdc_complete(host);
21847e8ba228SLudovic Desroches }
21857e8ba228SLudovic Desroches } else if (pending & ATMCI_ENDRX) {
21866801c41aSLudovic Desroches dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n");
2187796211b7SLudovic Desroches atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
2188796211b7SLudovic Desroches
2189796211b7SLudovic Desroches if (host->data_size) {
2190796211b7SLudovic Desroches atmci_pdc_set_single_buf(host,
2191796211b7SLudovic Desroches XFER_RECEIVE, PDC_SECOND_BUF);
2192796211b7SLudovic Desroches atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
2193796211b7SLudovic Desroches }
2194796211b7SLudovic Desroches }
2195796211b7SLudovic Desroches
2196f5177547SLudovic Desroches /*
2197f5177547SLudovic Desroches * First mci IPs, so mainly the ones having pdc, have some
2198f5177547SLudovic Desroches * issues with the notbusy signal. You can't get it after
2199f5177547SLudovic Desroches * data transmission if you have not sent a stop command.
2200f5177547SLudovic Desroches * The appropriate workaround is to use the BLKE signal.
2201f5177547SLudovic Desroches */
2202f5177547SLudovic Desroches if (pending & ATMCI_BLKE) {
22036801c41aSLudovic Desroches dev_dbg(&host->pdev->dev, "IRQ: blke\n");
2204f5177547SLudovic Desroches atmci_writel(host, ATMCI_IDR, ATMCI_BLKE);
2205965ebf33SHaavard Skinnemoen smp_wmb();
22066801c41aSLudovic Desroches dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2207f5177547SLudovic Desroches atmci_set_pending(host, EVENT_NOTBUSY);
22087d2be074SHaavard Skinnemoen tasklet_schedule(&host->tasklet);
22097d2be074SHaavard Skinnemoen }
2210f5177547SLudovic Desroches
2211f5177547SLudovic Desroches if (pending & ATMCI_NOTBUSY) {
22126801c41aSLudovic Desroches dev_dbg(&host->pdev->dev, "IRQ: not_busy\n");
2213f5177547SLudovic Desroches atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY);
2214f5177547SLudovic Desroches smp_wmb();
22156801c41aSLudovic Desroches dev_dbg(&host->pdev->dev, "set pending notbusy\n");
2216f5177547SLudovic Desroches atmci_set_pending(host, EVENT_NOTBUSY);
2217f5177547SLudovic Desroches tasklet_schedule(&host->tasklet);
2218f5177547SLudovic Desroches }
2219f5177547SLudovic Desroches
22202c96a293SLudovic Desroches if (pending & ATMCI_RXRDY)
22217d2be074SHaavard Skinnemoen atmci_read_data_pio(host);
22222c96a293SLudovic Desroches if (pending & ATMCI_TXRDY)
22237d2be074SHaavard Skinnemoen atmci_write_data_pio(host);
22247d2be074SHaavard Skinnemoen
2225f5177547SLudovic Desroches if (pending & ATMCI_CMDRDY) {
22266801c41aSLudovic Desroches dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n");
2227f5177547SLudovic Desroches atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
2228f5177547SLudovic Desroches host->cmd_status = status;
2229f5177547SLudovic Desroches smp_wmb();
22306801c41aSLudovic Desroches dev_dbg(&host->pdev->dev, "set pending cmd rdy\n");
2231f5177547SLudovic Desroches atmci_set_pending(host, EVENT_CMD_RDY);
2232f5177547SLudovic Desroches tasklet_schedule(&host->tasklet);
2233f5177547SLudovic Desroches }
223488ff82edSAnders Grahn
22352c96a293SLudovic Desroches if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
223688ff82edSAnders Grahn atmci_sdio_interrupt(host, status);
223788ff82edSAnders Grahn
22387d2be074SHaavard Skinnemoen } while (pass_count++ < 5);
22397d2be074SHaavard Skinnemoen
22407d2be074SHaavard Skinnemoen return pass_count ? IRQ_HANDLED : IRQ_NONE;
22417d2be074SHaavard Skinnemoen }
22427d2be074SHaavard Skinnemoen
atmci_detect_interrupt(int irq,void * dev_id)22437d2be074SHaavard Skinnemoen static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
22447d2be074SHaavard Skinnemoen {
2245965ebf33SHaavard Skinnemoen struct atmel_mci_slot *slot = dev_id;
22467d2be074SHaavard Skinnemoen
22477d2be074SHaavard Skinnemoen /*
22487d2be074SHaavard Skinnemoen * Disable interrupts until the pin has stabilized and check
22497d2be074SHaavard Skinnemoen * the state then. Use mod_timer() since we may be in the
22507d2be074SHaavard Skinnemoen * middle of the timer routine when this interrupt triggers.
22517d2be074SHaavard Skinnemoen */
22527d2be074SHaavard Skinnemoen disable_irq_nosync(irq);
2253965ebf33SHaavard Skinnemoen mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
22547d2be074SHaavard Skinnemoen
22557d2be074SHaavard Skinnemoen return IRQ_HANDLED;
22567d2be074SHaavard Skinnemoen }
22577d2be074SHaavard Skinnemoen
atmci_init_slot(struct atmel_mci * host,struct mci_slot_pdata * slot_data,unsigned int id,u32 sdc_reg,u32 sdio_irq)2258ab050b92Sludovic.desroches@atmel.com static int atmci_init_slot(struct atmel_mci *host,
2259965ebf33SHaavard Skinnemoen struct mci_slot_pdata *slot_data, unsigned int id,
226088ff82edSAnders Grahn u32 sdc_reg, u32 sdio_irq)
2261965ebf33SHaavard Skinnemoen {
2262965ebf33SHaavard Skinnemoen struct mmc_host *mmc;
2263965ebf33SHaavard Skinnemoen struct atmel_mci_slot *slot;
22649e6e8c43SYang Yingliang int ret;
2265965ebf33SHaavard Skinnemoen
2266965ebf33SHaavard Skinnemoen mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
2267965ebf33SHaavard Skinnemoen if (!mmc)
2268965ebf33SHaavard Skinnemoen return -ENOMEM;
2269965ebf33SHaavard Skinnemoen
2270965ebf33SHaavard Skinnemoen slot = mmc_priv(mmc);
2271965ebf33SHaavard Skinnemoen slot->mmc = mmc;
2272965ebf33SHaavard Skinnemoen slot->host = host;
2273965ebf33SHaavard Skinnemoen slot->detect_pin = slot_data->detect_pin;
2274965ebf33SHaavard Skinnemoen slot->wp_pin = slot_data->wp_pin;
2275965ebf33SHaavard Skinnemoen slot->sdc_reg = sdc_reg;
227688ff82edSAnders Grahn slot->sdio_irq = sdio_irq;
2277965ebf33SHaavard Skinnemoen
2278e919fd20SLudovic Desroches dev_dbg(&mmc->class_dev,
2279e919fd20SLudovic Desroches "slot[%u]: bus_width=%u, detect_pin=%d, "
2280e919fd20SLudovic Desroches "detect_is_active_high=%s, wp_pin=%d\n",
2281ce6e9472SBalamanikandan Gunasundar id, slot_data->bus_width, desc_to_gpio(slot_data->detect_pin),
2282*98ac9e4fSBalamanikandan Gunasundar !gpiod_is_active_low(slot_data->detect_pin) ? "true" : "false",
2283ce6e9472SBalamanikandan Gunasundar desc_to_gpio(slot_data->wp_pin));
2284e919fd20SLudovic Desroches
2285965ebf33SHaavard Skinnemoen mmc->ops = &atmci_ops;
2286965ebf33SHaavard Skinnemoen mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
2287965ebf33SHaavard Skinnemoen mmc->f_max = host->bus_hz / 2;
2288965ebf33SHaavard Skinnemoen mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
228988ff82edSAnders Grahn if (sdio_irq)
229088ff82edSAnders Grahn mmc->caps |= MMC_CAP_SDIO_IRQ;
2291796211b7SLudovic Desroches if (host->caps.has_highspeed)
229299ddffd8SNicolas Ferre mmc->caps |= MMC_CAP_SD_HIGHSPEED;
22937a90dcc2SLudovic Desroches /*
22947a90dcc2SLudovic Desroches * Without the read/write proof capability, it is strongly suggested to
22957a90dcc2SLudovic Desroches * use only one bit for data to prevent fifo underruns and overruns
22967a90dcc2SLudovic Desroches * which will corrupt data.
22977a90dcc2SLudovic Desroches */
2298b1d14045SNicolas Ferre if ((slot_data->bus_width >= 4) && host->caps.has_rwproof) {
2299965ebf33SHaavard Skinnemoen mmc->caps |= MMC_CAP_4_BIT_DATA;
2300b1d14045SNicolas Ferre if (slot_data->bus_width >= 8)
2301b1d14045SNicolas Ferre mmc->caps |= MMC_CAP_8_BIT_DATA;
2302b1d14045SNicolas Ferre }
2303965ebf33SHaavard Skinnemoen
23047a90dcc2SLudovic Desroches if (atmci_get_version(host) < 0x200) {
23057a90dcc2SLudovic Desroches mmc->max_segs = 256;
23067a90dcc2SLudovic Desroches mmc->max_blk_size = 4095;
23077a90dcc2SLudovic Desroches mmc->max_blk_count = 256;
23087a90dcc2SLudovic Desroches mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
23097a90dcc2SLudovic Desroches mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs;
23107a90dcc2SLudovic Desroches } else {
2311a36274e0SMartin K. Petersen mmc->max_segs = 64;
2312965ebf33SHaavard Skinnemoen mmc->max_req_size = 32768 * 512;
2313965ebf33SHaavard Skinnemoen mmc->max_blk_size = 32768;
2314965ebf33SHaavard Skinnemoen mmc->max_blk_count = 512;
23157a90dcc2SLudovic Desroches }
2316965ebf33SHaavard Skinnemoen
2317965ebf33SHaavard Skinnemoen /* Assume card is present initially */
2318965ebf33SHaavard Skinnemoen set_bit(ATMCI_CARD_PRESENT, &slot->flags);
2319ce6e9472SBalamanikandan Gunasundar if (slot->detect_pin) {
2320*98ac9e4fSBalamanikandan Gunasundar if (!gpiod_get_value_cansleep(slot->detect_pin))
2321965ebf33SHaavard Skinnemoen clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
2322ce6e9472SBalamanikandan Gunasundar } else {
2323ce6e9472SBalamanikandan Gunasundar dev_dbg(&mmc->class_dev, "no detect pin available\n");
2324965ebf33SHaavard Skinnemoen }
2325965ebf33SHaavard Skinnemoen
2326ce6e9472SBalamanikandan Gunasundar if (!slot->detect_pin) {
232776d55564STimo Kokkonen if (slot_data->non_removable)
232876d55564STimo Kokkonen mmc->caps |= MMC_CAP_NONREMOVABLE;
232976d55564STimo Kokkonen else
2330965ebf33SHaavard Skinnemoen mmc->caps |= MMC_CAP_NEEDS_POLL;
233176d55564STimo Kokkonen }
2332965ebf33SHaavard Skinnemoen
2333ce6e9472SBalamanikandan Gunasundar if (!slot->wp_pin)
2334965ebf33SHaavard Skinnemoen dev_dbg(&mmc->class_dev, "no WP pin available\n");
2335965ebf33SHaavard Skinnemoen
2336965ebf33SHaavard Skinnemoen host->slot[id] = slot;
23379e7861f5SAlexandre Belloni mmc_regulator_get_supply(mmc);
23389e6e8c43SYang Yingliang ret = mmc_add_host(mmc);
23399e6e8c43SYang Yingliang if (ret) {
23409e6e8c43SYang Yingliang mmc_free_host(mmc);
23419e6e8c43SYang Yingliang return ret;
23429e6e8c43SYang Yingliang }
2343965ebf33SHaavard Skinnemoen
2344ce6e9472SBalamanikandan Gunasundar if (slot->detect_pin) {
23452ee4f620SKees Cook timer_setup(&slot->detect_timer, atmci_detect_change, 0);
2346965ebf33SHaavard Skinnemoen
2347ce6e9472SBalamanikandan Gunasundar ret = request_irq(gpiod_to_irq(slot->detect_pin),
2348965ebf33SHaavard Skinnemoen atmci_detect_interrupt,
2349965ebf33SHaavard Skinnemoen IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
2350965ebf33SHaavard Skinnemoen "mmc-detect", slot);
2351965ebf33SHaavard Skinnemoen if (ret) {
2352965ebf33SHaavard Skinnemoen dev_dbg(&mmc->class_dev,
2353965ebf33SHaavard Skinnemoen "could not request IRQ %d for detect pin\n",
2354ce6e9472SBalamanikandan Gunasundar gpiod_to_irq(slot->detect_pin));
2355ce6e9472SBalamanikandan Gunasundar slot->detect_pin = NULL;
2356965ebf33SHaavard Skinnemoen }
2357965ebf33SHaavard Skinnemoen }
2358965ebf33SHaavard Skinnemoen
2359965ebf33SHaavard Skinnemoen atmci_init_debugfs(slot);
2360965ebf33SHaavard Skinnemoen
2361965ebf33SHaavard Skinnemoen return 0;
2362965ebf33SHaavard Skinnemoen }
2363965ebf33SHaavard Skinnemoen
atmci_cleanup_slot(struct atmel_mci_slot * slot,unsigned int id)23645fef365bSArnd Bergmann static void atmci_cleanup_slot(struct atmel_mci_slot *slot,
2365965ebf33SHaavard Skinnemoen unsigned int id)
2366965ebf33SHaavard Skinnemoen {
2367965ebf33SHaavard Skinnemoen /* Debugfs stuff is cleaned up by mmc core */
2368965ebf33SHaavard Skinnemoen
2369965ebf33SHaavard Skinnemoen set_bit(ATMCI_SHUTDOWN, &slot->flags);
2370965ebf33SHaavard Skinnemoen smp_wmb();
2371965ebf33SHaavard Skinnemoen
2372965ebf33SHaavard Skinnemoen mmc_remove_host(slot->mmc);
2373965ebf33SHaavard Skinnemoen
2374ce6e9472SBalamanikandan Gunasundar if (slot->detect_pin) {
2375ce6e9472SBalamanikandan Gunasundar free_irq(gpiod_to_irq(slot->detect_pin), slot);
2376965ebf33SHaavard Skinnemoen del_timer_sync(&slot->detect_timer);
2377965ebf33SHaavard Skinnemoen }
2378965ebf33SHaavard Skinnemoen
2379965ebf33SHaavard Skinnemoen slot->host->slot[id] = NULL;
2380965ebf33SHaavard Skinnemoen mmc_free_host(slot->mmc);
2381965ebf33SHaavard Skinnemoen }
2382965ebf33SHaavard Skinnemoen
atmci_configure_dma(struct atmel_mci * host)2383467e081dSludovic.desroches@atmel.com static int atmci_configure_dma(struct atmel_mci *host)
23842635d1baSNicolas Ferre {
23855503301fSPeter Ujfalusi host->dma.chan = dma_request_chan(&host->pdev->dev, "rxtx");
238674843787SMans Rullgard
238774843787SMans Rullgard if (PTR_ERR(host->dma.chan) == -ENODEV) {
238874843787SMans Rullgard struct mci_platform_data *pdata = host->pdev->dev.platform_data;
238974843787SMans Rullgard dma_cap_mask_t mask;
239074843787SMans Rullgard
239193c77d29SBrent Taylor if (!pdata || !pdata->dma_filter)
239274843787SMans Rullgard return -ENODEV;
239374843787SMans Rullgard
239474843787SMans Rullgard dma_cap_zero(mask);
239574843787SMans Rullgard dma_cap_set(DMA_SLAVE, mask);
239674843787SMans Rullgard
239774843787SMans Rullgard host->dma.chan = dma_request_channel(mask, pdata->dma_filter,
239874843787SMans Rullgard pdata->dma_slave);
239974843787SMans Rullgard if (!host->dma.chan)
240074843787SMans Rullgard host->dma.chan = ERR_PTR(-ENODEV);
240174843787SMans Rullgard }
240274843787SMans Rullgard
2403467e081dSludovic.desroches@atmel.com if (IS_ERR(host->dma.chan))
2404467e081dSludovic.desroches@atmel.com return PTR_ERR(host->dma.chan);
24052635d1baSNicolas Ferre
2406467e081dSludovic.desroches@atmel.com dev_info(&host->pdev->dev, "using %s for DMA transfers\n",
240774791a2dSNicolas Ferre dma_chan_name(host->dma.chan));
2408e2b35f3dSViresh Kumar
2409e2b35f3dSViresh Kumar host->dma_conf.src_addr = host->mapbase + ATMCI_RDR;
2410e2b35f3dSViresh Kumar host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2411e2b35f3dSViresh Kumar host->dma_conf.src_maxburst = 1;
2412e2b35f3dSViresh Kumar host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR;
2413e2b35f3dSViresh Kumar host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2414e2b35f3dSViresh Kumar host->dma_conf.dst_maxburst = 1;
2415e2b35f3dSViresh Kumar host->dma_conf.device_fc = false;
2416467e081dSludovic.desroches@atmel.com
2417467e081dSludovic.desroches@atmel.com return 0;
24182635d1baSNicolas Ferre }
2419796211b7SLudovic Desroches
2420796211b7SLudovic Desroches /*
2421796211b7SLudovic Desroches * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
2422796211b7SLudovic Desroches * HSMCI provides DMA support and a new config register but no more supports
2423796211b7SLudovic Desroches * PDC.
2424796211b7SLudovic Desroches */
atmci_get_cap(struct atmel_mci * host)2425ab050b92Sludovic.desroches@atmel.com static void atmci_get_cap(struct atmel_mci *host)
2426796211b7SLudovic Desroches {
2427796211b7SLudovic Desroches unsigned int version;
2428796211b7SLudovic Desroches
2429796211b7SLudovic Desroches version = atmci_get_version(host);
2430796211b7SLudovic Desroches dev_info(&host->pdev->dev,
2431796211b7SLudovic Desroches "version: 0x%x\n", version);
2432796211b7SLudovic Desroches
2433fe6e1471SJiapeng Zhong host->caps.has_dma_conf_reg = false;
2434fe6e1471SJiapeng Zhong host->caps.has_pdc = true;
2435fe6e1471SJiapeng Zhong host->caps.has_cfg_reg = false;
2436fe6e1471SJiapeng Zhong host->caps.has_cstor_reg = false;
2437fe6e1471SJiapeng Zhong host->caps.has_highspeed = false;
2438fe6e1471SJiapeng Zhong host->caps.has_rwproof = false;
2439fe6e1471SJiapeng Zhong host->caps.has_odd_clk_div = false;
2440fe6e1471SJiapeng Zhong host->caps.has_bad_data_ordering = true;
2441fe6e1471SJiapeng Zhong host->caps.need_reset_after_xfer = true;
2442fe6e1471SJiapeng Zhong host->caps.need_blksz_mul_4 = true;
2443fe6e1471SJiapeng Zhong host->caps.need_notbusy_for_read_ops = false;
2444796211b7SLudovic Desroches
2445796211b7SLudovic Desroches /* keep only major version number */
2446796211b7SLudovic Desroches switch (version & 0xf00) {
2447215ba399SNicolas Ferre case 0x600:
2448796211b7SLudovic Desroches case 0x500:
2449fe6e1471SJiapeng Zhong host->caps.has_odd_clk_div = true;
2450df561f66SGustavo A. R. Silva fallthrough;
2451faf8180bSLudovic Desroches case 0x400:
2452faf8180bSLudovic Desroches case 0x300:
2453fe6e1471SJiapeng Zhong host->caps.has_dma_conf_reg = true;
2454fe6e1471SJiapeng Zhong host->caps.has_pdc = false;
2455fe6e1471SJiapeng Zhong host->caps.has_cfg_reg = true;
2456fe6e1471SJiapeng Zhong host->caps.has_cstor_reg = true;
2457fe6e1471SJiapeng Zhong host->caps.has_highspeed = true;
2458df561f66SGustavo A. R. Silva fallthrough;
2459faf8180bSLudovic Desroches case 0x200:
2460fe6e1471SJiapeng Zhong host->caps.has_rwproof = true;
2461fe6e1471SJiapeng Zhong host->caps.need_blksz_mul_4 = false;
2462fe6e1471SJiapeng Zhong host->caps.need_notbusy_for_read_ops = true;
2463df561f66SGustavo A. R. Silva fallthrough;
2464faf8180bSLudovic Desroches case 0x100:
2465fe6e1471SJiapeng Zhong host->caps.has_bad_data_ordering = false;
2466fe6e1471SJiapeng Zhong host->caps.need_reset_after_xfer = false;
2467df561f66SGustavo A. R. Silva fallthrough;
246824011f34SLudovic Desroches case 0x0:
2469796211b7SLudovic Desroches break;
2470796211b7SLudovic Desroches default:
2471fe6e1471SJiapeng Zhong host->caps.has_pdc = false;
2472796211b7SLudovic Desroches dev_warn(&host->pdev->dev,
2473796211b7SLudovic Desroches "Unmanaged mci version, set minimum capabilities\n");
2474796211b7SLudovic Desroches break;
2475796211b7SLudovic Desroches }
2476796211b7SLudovic Desroches }
247774465b4fSDan Williams
atmci_probe(struct platform_device * pdev)2478ab050b92Sludovic.desroches@atmel.com static int atmci_probe(struct platform_device *pdev)
24797d2be074SHaavard Skinnemoen {
24807d2be074SHaavard Skinnemoen struct mci_platform_data *pdata;
24817d2be074SHaavard Skinnemoen struct atmel_mci *host;
24827d2be074SHaavard Skinnemoen struct resource *regs;
2483965ebf33SHaavard Skinnemoen unsigned int nr_slots;
24847d2be074SHaavard Skinnemoen int irq;
2485528bc780SPramod Gurav int ret, i;
24867d2be074SHaavard Skinnemoen
24877d2be074SHaavard Skinnemoen regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
24887d2be074SHaavard Skinnemoen if (!regs)
24897d2be074SHaavard Skinnemoen return -ENXIO;
24907d2be074SHaavard Skinnemoen pdata = pdev->dev.platform_data;
2491e919fd20SLudovic Desroches if (!pdata) {
2492e919fd20SLudovic Desroches pdata = atmci_of_init(pdev);
2493e919fd20SLudovic Desroches if (IS_ERR(pdata)) {
2494e919fd20SLudovic Desroches dev_err(&pdev->dev, "platform data not available\n");
2495e919fd20SLudovic Desroches return PTR_ERR(pdata);
2496e919fd20SLudovic Desroches }
2497e919fd20SLudovic Desroches }
2498e919fd20SLudovic Desroches
24997d2be074SHaavard Skinnemoen irq = platform_get_irq(pdev, 0);
25007d2be074SHaavard Skinnemoen if (irq < 0)
25017d2be074SHaavard Skinnemoen return irq;
25027d2be074SHaavard Skinnemoen
25037bca646eSPramod Gurav host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
2504965ebf33SHaavard Skinnemoen if (!host)
25057d2be074SHaavard Skinnemoen return -ENOMEM;
25067d2be074SHaavard Skinnemoen
25077d2be074SHaavard Skinnemoen host->pdev = pdev;
2508965ebf33SHaavard Skinnemoen spin_lock_init(&host->lock);
2509965ebf33SHaavard Skinnemoen INIT_LIST_HEAD(&host->queue);
25107d2be074SHaavard Skinnemoen
25117bca646eSPramod Gurav host->mck = devm_clk_get(&pdev->dev, "mci_clk");
25127bca646eSPramod Gurav if (IS_ERR(host->mck))
25137bca646eSPramod Gurav return PTR_ERR(host->mck);
25147d2be074SHaavard Skinnemoen
25157bca646eSPramod Gurav host->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
25167d2be074SHaavard Skinnemoen if (!host->regs)
25177bca646eSPramod Gurav return -ENOMEM;
25187d2be074SHaavard Skinnemoen
2519b3894f26SBoris BREZILLON ret = clk_prepare_enable(host->mck);
2520b3894f26SBoris BREZILLON if (ret)
25217bca646eSPramod Gurav return ret;
25227bca646eSPramod Gurav
252303fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
25247d2be074SHaavard Skinnemoen host->bus_hz = clk_get_rate(host->mck);
25257d2be074SHaavard Skinnemoen
25267d2be074SHaavard Skinnemoen host->mapbase = regs->start;
25277d2be074SHaavard Skinnemoen
252882a5d372SEmil Renner Berthing tasklet_setup(&host->tasklet, atmci_tasklet_func);
25297d2be074SHaavard Skinnemoen
253089c8aa20SKay Sievers ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
2531ae552ab0SWenyou Yang if (ret) {
2532ae552ab0SWenyou Yang clk_disable_unprepare(host->mck);
25337bca646eSPramod Gurav return ret;
2534ae552ab0SWenyou Yang }
25357d2be074SHaavard Skinnemoen
2536796211b7SLudovic Desroches /* Get MCI capabilities and set operations according to it */
2537796211b7SLudovic Desroches atmci_get_cap(host);
2538467e081dSludovic.desroches@atmel.com ret = atmci_configure_dma(host);
2539467e081dSludovic.desroches@atmel.com if (ret == -EPROBE_DEFER)
2540467e081dSludovic.desroches@atmel.com goto err_dma_probe_defer;
2541467e081dSludovic.desroches@atmel.com if (ret == 0) {
2542796211b7SLudovic Desroches host->prepare_data = &atmci_prepare_data_dma;
2543796211b7SLudovic Desroches host->submit_data = &atmci_submit_data_dma;
2544796211b7SLudovic Desroches host->stop_transfer = &atmci_stop_transfer_dma;
2545796211b7SLudovic Desroches } else if (host->caps.has_pdc) {
2546796211b7SLudovic Desroches dev_info(&pdev->dev, "using PDC\n");
2547796211b7SLudovic Desroches host->prepare_data = &atmci_prepare_data_pdc;
2548796211b7SLudovic Desroches host->submit_data = &atmci_submit_data_pdc;
2549796211b7SLudovic Desroches host->stop_transfer = &atmci_stop_transfer_pdc;
2550796211b7SLudovic Desroches } else {
2551ef878198SLudovic Desroches dev_info(&pdev->dev, "using PIO\n");
2552796211b7SLudovic Desroches host->prepare_data = &atmci_prepare_data;
2553796211b7SLudovic Desroches host->submit_data = &atmci_submit_data;
2554796211b7SLudovic Desroches host->stop_transfer = &atmci_stop_transfer;
2555796211b7SLudovic Desroches }
2556796211b7SLudovic Desroches
25577d2be074SHaavard Skinnemoen platform_set_drvdata(pdev, host);
25587d2be074SHaavard Skinnemoen
25592ee4f620SKees Cook timer_setup(&host->timer, atmci_timeout_timer, 0);
2560b87cc1b5SLudovic Desroches
2561ae552ab0SWenyou Yang pm_runtime_get_noresume(&pdev->dev);
2562ae552ab0SWenyou Yang pm_runtime_set_active(&pdev->dev);
2563ae552ab0SWenyou Yang pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_DELAY);
2564ae552ab0SWenyou Yang pm_runtime_use_autosuspend(&pdev->dev);
2565ae552ab0SWenyou Yang pm_runtime_enable(&pdev->dev);
2566ae552ab0SWenyou Yang
2567965ebf33SHaavard Skinnemoen /* We need at least one slot to succeed */
2568965ebf33SHaavard Skinnemoen nr_slots = 0;
2569965ebf33SHaavard Skinnemoen ret = -ENODEV;
2570965ebf33SHaavard Skinnemoen if (pdata->slot[0].bus_width) {
2571965ebf33SHaavard Skinnemoen ret = atmci_init_slot(host, &pdata->slot[0],
25722c96a293SLudovic Desroches 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
25737a90dcc2SLudovic Desroches if (!ret) {
2574965ebf33SHaavard Skinnemoen nr_slots++;
25757a90dcc2SLudovic Desroches host->buf_size = host->slot[0]->mmc->max_req_size;
25767a90dcc2SLudovic Desroches }
25777d2be074SHaavard Skinnemoen }
2578965ebf33SHaavard Skinnemoen if (pdata->slot[1].bus_width) {
2579965ebf33SHaavard Skinnemoen ret = atmci_init_slot(host, &pdata->slot[1],
25802c96a293SLudovic Desroches 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
25817a90dcc2SLudovic Desroches if (!ret) {
2582965ebf33SHaavard Skinnemoen nr_slots++;
25837a90dcc2SLudovic Desroches if (host->slot[1]->mmc->max_req_size > host->buf_size)
25847a90dcc2SLudovic Desroches host->buf_size =
25857a90dcc2SLudovic Desroches host->slot[1]->mmc->max_req_size;
25867a90dcc2SLudovic Desroches }
25877d2be074SHaavard Skinnemoen }
25887d2be074SHaavard Skinnemoen
258904d699c3SRob Emanuele if (!nr_slots) {
259004d699c3SRob Emanuele dev_err(&pdev->dev, "init failed: no slot defined\n");
2591965ebf33SHaavard Skinnemoen goto err_init_slot;
259204d699c3SRob Emanuele }
25937d2be074SHaavard Skinnemoen
25947a90dcc2SLudovic Desroches if (!host->caps.has_rwproof) {
25957a90dcc2SLudovic Desroches host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size,
25967a90dcc2SLudovic Desroches &host->buf_phys_addr,
25977a90dcc2SLudovic Desroches GFP_KERNEL);
25987a90dcc2SLudovic Desroches if (!host->buffer) {
25997a90dcc2SLudovic Desroches ret = -ENOMEM;
26007a90dcc2SLudovic Desroches dev_err(&pdev->dev, "buffer allocation failed\n");
2601528bc780SPramod Gurav goto err_dma_alloc;
26027a90dcc2SLudovic Desroches }
26037a90dcc2SLudovic Desroches }
26047a90dcc2SLudovic Desroches
2605965ebf33SHaavard Skinnemoen dev_info(&pdev->dev,
2606965ebf33SHaavard Skinnemoen "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2607965ebf33SHaavard Skinnemoen host->mapbase, irq, nr_slots);
2608deec9ae3SHaavard Skinnemoen
2609ae552ab0SWenyou Yang pm_runtime_mark_last_busy(&host->pdev->dev);
2610ae552ab0SWenyou Yang pm_runtime_put_autosuspend(&pdev->dev);
2611ae552ab0SWenyou Yang
26127d2be074SHaavard Skinnemoen return 0;
26137d2be074SHaavard Skinnemoen
2614528bc780SPramod Gurav err_dma_alloc:
2615528bc780SPramod Gurav for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2616528bc780SPramod Gurav if (host->slot[i])
2617528bc780SPramod Gurav atmci_cleanup_slot(host->slot[i], i);
2618528bc780SPramod Gurav }
2619965ebf33SHaavard Skinnemoen err_init_slot:
2620ae552ab0SWenyou Yang clk_disable_unprepare(host->mck);
2621ae552ab0SWenyou Yang
2622ae552ab0SWenyou Yang pm_runtime_disable(&pdev->dev);
2623ae552ab0SWenyou Yang pm_runtime_put_noidle(&pdev->dev);
2624ae552ab0SWenyou Yang
2625528bc780SPramod Gurav del_timer_sync(&host->timer);
2626467e081dSludovic.desroches@atmel.com if (!IS_ERR(host->dma.chan))
262774465b4fSDan Williams dma_release_channel(host->dma.chan);
2628467e081dSludovic.desroches@atmel.com err_dma_probe_defer:
2629965ebf33SHaavard Skinnemoen free_irq(irq, host);
26307d2be074SHaavard Skinnemoen return ret;
26317d2be074SHaavard Skinnemoen }
26327d2be074SHaavard Skinnemoen
atmci_remove(struct platform_device * pdev)2633ee65ea2bSYangtao Li static void atmci_remove(struct platform_device *pdev)
26347d2be074SHaavard Skinnemoen {
26357d2be074SHaavard Skinnemoen struct atmel_mci *host = platform_get_drvdata(pdev);
2636965ebf33SHaavard Skinnemoen unsigned int i;
26377d2be074SHaavard Skinnemoen
2638ae552ab0SWenyou Yang pm_runtime_get_sync(&pdev->dev);
2639ae552ab0SWenyou Yang
26407a90dcc2SLudovic Desroches if (host->buffer)
26417a90dcc2SLudovic Desroches dma_free_coherent(&pdev->dev, host->buf_size,
26427a90dcc2SLudovic Desroches host->buffer, host->buf_phys_addr);
26437a90dcc2SLudovic Desroches
26442c96a293SLudovic Desroches for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2645965ebf33SHaavard Skinnemoen if (host->slot[i])
2646965ebf33SHaavard Skinnemoen atmci_cleanup_slot(host->slot[i], i);
26477d2be074SHaavard Skinnemoen }
26487d2be074SHaavard Skinnemoen
264903fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_IDR, ~0UL);
265003fc9a7fSLudovic Desroches atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
265103fc9a7fSLudovic Desroches atmci_readl(host, ATMCI_SR);
26527d2be074SHaavard Skinnemoen
2653528bc780SPramod Gurav del_timer_sync(&host->timer);
2654467e081dSludovic.desroches@atmel.com if (!IS_ERR(host->dma.chan))
265574465b4fSDan Williams dma_release_channel(host->dma.chan);
265665e8b083SHaavard Skinnemoen
2657965ebf33SHaavard Skinnemoen free_irq(platform_get_irq(pdev, 0), host);
26587d2be074SHaavard Skinnemoen
2659ae552ab0SWenyou Yang clk_disable_unprepare(host->mck);
2660ae552ab0SWenyou Yang
2661ae552ab0SWenyou Yang pm_runtime_disable(&pdev->dev);
2662ae552ab0SWenyou Yang pm_runtime_put_noidle(&pdev->dev);
26637d2be074SHaavard Skinnemoen }
26647d2be074SHaavard Skinnemoen
2665ae552ab0SWenyou Yang #ifdef CONFIG_PM
atmci_runtime_suspend(struct device * dev)2666ae552ab0SWenyou Yang static int atmci_runtime_suspend(struct device *dev)
2667ae552ab0SWenyou Yang {
2668ae552ab0SWenyou Yang struct atmel_mci *host = dev_get_drvdata(dev);
2669ae552ab0SWenyou Yang
2670ae552ab0SWenyou Yang clk_disable_unprepare(host->mck);
2671ae552ab0SWenyou Yang
2672b5b64fa6SWenyou Yang pinctrl_pm_select_sleep_state(dev);
2673b5b64fa6SWenyou Yang
2674ae552ab0SWenyou Yang return 0;
2675ae552ab0SWenyou Yang }
2676ae552ab0SWenyou Yang
atmci_runtime_resume(struct device * dev)2677ae552ab0SWenyou Yang static int atmci_runtime_resume(struct device *dev)
2678ae552ab0SWenyou Yang {
2679ae552ab0SWenyou Yang struct atmel_mci *host = dev_get_drvdata(dev);
2680ae552ab0SWenyou Yang
26816986ee3fSUlf Hansson pinctrl_select_default_state(dev);
2682b5b64fa6SWenyou Yang
2683ae552ab0SWenyou Yang return clk_prepare_enable(host->mck);
2684ae552ab0SWenyou Yang }
2685ae552ab0SWenyou Yang #endif
2686ae552ab0SWenyou Yang
2687ae552ab0SWenyou Yang static const struct dev_pm_ops atmci_dev_pm_ops = {
2688ae552ab0SWenyou Yang SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2689ae552ab0SWenyou Yang pm_runtime_force_resume)
2690c3cb6ba4SLudovic Desroches SET_RUNTIME_PM_OPS(atmci_runtime_suspend, atmci_runtime_resume, NULL)
2691ae552ab0SWenyou Yang };
2692ae552ab0SWenyou Yang
26937d2be074SHaavard Skinnemoen static struct platform_driver atmci_driver = {
26945e0fe897Sludovic.desroches@atmel.com .probe = atmci_probe,
2695ee65ea2bSYangtao Li .remove_new = atmci_remove,
26967d2be074SHaavard Skinnemoen .driver = {
26977d2be074SHaavard Skinnemoen .name = "atmel_mci",
269821b2cec6SDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS,
2699e919fd20SLudovic Desroches .of_match_table = of_match_ptr(atmci_dt_ids),
2700ae552ab0SWenyou Yang .pm = &atmci_dev_pm_ops,
27017d2be074SHaavard Skinnemoen },
27027d2be074SHaavard Skinnemoen };
27035e0fe897Sludovic.desroches@atmel.com module_platform_driver(atmci_driver);
27047d2be074SHaavard Skinnemoen
27057d2be074SHaavard Skinnemoen MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
2706e05503efSJean Delvare MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
27077d2be074SHaavard Skinnemoen MODULE_LICENSE("GPL v2");
2708