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/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dspi-zynqmp-qspi.yaml61 interrupts = <0 15 4>;
63 reg = <0x0 0xff0f0000 0x0 0x1000>,
64 <0x0 0xc0000000 0x0 0x8000000>;
/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp-mini-qspi.dts30 reg = <0x0 0xfffc0000 0x40000>;
51 reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>;
53 #size-cells = <0>;
58 #clock-cells = <0>;
66 flash@0 {
70 reg = <0x0>;
H A Dzynqmp.dtsi22 #size-cells = <0>;
24 cpu0: cpu@0 {
29 reg = <0x0>;
37 reg = <0x1>;
46 reg = <0x2>;
55 reg = <0x3>;
63 CPU_SLEEP_0: cpu-sleep-0 {
65 arm,psci-suspend-param = <0x40000000>;
108 interrupts = <0 143 4>,
109 <0 144 4>,
[all …]
H A Drk3368.dtsi76 #address-cells = <0x2>;
77 #size-cells = <0x0>;
114 cpu_sleep: cpu-sleep-0 {
116 arm,psci-suspend-param = <0x1010000>;
117 entry-latency-us = <0x3fffffff>;
118 exit-latency-us = <0x40000000>;
119 min-residency-us = <0xffffffff>;
123 cpu_l0: cpu@0 {
126 reg = <0x0 0x0>;
136 reg = <0x0 0x1>;
[all …]
H A Drk3288.dtsi53 #size-cells = <0>;
60 reg = <0x500>;
85 reg = <0x501>;
91 reg = <0x502>;
97 reg = <0x503>;
111 reg = <0xff250000 0x4000>;
122 reg = <0xff600000 0x4000>;
123 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
134 reg = <0xffb20000 0x4000>;
135 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
[all …]
/openbmc/linux/arch/arm/mm/
H A Dcache-tauros2.c44 __asm__("mcr p15, 1, %0, c7, c11, 3" : : "r" (addr)); in tauros2_clean_pa()
49 __asm__("mcr p15, 1, %0, c7, c15, 3" : : "r" (addr)); in tauros2_clean_inv_pa()
54 __asm__("mcr p15, 1, %0, c7, c7, 3" : : "r" (addr)); in tauros2_inv_pa()
120 "mcr p15, 1, %0, c7, c11, 0 @L2 Cache Clean All\n\t" in tauros2_disable()
121 "mrc p15, 0, %0, c1, c0, 0\n\t" in tauros2_disable()
122 "bic %0, %0, #(1 << 26)\n\t" in tauros2_disable()
123 "mcr p15, 0, %0, c1, c0, 0 @Disable L2 Cache\n\t" in tauros2_disable()
124 : : "r" (0x0)); in tauros2_disable()
130 "mcr p15, 1, %0, c7, c7, 0 @L2 Cache Invalidate All\n\t" in tauros2_resume()
131 "mrc p15, 0, %0, c1, c0, 0\n\t" in tauros2_resume()
[all …]
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_axp.h9 #define MV_78XX0_Z1_REV 0x0
10 #define MV_78XX0_A0_REV 0x1
11 #define MV_78XX0_B0_REV 0x2
13 #define SAR_DDR3_FREQ_MASK 0xFE00000
14 #define SAR_CPU_FAB_GET(cpu, fab) (((cpu & 0x7) << 21) | ((fab & 0xF) << 24))
18 #define MIN_DIMM_ADDR 0x50
19 #define FAR_END_DIMM_ADDR 0x50
20 #define MAX_DIMM_ADDR 0x60
23 #define SDRAM_CS_SIZE 0xFFFFFFF
27 #define SDRAM_CS_BASE 0x0
[all …]
/openbmc/qemu/hw/arm/
H A Dxlnx-zynqmp.c39 #define GEM_REVISION 0x40070106
41 #define GIC_BASE_ADDR 0xf9000000
42 #define GIC_DIST_ADDR 0xf9010000
43 #define GIC_CPU_ADDR 0xf9020000
44 #define GIC_VIFACE_ADDR 0xf9040000
45 #define GIC_VCPU_ADDR 0xf9060000
48 #define SATA_ADDR 0xFD0C0000
51 #define QSPI_ADDR 0xff0f0000
52 #define LQSPI_ADDR 0xc0000000
54 #define QSPI_DMA_ADDR 0xff0f0800
[all …]
/openbmc/linux/drivers/net/ethernet/microchip/
H A Dlan743x_main.h15 #define ID_REV (0x00)
16 #define ID_REV_ID_MASK_ (0xFFFF0000)
17 #define ID_REV_ID_LAN7430_ (0x74300000)
18 #define ID_REV_ID_LAN7431_ (0x74310000)
19 #define ID_REV_ID_LAN743X_ (0x74300000)
20 #define ID_REV_ID_A011_ (0xA0110000) // PCI11010
21 #define ID_REV_ID_A041_ (0xA0410000) // PCI11414
22 #define ID_REV_ID_A0X1_ (0xA0010000)
24 ((((id_rev) & 0xFFF00000) == ID_REV_ID_LAN743X_) || \
25 (((id_rev) & 0xFF0F0000) == ID_REV_ID_A0X1_))
[all …]
/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp.dtsi29 #size-cells = <0>;
31 cpu0: cpu@0 {
36 reg = <0x0>;
45 reg = <0x1>;
55 reg = <0x2>;
65 reg = <0x3>;
80 CPU_SLEEP_0: cpu-sleep-0 {
82 arm,psci-suspend-param = <0x40000000>;
123 reg = <0x0 0x3ed00000 0x0 0x40000>;
128 reg = <0x0 0x3ef00000 0x0 0x40000>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3368.dtsi40 #address-cells = <0x2>;
41 #size-cells = <0x0>;
75 cpu_l0: cpu@0 {
78 reg = <0x0 0x0>;
86 reg = <0x0 0x1>;
94 reg = <0x0 0x2>;
102 reg = <0x0 0x3>;
110 reg = <0x0 0x100>;
118 reg = <0x0 0x101>;
126 reg = <0x0 0x102>;
[all …]
/openbmc/linux/arch/arm/boot/compressed/
H A Dhead.S15 #define OF_DT_MAGIC 0xd00dfeed
17 #define OF_DT_MAGIC 0xedfe0dd0
38 mcr p14, 0, \ch, c0, c5, 0
44 mcr p14, 0, \ch, c8, c0, 0
50 mcr p14, 0, \ch, c1, c0, 0
69 mov \rb, #0x80000000 @ physical base address
70 add \rb, \rb, #0x00010000 @ Ser1
98 kputc #'0'
102 kputc #'0'
107 kputc #'0'
[all …]
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3288.dtsi53 #size-cells = <0>;
60 reg = <0x500>;
71 reg = <0x501>;
82 reg = <0x502>;
93 reg = <0x503>;
103 cpu_opp_table: opp-table-0 {
163 * The rk3288 cannot use the memory area above 0xfe000000
173 reg = <0x0 0xfe000000 0x0 0x1000000>;
181 #clock-cells = <0>;
197 reg = <0x0 0xff810000 0x0 0x20>;
[all …]