Lines Matching +full:0 +full:xff0f0000
40 #address-cells = <0x2>;
41 #size-cells = <0x0>;
75 cpu_l0: cpu@0 {
78 reg = <0x0 0x0>;
86 reg = <0x0 0x1>;
94 reg = <0x0 0x2>;
102 reg = <0x0 0x3>;
110 reg = <0x0 0x100>;
118 reg = <0x0 0x101>;
126 reg = <0x0 0x102>;
134 reg = <0x0 0x103>;
176 #clock-cells = <0>;
181 reg = <0x0 0xff0c0000 0x0 0x4000>;
186 fifo-depth = <0x100>;
195 reg = <0x0 0xff0d0000 0x0 0x4000>;
200 fifo-depth = <0x100>;
209 reg = <0x0 0xff0f0000 0x0 0x4000>;
214 fifo-depth = <0x100>;
223 reg = <0x0 0xff100000 0x0 0x100>;
235 reg = <0x0 0xff110000 0x0 0x1000>;
240 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
242 #size-cells = <0>;
248 reg = <0x0 0xff120000 0x0 0x1000>;
253 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
255 #size-cells = <0>;
261 reg = <0x0 0xff130000 0x0 0x1000>;
266 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
268 #size-cells = <0>;
274 reg = <0x0 0xff140000 0x0 0x1000>;
277 #size-cells = <0>;
281 pinctrl-0 = <&i2c2_xfer>;
287 reg = <0x0 0xff150000 0x0 0x1000>;
290 #size-cells = <0>;
294 pinctrl-0 = <&i2c3_xfer>;
300 reg = <0x0 0xff160000 0x0 0x1000>;
303 #size-cells = <0>;
307 pinctrl-0 = <&i2c4_xfer>;
313 reg = <0x0 0xff170000 0x0 0x1000>;
316 #size-cells = <0>;
320 pinctrl-0 = <&i2c5_xfer>;
326 reg = <0x0 0xff180000 0x0 0x100>;
338 reg = <0x0 0xff190000 0x0 0x100>;
350 reg = <0x0 0xff1b0000 0x0 0x100>;
362 reg = <0x0 0xff1c0000 0x0 0x100>;
374 reg = <0x0 0xff250000 0x0 0x4000>;
389 thermal-sensors = <&tsadc 0>;
463 reg = <0x0 0xff280000 0x0 0x100>;
470 pinctrl-0 = <&otp_pin>;
480 reg = <0x0 0xff290000 0x0 0x10000>;
497 reg = <0x0 0xff500000 0x0 0x100>;
506 reg = <0x0 0xff580000 0x0 0x40000>;
519 reg = <0x0 0xff600000 0x0 0x4000>;
520 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
531 reg = <0x0 0xff650000 0x0 0x1000>;
536 pinctrl-0 = <&i2c0_xfer>;
538 #size-cells = <0>;
544 reg = <0x0 0xff660000 0x0 0x1000>;
547 #size-cells = <0>;
551 pinctrl-0 = <&i2c1_xfer>;
557 reg = <0x0 0xff680000 0x0 0x10>;
560 pinctrl-0 = <&pwm0_pin>;
567 reg = <0x0 0xff680010 0x0 0x10>;
570 pinctrl-0 = <&pwm1_pin>;
577 reg = <0x0 0xff680020 0x0 0x10>;
585 reg = <0x0 0xff680030 0x0 0x10>;
588 pinctrl-0 = <&pwm3_pin>;
595 reg = <0x0 0xff690000 0x0 0x100>;
600 pinctrl-0 = <&uart2_xfer>;
608 reg = <0x0 0xff6b0000 0x0 0x1000>;
621 reg = <0x0 0xff730000 0x0 0x1000>;
627 #size-cells = <0>;
693 #power-domain-cells = <0>;
710 #power-domain-cells = <0>;
723 #power-domain-cells = <0>;
730 reg = <0x0 0xff738000 0x0 0x1000>;
739 offset = <0x200>;
749 reg = <0x0 0xff760000 0x0 0x1000>;
759 reg = <0x0 0xff770000 0x0 0x1000>;
769 reg = <0x0 0xff800000 0x0 0x100>;
777 reg = <0x0 0xff810000 0x0 0x20>;
785 reg = <0x0 0xff880000 0x0 0x1000>;
792 pinctrl-0 = <&spdif_tx>;
793 #sound-dai-cells = <0>;
799 reg = <0x0 0xff890000 0x0 0x1000>;
805 #sound-dai-cells = <0>;
811 reg = <0x0 0xff898000 0x0 0x1000>;
815 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
818 pinctrl-0 = <&i2s_8ch_bus>;
819 #sound-dai-cells = <0>;
825 reg = <0x0 0xff900800 0x0 0x100>;
830 #iommu-cells = <0>;
836 reg = <0x0 0xff914000 0x0 0x100>,
837 <0x0 0xff915000 0x0 0x100>;
841 #iommu-cells = <0>;
849 reg = <0x0 0xff930300 0x0 0x100>;
854 #iommu-cells = <0>;
860 reg = <0x0 0xff9a0440 0x0 0x40>,
861 <0x0 0xff9a0480 0x0 0x40>;
865 #iommu-cells = <0>;
871 reg = <0x0 0xff9a0800 0x0 0x100>;
876 #iommu-cells = <0>;
882 reg = <0x0 0xffad0000 0x0 0x20>;
887 reg = <0x0 0xffad0080 0x0 0x20>;
892 reg = <0x0 0xffad0100 0x0 0x20>;
897 reg = <0x0 0xffad0180 0x0 0x20>;
902 reg = <0x0 0xffad0200 0x0 0x20>;
907 reg = <0x0 0xffad0280 0x0 0x20>;
912 reg = <0x0 0xffad0300 0x0 0x20>;
917 reg = <0x0 0xffad0380 0x0 0x20>;
922 reg = <0x0 0xffad0400 0x0 0x20>;
927 reg = <0x0 0xffae0000 0x0 0x20>;
932 reg = <0x0 0xffae0100 0x0 0x20>;
937 reg = <0x0 0xffae0180 0x0 0x20>;
942 reg = <0x0 0xffaf0000 0x0 0x20>;
947 reg = <0x0 0xffb00000 0x0 0x20>;
954 reg = <0x17 0x1>;
957 reg = <0x1f 0x1>;
965 #address-cells = <0>;
967 reg = <0x0 0xffb71000 0x0 0x1000>,
968 <0x0 0xffb72000 0x0 0x2000>,
969 <0x0 0xffb74000 0x0 0x2000>,
970 <0x0 0xffb76000 0x0 0x2000>;
979 #address-cells = <0x2>;
980 #size-cells = <0x2>;
985 reg = <0x0 0xff750000 0x0 0x100>;
987 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
990 #gpio-cells = <0x2>;
993 #interrupt-cells = <0x2>;
998 reg = <0x0 0xff780000 0x0 0x100>;
1000 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
1003 #gpio-cells = <0x2>;
1006 #interrupt-cells = <0x2>;
1011 reg = <0x0 0xff790000 0x0 0x100>;
1013 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
1016 #gpio-cells = <0x2>;
1019 #interrupt-cells = <0x2>;
1024 reg = <0x0 0xff7a0000 0x0 0x100>;
1026 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
1029 #gpio-cells = <0x2>;
1032 #interrupt-cells = <0x2>;
1123 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>,
1124 <0 RK_PA7 1 &pcfg_pull_none>;
1137 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_none>,
1185 rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>;
1305 rockchip,pins = <0 RK_PB4 2 &pcfg_pull_up>;
1308 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>;
1311 rockchip,pins = <0 RK_PB2 2 &pcfg_pull_up>;
1314 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>;
1320 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
1324 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1345 rockchip,pins = <0 RK_PC4 3 &pcfg_pull_up>,
1346 <0 RK_PC5 3 &pcfg_pull_none>;
1350 rockchip,pins = <0 RK_PC6 3 &pcfg_pull_none>;
1354 rockchip,pins = <0 RK_PC7 3 &pcfg_pull_none>;
1383 rockchip,pins = <0 RK_PD3 3 &pcfg_pull_up>,
1384 <0 RK_PD2 3 &pcfg_pull_none>;
1388 rockchip,pins = <0 RK_PD0 3 &pcfg_pull_none>;
1392 rockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>;