123f0703cSBryan Whitehead /* SPDX-License-Identifier: GPL-2.0+ */ 223f0703cSBryan Whitehead /* Copyright (C) 2018 Microchip Technology Inc. */ 323f0703cSBryan Whitehead 423f0703cSBryan Whitehead #ifndef _LAN743X_H 523f0703cSBryan Whitehead #define _LAN743X_H 623f0703cSBryan Whitehead 76f197fb6SRoelof Berg #include <linux/phy.h> 807624df1SBryan Whitehead #include "lan743x_ptp.h" 907624df1SBryan Whitehead 1023f0703cSBryan Whitehead #define DRIVER_AUTHOR "Bryan Whitehead <Bryan.Whitehead@microchip.com>" 1123f0703cSBryan Whitehead #define DRIVER_DESC "LAN743x PCIe Gigabit Ethernet Driver" 1223f0703cSBryan Whitehead #define DRIVER_NAME "lan743x" 1323f0703cSBryan Whitehead 1423f0703cSBryan Whitehead /* Register Definitions */ 1523f0703cSBryan Whitehead #define ID_REV (0x00) 1607624df1SBryan Whitehead #define ID_REV_ID_MASK_ (0xFFFF0000) 1707624df1SBryan Whitehead #define ID_REV_ID_LAN7430_ (0x74300000) 1807624df1SBryan Whitehead #define ID_REV_ID_LAN7431_ (0x74310000) 19bb4f6bffSRaju Lakkaraju #define ID_REV_ID_LAN743X_ (0x74300000) 20bb4f6bffSRaju Lakkaraju #define ID_REV_ID_A011_ (0xA0110000) // PCI11010 21bb4f6bffSRaju Lakkaraju #define ID_REV_ID_A041_ (0xA0410000) // PCI11414 22bb4f6bffSRaju Lakkaraju #define ID_REV_ID_A0X1_ (0xA0010000) 2323f0703cSBryan Whitehead #define ID_REV_IS_VALID_CHIP_ID_(id_rev) \ 24bb4f6bffSRaju Lakkaraju ((((id_rev) & 0xFFF00000) == ID_REV_ID_LAN743X_) || \ 25bb4f6bffSRaju Lakkaraju (((id_rev) & 0xFF0F0000) == ID_REV_ID_A0X1_)) 2623f0703cSBryan Whitehead #define ID_REV_CHIP_REV_MASK_ (0x0000FFFF) 2723f0703cSBryan Whitehead #define ID_REV_CHIP_REV_A0_ (0x00000000) 2823f0703cSBryan Whitehead #define ID_REV_CHIP_REV_B0_ (0x00000010) 2974a78a00SRaju Lakkaraju #define ID_REV_CHIP_REV_PCI11X1X_B0_ (0x000000B0) 3023f0703cSBryan Whitehead 3123f0703cSBryan Whitehead #define FPGA_REV (0x04) 3223f0703cSBryan Whitehead #define FPGA_REV_GET_MINOR_(fpga_rev) (((fpga_rev) >> 8) & 0x000000FF) 3323f0703cSBryan Whitehead #define FPGA_REV_GET_MAJOR_(fpga_rev) ((fpga_rev) & 0x000000FF) 34a46d9d37SRaju Lakkaraju #define FPGA_SGMII_OP BIT(24) 35a46d9d37SRaju Lakkaraju 36a46d9d37SRaju Lakkaraju #define STRAP_READ (0x0C) 37a46d9d37SRaju Lakkaraju #define STRAP_READ_USE_SGMII_EN_ BIT(22) 38a46d9d37SRaju Lakkaraju #define STRAP_READ_SGMII_EN_ BIT(6) 39a46d9d37SRaju Lakkaraju #define STRAP_READ_SGMII_REFCLK_ BIT(5) 40a46d9d37SRaju Lakkaraju #define STRAP_READ_SGMII_2_5G_ BIT(4) 41a46d9d37SRaju Lakkaraju #define STRAP_READ_BASE_X_ BIT(3) 42a46d9d37SRaju Lakkaraju #define STRAP_READ_RGMII_TXC_DELAY_EN_ BIT(2) 43a46d9d37SRaju Lakkaraju #define STRAP_READ_RGMII_RXC_DELAY_EN_ BIT(1) 44a46d9d37SRaju Lakkaraju #define STRAP_READ_ADV_PM_DISABLE_ BIT(0) 4523f0703cSBryan Whitehead 4623f0703cSBryan Whitehead #define HW_CFG (0x010) 476b3768acSRaju Lakkaraju #define HW_CFG_RST_PROTECT_PCIE_ BIT(19) 486b3768acSRaju Lakkaraju #define HW_CFG_HOT_RESET_DIS_ BIT(15) 496b3768acSRaju Lakkaraju #define HW_CFG_D3_VAUX_OVR_ BIT(14) 506b3768acSRaju Lakkaraju #define HW_CFG_D3_RESET_DIS_ BIT(13) 516b3768acSRaju Lakkaraju #define HW_CFG_RST_PROTECT_ BIT(12) 52662a14d0SBryan Whitehead #define HW_CFG_RELOAD_TYPE_ALL_ (0x00000FC0) 53662a14d0SBryan Whitehead #define HW_CFG_EE_OTP_RELOAD_ BIT(4) 5423f0703cSBryan Whitehead #define HW_CFG_LRST_ BIT(1) 5523f0703cSBryan Whitehead 5623f0703cSBryan Whitehead #define PMT_CTL (0x014) 574d94282aSBryan Whitehead #define PMT_CTL_ETH_PHY_D3_COLD_OVR_ BIT(27) 584d94282aSBryan Whitehead #define PMT_CTL_MAC_D3_RX_CLK_OVR_ BIT(25) 594d94282aSBryan Whitehead #define PMT_CTL_ETH_PHY_EDPD_PLL_CTL_ BIT(24) 604d94282aSBryan Whitehead #define PMT_CTL_ETH_PHY_D3_OVR_ BIT(23) 614d94282aSBryan Whitehead #define PMT_CTL_RX_FCT_RFE_D3_CLK_OVR_ BIT(18) 624d94282aSBryan Whitehead #define PMT_CTL_GPIO_WAKEUP_EN_ BIT(15) 634d94282aSBryan Whitehead #define PMT_CTL_EEE_WAKEUP_EN_ BIT(13) 6441805c46SRaju Lakkaraju #define PMT_CTL_RES_CLR_WKP_MASK_ GENMASK(9, 8) 6523f0703cSBryan Whitehead #define PMT_CTL_READY_ BIT(7) 6623f0703cSBryan Whitehead #define PMT_CTL_ETH_PHY_RST_ BIT(4) 674d94282aSBryan Whitehead #define PMT_CTL_WOL_EN_ BIT(3) 684d94282aSBryan Whitehead #define PMT_CTL_ETH_PHY_WAKE_EN_ BIT(2) 694d94282aSBryan Whitehead #define PMT_CTL_WUPS_MASK_ (0x00000003) 7023f0703cSBryan Whitehead 7123f0703cSBryan Whitehead #define DP_SEL (0x024) 7223f0703cSBryan Whitehead #define DP_SEL_DPRDY_ BIT(31) 7323f0703cSBryan Whitehead #define DP_SEL_MASK_ (0x0000001F) 7423f0703cSBryan Whitehead #define DP_SEL_RFE_RAM (0x00000001) 7523f0703cSBryan Whitehead 7623f0703cSBryan Whitehead #define DP_SEL_VHF_HASH_LEN (16) 7723f0703cSBryan Whitehead #define DP_SEL_VHF_VLAN_LEN (128) 7823f0703cSBryan Whitehead 7923f0703cSBryan Whitehead #define DP_CMD (0x028) 8023f0703cSBryan Whitehead #define DP_CMD_WRITE_ (0x00000001) 8123f0703cSBryan Whitehead 8223f0703cSBryan Whitehead #define DP_ADDR (0x02C) 8323f0703cSBryan Whitehead 8423f0703cSBryan Whitehead #define DP_DATA_0 (0x030) 8523f0703cSBryan Whitehead 8669584604SBryan Whitehead #define E2P_CMD (0x040) 8769584604SBryan Whitehead #define E2P_CMD_EPC_BUSY_ BIT(31) 8869584604SBryan Whitehead #define E2P_CMD_EPC_CMD_WRITE_ (0x30000000) 8969584604SBryan Whitehead #define E2P_CMD_EPC_CMD_EWEN_ (0x20000000) 9069584604SBryan Whitehead #define E2P_CMD_EPC_CMD_READ_ (0x00000000) 9169584604SBryan Whitehead #define E2P_CMD_EPC_TIMEOUT_ BIT(10) 9269584604SBryan Whitehead #define E2P_CMD_EPC_ADDR_MASK_ (0x000001FF) 9369584604SBryan Whitehead 9469584604SBryan Whitehead #define E2P_DATA (0x044) 9569584604SBryan Whitehead 96cdea83ccSRaju Lakkaraju /* Hearthstone top level & System Reg Addresses */ 97cdea83ccSRaju Lakkaraju #define ETH_CTRL_REG_ADDR_BASE (0x0000) 98cdea83ccSRaju Lakkaraju #define ETH_SYS_REG_ADDR_BASE (0x4000) 99cdea83ccSRaju Lakkaraju #define CONFIG_REG_ADDR_BASE (0x0000) 100cdea83ccSRaju Lakkaraju #define ETH_EEPROM_REG_ADDR_BASE (0x0E00) 101cdea83ccSRaju Lakkaraju #define ETH_OTP_REG_ADDR_BASE (0x1000) 10246b777adSRaju Lakkaraju #define GEN_SYS_CONFIG_LOAD_STARTED_REG (0x0078) 10346b777adSRaju Lakkaraju #define ETH_SYS_CONFIG_LOAD_STARTED_REG (ETH_SYS_REG_ADDR_BASE + \ 10446b777adSRaju Lakkaraju CONFIG_REG_ADDR_BASE + \ 10546b777adSRaju Lakkaraju GEN_SYS_CONFIG_LOAD_STARTED_REG) 10646b777adSRaju Lakkaraju #define GEN_SYS_LOAD_STARTED_REG_ETH_ BIT(4) 107cdea83ccSRaju Lakkaraju #define SYS_LOCK_REG (0x00A0) 108cdea83ccSRaju Lakkaraju #define SYS_LOCK_REG_MAIN_LOCK_ BIT(7) 109cdea83ccSRaju Lakkaraju #define SYS_LOCK_REG_GEN_PERI_LOCK_ BIT(5) 110cdea83ccSRaju Lakkaraju #define SYS_LOCK_REG_SPI_PERI_LOCK_ BIT(4) 111cdea83ccSRaju Lakkaraju #define SYS_LOCK_REG_SMBUS_PERI_LOCK_ BIT(3) 112cdea83ccSRaju Lakkaraju #define SYS_LOCK_REG_UART_SS_LOCK_ BIT(2) 113cdea83ccSRaju Lakkaraju #define SYS_LOCK_REG_ENET_SS_LOCK_ BIT(1) 114cdea83ccSRaju Lakkaraju #define SYS_LOCK_REG_USB_SS_LOCK_ BIT(0) 115cdea83ccSRaju Lakkaraju #define ETH_SYSTEM_SYS_LOCK_REG (ETH_SYS_REG_ADDR_BASE + \ 116cdea83ccSRaju Lakkaraju CONFIG_REG_ADDR_BASE + \ 117cdea83ccSRaju Lakkaraju SYS_LOCK_REG) 118cdea83ccSRaju Lakkaraju #define HS_EEPROM_REG_ADDR_BASE (ETH_SYS_REG_ADDR_BASE + \ 119cdea83ccSRaju Lakkaraju ETH_EEPROM_REG_ADDR_BASE) 120cdea83ccSRaju Lakkaraju #define HS_E2P_CMD (HS_EEPROM_REG_ADDR_BASE + 0x0000) 121cdea83ccSRaju Lakkaraju #define HS_E2P_CMD_EPC_BUSY_ BIT(31) 122cdea83ccSRaju Lakkaraju #define HS_E2P_CMD_EPC_CMD_WRITE_ GENMASK(29, 28) 123cdea83ccSRaju Lakkaraju #define HS_E2P_CMD_EPC_CMD_READ_ (0x0) 124cdea83ccSRaju Lakkaraju #define HS_E2P_CMD_EPC_TIMEOUT_ BIT(17) 125cdea83ccSRaju Lakkaraju #define HS_E2P_CMD_EPC_ADDR_MASK_ GENMASK(15, 0) 126cdea83ccSRaju Lakkaraju #define HS_E2P_DATA (HS_EEPROM_REG_ADDR_BASE + 0x0004) 127cdea83ccSRaju Lakkaraju #define HS_E2P_DATA_MASK_ GENMASK(7, 0) 128cdea83ccSRaju Lakkaraju #define HS_E2P_CFG (HS_EEPROM_REG_ADDR_BASE + 0x0008) 129cdea83ccSRaju Lakkaraju #define HS_E2P_CFG_I2C_PULSE_MASK_ GENMASK(19, 16) 130cdea83ccSRaju Lakkaraju #define HS_E2P_CFG_EEPROM_SIZE_SEL_ BIT(12) 131cdea83ccSRaju Lakkaraju #define HS_E2P_CFG_I2C_BAUD_RATE_MASK_ GENMASK(9, 8) 132cdea83ccSRaju Lakkaraju #define HS_E2P_CFG_TEST_EEPR_TO_BYP_ BIT(0) 133cdea83ccSRaju Lakkaraju #define HS_E2P_PAD_CTL (HS_EEPROM_REG_ADDR_BASE + 0x000C) 134cdea83ccSRaju Lakkaraju 13507624df1SBryan Whitehead #define GPIO_CFG0 (0x050) 13607624df1SBryan Whitehead #define GPIO_CFG0_GPIO_DIR_BIT_(bit) BIT(16 + (bit)) 13707624df1SBryan Whitehead #define GPIO_CFG0_GPIO_DATA_BIT_(bit) BIT(0 + (bit)) 13807624df1SBryan Whitehead 13907624df1SBryan Whitehead #define GPIO_CFG1 (0x054) 14007624df1SBryan Whitehead #define GPIO_CFG1_GPIOEN_BIT_(bit) BIT(16 + (bit)) 14107624df1SBryan Whitehead #define GPIO_CFG1_GPIOBUF_BIT_(bit) BIT(0 + (bit)) 14207624df1SBryan Whitehead 14307624df1SBryan Whitehead #define GPIO_CFG2 (0x058) 14407624df1SBryan Whitehead #define GPIO_CFG2_1588_POL_BIT_(bit) BIT(0 + (bit)) 14507624df1SBryan Whitehead 14607624df1SBryan Whitehead #define GPIO_CFG3 (0x05C) 14707624df1SBryan Whitehead #define GPIO_CFG3_1588_CH_SEL_BIT_(bit) BIT(16 + (bit)) 14807624df1SBryan Whitehead #define GPIO_CFG3_1588_OE_BIT_(bit) BIT(0 + (bit)) 14907624df1SBryan Whitehead 15023f0703cSBryan Whitehead #define FCT_RX_CTL (0xAC) 15123f0703cSBryan Whitehead #define FCT_RX_CTL_EN_(channel) BIT(28 + (channel)) 15223f0703cSBryan Whitehead #define FCT_RX_CTL_DIS_(channel) BIT(24 + (channel)) 15323f0703cSBryan Whitehead #define FCT_RX_CTL_RESET_(channel) BIT(20 + (channel)) 15423f0703cSBryan Whitehead 15523f0703cSBryan Whitehead #define FCT_TX_CTL (0xC4) 15623f0703cSBryan Whitehead #define FCT_TX_CTL_EN_(channel) BIT(28 + (channel)) 15723f0703cSBryan Whitehead #define FCT_TX_CTL_DIS_(channel) BIT(24 + (channel)) 15823f0703cSBryan Whitehead #define FCT_TX_CTL_RESET_(channel) BIT(20 + (channel)) 15923f0703cSBryan Whitehead 16023f0703cSBryan Whitehead #define FCT_FLOW(rx_channel) (0xE0 + ((rx_channel) << 2)) 16123f0703cSBryan Whitehead #define FCT_FLOW_CTL_OFF_THRESHOLD_ (0x00007F00) 16223f0703cSBryan Whitehead #define FCT_FLOW_CTL_OFF_THRESHOLD_SET_(value) \ 16323f0703cSBryan Whitehead ((value << 8) & FCT_FLOW_CTL_OFF_THRESHOLD_) 16423f0703cSBryan Whitehead #define FCT_FLOW_CTL_REQ_EN_ BIT(7) 16523f0703cSBryan Whitehead #define FCT_FLOW_CTL_ON_THRESHOLD_ (0x0000007F) 16623f0703cSBryan Whitehead #define FCT_FLOW_CTL_ON_THRESHOLD_SET_(value) \ 16723f0703cSBryan Whitehead ((value << 0) & FCT_FLOW_CTL_ON_THRESHOLD_) 16823f0703cSBryan Whitehead 16923f0703cSBryan Whitehead #define MAC_CR (0x100) 1706f197fb6SRoelof Berg #define MAC_CR_MII_EN_ BIT(19) 171c9cf96bbSBryan Whitehead #define MAC_CR_EEE_EN_ BIT(17) 17223f0703cSBryan Whitehead #define MAC_CR_ADD_ BIT(12) 17323f0703cSBryan Whitehead #define MAC_CR_ASD_ BIT(11) 17423f0703cSBryan Whitehead #define MAC_CR_CNTR_RST_ BIT(5) 1756f197fb6SRoelof Berg #define MAC_CR_DPX_ BIT(3) 1766f197fb6SRoelof Berg #define MAC_CR_CFG_H_ BIT(2) 1776f197fb6SRoelof Berg #define MAC_CR_CFG_L_ BIT(1) 17823f0703cSBryan Whitehead #define MAC_CR_RST_ BIT(0) 17923f0703cSBryan Whitehead 18023f0703cSBryan Whitehead #define MAC_RX (0x104) 18123f0703cSBryan Whitehead #define MAC_RX_MAX_SIZE_SHIFT_ (16) 18223f0703cSBryan Whitehead #define MAC_RX_MAX_SIZE_MASK_ (0x3FFF0000) 18323f0703cSBryan Whitehead #define MAC_RX_RXD_ BIT(1) 18423f0703cSBryan Whitehead #define MAC_RX_RXEN_ BIT(0) 18523f0703cSBryan Whitehead 18623f0703cSBryan Whitehead #define MAC_TX (0x108) 18723f0703cSBryan Whitehead #define MAC_TX_TXD_ BIT(1) 18823f0703cSBryan Whitehead #define MAC_TX_TXEN_ BIT(0) 18923f0703cSBryan Whitehead 19023f0703cSBryan Whitehead #define MAC_FLOW (0x10C) 19123f0703cSBryan Whitehead #define MAC_FLOW_CR_TX_FCEN_ BIT(30) 19223f0703cSBryan Whitehead #define MAC_FLOW_CR_RX_FCEN_ BIT(29) 19323f0703cSBryan Whitehead #define MAC_FLOW_CR_FCPT_MASK_ (0x0000FFFF) 19423f0703cSBryan Whitehead 19523f0703cSBryan Whitehead #define MAC_RX_ADDRH (0x118) 19623f0703cSBryan Whitehead 19723f0703cSBryan Whitehead #define MAC_RX_ADDRL (0x11C) 19823f0703cSBryan Whitehead 19923f0703cSBryan Whitehead #define MAC_MII_ACC (0x120) 200a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MDC_CYCLE_SHIFT_ (16) 201a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MDC_CYCLE_MASK_ (0x00070000) 202a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MDC_CYCLE_2_5MHZ_ (0) 203a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MDC_CYCLE_5MHZ_ (1) 204a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MDC_CYCLE_12_5MHZ_ (2) 205a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MDC_CYCLE_25MHZ_ (3) 206a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MDC_CYCLE_1_25MHZ_ (4) 20723f0703cSBryan Whitehead #define MAC_MII_ACC_PHY_ADDR_SHIFT_ (11) 20823f0703cSBryan Whitehead #define MAC_MII_ACC_PHY_ADDR_MASK_ (0x0000F800) 20923f0703cSBryan Whitehead #define MAC_MII_ACC_MIIRINDA_SHIFT_ (6) 21023f0703cSBryan Whitehead #define MAC_MII_ACC_MIIRINDA_MASK_ (0x000007C0) 21123f0703cSBryan Whitehead #define MAC_MII_ACC_MII_READ_ (0x00000000) 21223f0703cSBryan Whitehead #define MAC_MII_ACC_MII_WRITE_ (0x00000002) 21323f0703cSBryan Whitehead #define MAC_MII_ACC_MII_BUSY_ BIT(0) 21423f0703cSBryan Whitehead 215a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MIIMMD_SHIFT_ (6) 216a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MIIMMD_MASK_ (0x000007C0) 217a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MIICL45_ BIT(3) 218a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MIICMD_MASK_ (0x00000006) 219a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MIICMD_ADDR_ (0x00000000) 220a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MIICMD_WRITE_ (0x00000002) 221a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MIICMD_READ_ (0x00000004) 222a2ab95a3SRaju Lakkaraju #define MAC_MII_ACC_MIICMD_READ_INC_ (0x00000006) 223a2ab95a3SRaju Lakkaraju 22423f0703cSBryan Whitehead #define MAC_MII_DATA (0x124) 22523f0703cSBryan Whitehead 226c9cf96bbSBryan Whitehead #define MAC_EEE_TX_LPI_REQ_DLY_CNT (0x130) 227c9cf96bbSBryan Whitehead 2284d94282aSBryan Whitehead #define MAC_WUCSR (0x140) 2296b3768acSRaju Lakkaraju #define MAC_MP_SO_EN_ BIT(21) 2304d94282aSBryan Whitehead #define MAC_WUCSR_RFE_WAKE_EN_ BIT(14) 23141805c46SRaju Lakkaraju #define MAC_WUCSR_EEE_TX_WAKE_ BIT(13) 23241805c46SRaju Lakkaraju #define MAC_WUCSR_EEE_RX_WAKE_ BIT(11) 23341805c46SRaju Lakkaraju #define MAC_WUCSR_RFE_WAKE_FR_ BIT(9) 23441805c46SRaju Lakkaraju #define MAC_WUCSR_PFDA_FR_ BIT(7) 23541805c46SRaju Lakkaraju #define MAC_WUCSR_WUFR_ BIT(6) 23641805c46SRaju Lakkaraju #define MAC_WUCSR_MPR_ BIT(5) 23741805c46SRaju Lakkaraju #define MAC_WUCSR_BCAST_FR_ BIT(4) 2384d94282aSBryan Whitehead #define MAC_WUCSR_PFDA_EN_ BIT(3) 2394d94282aSBryan Whitehead #define MAC_WUCSR_WAKE_EN_ BIT(2) 2404d94282aSBryan Whitehead #define MAC_WUCSR_MPEN_ BIT(1) 2414d94282aSBryan Whitehead #define MAC_WUCSR_BCST_EN_ BIT(0) 2424d94282aSBryan Whitehead 2434d94282aSBryan Whitehead #define MAC_WK_SRC (0x144) 24441805c46SRaju Lakkaraju #define MAC_WK_SRC_ETH_PHY_WK_ BIT(17) 24541805c46SRaju Lakkaraju #define MAC_WK_SRC_IPV6_TCPSYN_RCD_WK_ BIT(16) 24641805c46SRaju Lakkaraju #define MAC_WK_SRC_IPV4_TCPSYN_RCD_WK_ BIT(15) 24741805c46SRaju Lakkaraju #define MAC_WK_SRC_EEE_TX_WK_ BIT(14) 24841805c46SRaju Lakkaraju #define MAC_WK_SRC_EEE_RX_WK_ BIT(13) 24941805c46SRaju Lakkaraju #define MAC_WK_SRC_RFE_FR_WK_ BIT(12) 25041805c46SRaju Lakkaraju #define MAC_WK_SRC_PFDA_FR_WK_ BIT(11) 25141805c46SRaju Lakkaraju #define MAC_WK_SRC_MP_FR_WK_ BIT(10) 25241805c46SRaju Lakkaraju #define MAC_WK_SRC_BCAST_FR_WK_ BIT(9) 25341805c46SRaju Lakkaraju #define MAC_WK_SRC_WU_FR_WK_ BIT(8) 25441805c46SRaju Lakkaraju #define MAC_WK_SRC_WK_FR_SAVED_ BIT(7) 25541805c46SRaju Lakkaraju 2566b3768acSRaju Lakkaraju #define MAC_MP_SO_HI (0x148) 2576b3768acSRaju Lakkaraju #define MAC_MP_SO_LO (0x14C) 2584d94282aSBryan Whitehead 2594d94282aSBryan Whitehead #define MAC_WUF_CFG0 (0x150) 2604d94282aSBryan Whitehead #define MAC_NUM_OF_WUF_CFG (32) 2614d94282aSBryan Whitehead #define MAC_WUF_CFG_BEGIN (MAC_WUF_CFG0) 2624d94282aSBryan Whitehead #define MAC_WUF_CFG(index) (MAC_WUF_CFG_BEGIN + (4 * (index))) 2634d94282aSBryan Whitehead #define MAC_WUF_CFG_EN_ BIT(31) 2644d94282aSBryan Whitehead #define MAC_WUF_CFG_TYPE_MCAST_ (0x02000000) 2654d94282aSBryan Whitehead #define MAC_WUF_CFG_TYPE_ALL_ (0x01000000) 2664d94282aSBryan Whitehead #define MAC_WUF_CFG_OFFSET_SHIFT_ (16) 2674d94282aSBryan Whitehead #define MAC_WUF_CFG_CRC16_MASK_ (0x0000FFFF) 2684d94282aSBryan Whitehead 2694d94282aSBryan Whitehead #define MAC_WUF_MASK0_0 (0x200) 2704d94282aSBryan Whitehead #define MAC_WUF_MASK0_1 (0x204) 2714d94282aSBryan Whitehead #define MAC_WUF_MASK0_2 (0x208) 2724d94282aSBryan Whitehead #define MAC_WUF_MASK0_3 (0x20C) 2734d94282aSBryan Whitehead #define MAC_WUF_MASK0_BEGIN (MAC_WUF_MASK0_0) 2744d94282aSBryan Whitehead #define MAC_WUF_MASK1_BEGIN (MAC_WUF_MASK0_1) 2754d94282aSBryan Whitehead #define MAC_WUF_MASK2_BEGIN (MAC_WUF_MASK0_2) 2764d94282aSBryan Whitehead #define MAC_WUF_MASK3_BEGIN (MAC_WUF_MASK0_3) 2774d94282aSBryan Whitehead #define MAC_WUF_MASK0(index) (MAC_WUF_MASK0_BEGIN + (0x10 * (index))) 2784d94282aSBryan Whitehead #define MAC_WUF_MASK1(index) (MAC_WUF_MASK1_BEGIN + (0x10 * (index))) 2794d94282aSBryan Whitehead #define MAC_WUF_MASK2(index) (MAC_WUF_MASK2_BEGIN + (0x10 * (index))) 2804d94282aSBryan Whitehead #define MAC_WUF_MASK3(index) (MAC_WUF_MASK3_BEGIN + (0x10 * (index))) 2814d94282aSBryan Whitehead 28223f0703cSBryan Whitehead /* offset 0x400 - 0x500, x may range from 0 to 32, for a total of 33 entries */ 28323f0703cSBryan Whitehead #define RFE_ADDR_FILT_HI(x) (0x400 + (8 * (x))) 28423f0703cSBryan Whitehead #define RFE_ADDR_FILT_HI_VALID_ BIT(31) 28523f0703cSBryan Whitehead 28623f0703cSBryan Whitehead /* offset 0x404 - 0x504, x may range from 0 to 32, for a total of 33 entries */ 28723f0703cSBryan Whitehead #define RFE_ADDR_FILT_LO(x) (0x404 + (8 * (x))) 28823f0703cSBryan Whitehead 28923f0703cSBryan Whitehead #define RFE_CTL (0x508) 290cd691050SRaju Lakkaraju #define RFE_CTL_TCP_UDP_COE_ BIT(12) 291cd691050SRaju Lakkaraju #define RFE_CTL_IP_COE_ BIT(11) 29223f0703cSBryan Whitehead #define RFE_CTL_AB_ BIT(10) 29323f0703cSBryan Whitehead #define RFE_CTL_AM_ BIT(9) 29423f0703cSBryan Whitehead #define RFE_CTL_AU_ BIT(8) 29523f0703cSBryan Whitehead #define RFE_CTL_MCAST_HASH_ BIT(3) 29623f0703cSBryan Whitehead #define RFE_CTL_DA_PERFECT_ BIT(1) 29723f0703cSBryan Whitehead 29843e8fe9bSBryan Whitehead #define RFE_RSS_CFG (0x554) 29943e8fe9bSBryan Whitehead #define RFE_RSS_CFG_UDP_IPV6_EX_ BIT(16) 30043e8fe9bSBryan Whitehead #define RFE_RSS_CFG_TCP_IPV6_EX_ BIT(15) 30143e8fe9bSBryan Whitehead #define RFE_RSS_CFG_IPV6_EX_ BIT(14) 30243e8fe9bSBryan Whitehead #define RFE_RSS_CFG_UDP_IPV6_ BIT(13) 30343e8fe9bSBryan Whitehead #define RFE_RSS_CFG_TCP_IPV6_ BIT(12) 30443e8fe9bSBryan Whitehead #define RFE_RSS_CFG_IPV6_ BIT(11) 30543e8fe9bSBryan Whitehead #define RFE_RSS_CFG_UDP_IPV4_ BIT(10) 30643e8fe9bSBryan Whitehead #define RFE_RSS_CFG_TCP_IPV4_ BIT(9) 30743e8fe9bSBryan Whitehead #define RFE_RSS_CFG_IPV4_ BIT(8) 30843e8fe9bSBryan Whitehead #define RFE_RSS_CFG_VALID_HASH_BITS_ (0x000000E0) 30943e8fe9bSBryan Whitehead #define RFE_RSS_CFG_RSS_QUEUE_ENABLE_ BIT(2) 31043e8fe9bSBryan Whitehead #define RFE_RSS_CFG_RSS_HASH_STORE_ BIT(1) 31143e8fe9bSBryan Whitehead #define RFE_RSS_CFG_RSS_ENABLE_ BIT(0) 31243e8fe9bSBryan Whitehead 31343e8fe9bSBryan Whitehead #define RFE_HASH_KEY(index) (0x558 + (index << 2)) 31443e8fe9bSBryan Whitehead 31543e8fe9bSBryan Whitehead #define RFE_INDX(index) (0x580 + (index << 2)) 31643e8fe9bSBryan Whitehead 3174d94282aSBryan Whitehead #define MAC_WUCSR2 (0x600) 31841805c46SRaju Lakkaraju #define MAC_WUCSR2_NS_RCD_ BIT(7) 31941805c46SRaju Lakkaraju #define MAC_WUCSR2_ARP_RCD_ BIT(6) 32041805c46SRaju Lakkaraju #define MAC_WUCSR2_IPV6_TCPSYN_RCD_ BIT(5) 32141805c46SRaju Lakkaraju #define MAC_WUCSR2_IPV4_TCPSYN_RCD_ BIT(4) 3224d94282aSBryan Whitehead 32346b777adSRaju Lakkaraju #define SGMII_ACC (0x720) 32446b777adSRaju Lakkaraju #define SGMII_ACC_SGMII_BZY_ BIT(31) 32546b777adSRaju Lakkaraju #define SGMII_ACC_SGMII_WR_ BIT(30) 32646b777adSRaju Lakkaraju #define SGMII_ACC_SGMII_MMD_SHIFT_ (16) 32746b777adSRaju Lakkaraju #define SGMII_ACC_SGMII_MMD_MASK_ GENMASK(20, 16) 32846b777adSRaju Lakkaraju #define SGMII_ACC_SGMII_MMD_VSR_ BIT(15) 32946b777adSRaju Lakkaraju #define SGMII_ACC_SGMII_ADDR_SHIFT_ (0) 33046b777adSRaju Lakkaraju #define SGMII_ACC_SGMII_ADDR_MASK_ GENMASK(15, 0) 33146b777adSRaju Lakkaraju #define SGMII_DATA (0x724) 33246b777adSRaju Lakkaraju #define SGMII_DATA_SHIFT_ (0) 33346b777adSRaju Lakkaraju #define SGMII_DATA_MASK_ GENMASK(15, 0) 334a46d9d37SRaju Lakkaraju #define SGMII_CTL (0x728) 335a46d9d37SRaju Lakkaraju #define SGMII_CTL_SGMII_ENABLE_ BIT(31) 336a46d9d37SRaju Lakkaraju #define SGMII_CTL_LINK_STATUS_SOURCE_ BIT(8) 337a46d9d37SRaju Lakkaraju #define SGMII_CTL_SGMII_POWER_DN_ BIT(1) 338a46d9d37SRaju Lakkaraju 33974a78a00SRaju Lakkaraju #define MISC_CTL_0 (0x920) 34074a78a00SRaju Lakkaraju #define MISC_CTL_0_RFE_READ_FIFO_MASK_ GENMASK(6, 4) 34174a78a00SRaju Lakkaraju 34246b777adSRaju Lakkaraju /* Vendor Specific SGMII MMD details */ 34346b777adSRaju Lakkaraju #define SR_VSMMD_PCS_ID1 0x0004 34446b777adSRaju Lakkaraju #define SR_VSMMD_PCS_ID2 0x0005 34546b777adSRaju Lakkaraju #define SR_VSMMD_STS 0x0008 34646b777adSRaju Lakkaraju #define SR_VSMMD_CTRL 0x0009 34746b777adSRaju Lakkaraju 34846b777adSRaju Lakkaraju #define VR_MII_DIG_CTRL1 0x8000 34946b777adSRaju Lakkaraju #define VR_MII_DIG_CTRL1_VR_RST_ BIT(15) 35046b777adSRaju Lakkaraju #define VR_MII_DIG_CTRL1_R2TLBE_ BIT(14) 35146b777adSRaju Lakkaraju #define VR_MII_DIG_CTRL1_EN_VSMMD1_ BIT(13) 35246b777adSRaju Lakkaraju #define VR_MII_DIG_CTRL1_CS_EN_ BIT(10) 35346b777adSRaju Lakkaraju #define VR_MII_DIG_CTRL1_MAC_AUTO_SW_ BIT(9) 35446b777adSRaju Lakkaraju #define VR_MII_DIG_CTRL1_INIT_ BIT(8) 35546b777adSRaju Lakkaraju #define VR_MII_DIG_CTRL1_DTXLANED_0_ BIT(4) 35646b777adSRaju Lakkaraju #define VR_MII_DIG_CTRL1_CL37_TMR_OVR_RIDE_ BIT(3) 35746b777adSRaju Lakkaraju #define VR_MII_DIG_CTRL1_EN_2_5G_MODE_ BIT(2) 35846b777adSRaju Lakkaraju #define VR_MII_DIG_CTRL1_BYP_PWRUP_ BIT(1) 35946b777adSRaju Lakkaraju #define VR_MII_DIG_CTRL1_PHY_MODE_CTRL_ BIT(0) 36046b777adSRaju Lakkaraju #define VR_MII_AN_CTRL 0x8001 36146b777adSRaju Lakkaraju #define VR_MII_AN_CTRL_MII_CTRL_ BIT(8) 36246b777adSRaju Lakkaraju #define VR_MII_AN_CTRL_SGMII_LINK_STS_ BIT(4) 36346b777adSRaju Lakkaraju #define VR_MII_AN_CTRL_TX_CONFIG_ BIT(3) 36446b777adSRaju Lakkaraju #define VR_MII_AN_CTRL_1000BASE_X_ (0) 36546b777adSRaju Lakkaraju #define VR_MII_AN_CTRL_SGMII_MODE_ (2) 36646b777adSRaju Lakkaraju #define VR_MII_AN_CTRL_QSGMII_MODE_ (3) 36746b777adSRaju Lakkaraju #define VR_MII_AN_CTRL_PCS_MODE_SHIFT_ (1) 36846b777adSRaju Lakkaraju #define VR_MII_AN_CTRL_PCS_MODE_MASK_ GENMASK(2, 1) 36946b777adSRaju Lakkaraju #define VR_MII_AN_CTRL_MII_AN_INTR_EN_ BIT(0) 37046b777adSRaju Lakkaraju #define VR_MII_AN_INTR_STS 0x8002 37146b777adSRaju Lakkaraju #define VR_MII_AN_INTR_STS_LINK_UP_ BIT(4) 37246b777adSRaju Lakkaraju #define VR_MII_AN_INTR_STS_SPEED_MASK_ GENMASK(3, 2) 37346b777adSRaju Lakkaraju #define VR_MII_AN_INTR_STS_1000_MBPS_ BIT(3) 37446b777adSRaju Lakkaraju #define VR_MII_AN_INTR_STS_100_MBPS_ BIT(2) 37546b777adSRaju Lakkaraju #define VR_MII_AN_INTR_STS_10_MBPS_ (0) 37646b777adSRaju Lakkaraju #define VR_MII_AN_INTR_STS_FDX_ BIT(1) 37746b777adSRaju Lakkaraju #define VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR_ BIT(0) 37846b777adSRaju Lakkaraju 37946b777adSRaju Lakkaraju #define VR_MII_LINK_TIMER_CTRL 0x800A 38046b777adSRaju Lakkaraju #define VR_MII_DIG_STS 0x8010 38146b777adSRaju Lakkaraju #define VR_MII_DIG_STS_PSEQ_STATE_MASK_ GENMASK(4, 2) 38246b777adSRaju Lakkaraju #define VR_MII_DIG_STS_PSEQ_STATE_POS_ (2) 38346b777adSRaju Lakkaraju #define VR_MII_GEN2_4_MPLL_CTRL0 0x8078 38446b777adSRaju Lakkaraju #define VR_MII_MPLL_CTRL0_REF_CLK_DIV2_ BIT(12) 38546b777adSRaju Lakkaraju #define VR_MII_MPLL_CTRL0_USE_REFCLK_PAD_ BIT(4) 38646b777adSRaju Lakkaraju #define VR_MII_GEN2_4_MPLL_CTRL1 0x8079 38746b777adSRaju Lakkaraju #define VR_MII_MPLL_CTRL1_MPLL_MULTIPLIER_ GENMASK(6, 0) 38846b777adSRaju Lakkaraju #define VR_MII_BAUD_RATE_3P125GBPS (3125) 38946b777adSRaju Lakkaraju #define VR_MII_BAUD_RATE_1P25GBPS (1250) 39046b777adSRaju Lakkaraju #define VR_MII_MPLL_MULTIPLIER_125 (125) 39146b777adSRaju Lakkaraju #define VR_MII_MPLL_MULTIPLIER_100 (100) 39246b777adSRaju Lakkaraju #define VR_MII_MPLL_MULTIPLIER_50 (50) 39346b777adSRaju Lakkaraju #define VR_MII_MPLL_MULTIPLIER_40 (40) 39446b777adSRaju Lakkaraju #define VR_MII_GEN2_4_MISC_CTRL1 0x809A 39546b777adSRaju Lakkaraju #define VR_MII_CTRL1_RX_RATE_0_MASK_ GENMASK(3, 2) 39646b777adSRaju Lakkaraju #define VR_MII_CTRL1_RX_RATE_0_SHIFT_ (2) 39746b777adSRaju Lakkaraju #define VR_MII_CTRL1_TX_RATE_0_MASK_ GENMASK(1, 0) 39846b777adSRaju Lakkaraju #define VR_MII_MPLL_BAUD_CLK (0) 39946b777adSRaju Lakkaraju #define VR_MII_MPLL_BAUD_CLK_DIV_2 (1) 40046b777adSRaju Lakkaraju #define VR_MII_MPLL_BAUD_CLK_DIV_4 (2) 40146b777adSRaju Lakkaraju 40223f0703cSBryan Whitehead #define INT_STS (0x780) 40323f0703cSBryan Whitehead #define INT_BIT_DMA_RX_(channel) BIT(24 + (channel)) 40423f0703cSBryan Whitehead #define INT_BIT_ALL_RX_ (0x0F000000) 40523f0703cSBryan Whitehead #define INT_BIT_DMA_TX_(channel) BIT(16 + (channel)) 40623f0703cSBryan Whitehead #define INT_BIT_ALL_TX_ (0x000F0000) 40723f0703cSBryan Whitehead #define INT_BIT_SW_GP_ BIT(9) 40807624df1SBryan Whitehead #define INT_BIT_1588_ BIT(7) 40907624df1SBryan Whitehead #define INT_BIT_ALL_OTHER_ (INT_BIT_SW_GP_ | INT_BIT_1588_) 41023f0703cSBryan Whitehead #define INT_BIT_MAS_ BIT(0) 41123f0703cSBryan Whitehead 41223f0703cSBryan Whitehead #define INT_SET (0x784) 41323f0703cSBryan Whitehead 41423f0703cSBryan Whitehead #define INT_EN_SET (0x788) 41523f0703cSBryan Whitehead 41623f0703cSBryan Whitehead #define INT_EN_CLR (0x78C) 41723f0703cSBryan Whitehead 41823f0703cSBryan Whitehead #define INT_STS_R2C (0x790) 41923f0703cSBryan Whitehead 42023f0703cSBryan Whitehead #define INT_VEC_EN_SET (0x794) 42123f0703cSBryan Whitehead #define INT_VEC_EN_CLR (0x798) 42223f0703cSBryan Whitehead #define INT_VEC_EN_AUTO_CLR (0x79C) 42323f0703cSBryan Whitehead #define INT_VEC_EN_(vector_index) BIT(0 + vector_index) 42423f0703cSBryan Whitehead 42523f0703cSBryan Whitehead #define INT_VEC_MAP0 (0x7A0) 42623f0703cSBryan Whitehead #define INT_VEC_MAP0_RX_VEC_(channel, vector) \ 42723f0703cSBryan Whitehead (((u32)(vector)) << ((channel) << 2)) 42823f0703cSBryan Whitehead 42923f0703cSBryan Whitehead #define INT_VEC_MAP1 (0x7A4) 43023f0703cSBryan Whitehead #define INT_VEC_MAP1_TX_VEC_(channel, vector) \ 43123f0703cSBryan Whitehead (((u32)(vector)) << ((channel) << 2)) 43223f0703cSBryan Whitehead 43323f0703cSBryan Whitehead #define INT_VEC_MAP2 (0x7A8) 43423f0703cSBryan Whitehead 43523f0703cSBryan Whitehead #define INT_MOD_MAP0 (0x7B0) 43623f0703cSBryan Whitehead 43723f0703cSBryan Whitehead #define INT_MOD_MAP1 (0x7B4) 43823f0703cSBryan Whitehead 43923f0703cSBryan Whitehead #define INT_MOD_MAP2 (0x7B8) 44023f0703cSBryan Whitehead 44123f0703cSBryan Whitehead #define INT_MOD_CFG0 (0x7C0) 44223f0703cSBryan Whitehead #define INT_MOD_CFG1 (0x7C4) 44323f0703cSBryan Whitehead #define INT_MOD_CFG2 (0x7C8) 44423f0703cSBryan Whitehead #define INT_MOD_CFG3 (0x7CC) 44523f0703cSBryan Whitehead #define INT_MOD_CFG4 (0x7D0) 44623f0703cSBryan Whitehead #define INT_MOD_CFG5 (0x7D4) 44723f0703cSBryan Whitehead #define INT_MOD_CFG6 (0x7D8) 44823f0703cSBryan Whitehead #define INT_MOD_CFG7 (0x7DC) 449ac16b6ebSRaju Lakkaraju #define INT_MOD_CFG8 (0x7E0) 450ac16b6ebSRaju Lakkaraju #define INT_MOD_CFG9 (0x7E4) 45123f0703cSBryan Whitehead 45207624df1SBryan Whitehead #define PTP_CMD_CTL (0x0A00) 453e432dd3bSRaju Lakkaraju #define PTP_CMD_CTL_PTP_LTC_TARGET_READ_ BIT(13) 45407624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_CLK_STP_NSEC_ BIT(6) 45507624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_CLOCK_STEP_SEC_ BIT(5) 45607624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_CLOCK_LOAD_ BIT(4) 45707624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_CLOCK_READ_ BIT(3) 45807624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_ENABLE_ BIT(2) 45907624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_DISABLE_ BIT(1) 46007624df1SBryan Whitehead #define PTP_CMD_CTL_PTP_RESET_ BIT(0) 46107624df1SBryan Whitehead #define PTP_GENERAL_CONFIG (0x0A04) 46207624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \ 46307624df1SBryan Whitehead (0x7 << (1 + ((channel) << 2))) 46407624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_ (0) 46507624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_10US_ (1) 46607624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_100US_ (2) 46707624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_1MS_ (3) 46807624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_10MS_ (4) 46907624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_200MS_ (5) 4704ece1ae4SYuiko Oshino #define PTP_GENERAL_CONFIG_CLOCK_EVENT_TOGGLE_ (6) 47107624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \ 47207624df1SBryan Whitehead (((value) & 0x7) << (1 + ((channel) << 2))) 47307624df1SBryan Whitehead #define PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) << 2)) 47407624df1SBryan Whitehead 475e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG (0x0A04) 476e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_X_MASK_(channel) \ 477e432dd3bSRaju Lakkaraju (0xf << (4 + ((channel) << 2))) 478e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_100NS_ (0) 479e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_500NS_ (1) 480e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_1US_ (2) 481e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_5US_ (3) 482e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_10US_ (4) 483e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_50US_ (5) 484e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_100US_ (6) 485e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_500US_ (7) 486e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_1MS_ (8) 487e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_5MS_ (9) 488e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_10MS_ (10) 489e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_50MS_ (11) 490e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_100MS_ (12) 491e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_200MS_ (13) 492e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_TOGG_ (14) 493e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_INT_ (15) 494e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_CLOCK_EVENT_X_SET_(channel, value) \ 495e432dd3bSRaju Lakkaraju (((value) & 0xf) << (4 + ((channel) << 2))) 496e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_EVENT_POL_X_(channel) (BIT(1 + ((channel) * 2))) 497e432dd3bSRaju Lakkaraju #define HS_PTP_GENERAL_CONFIG_RELOAD_ADD_X_(channel) (BIT((channel) * 2)) 498e432dd3bSRaju Lakkaraju 49907624df1SBryan Whitehead #define PTP_INT_STS (0x0A08) 50060942c39SRaju Lakkaraju #define PTP_INT_IO_FE_MASK_ GENMASK(31, 24) 50160942c39SRaju Lakkaraju #define PTP_INT_IO_FE_SHIFT_ (24) 50260942c39SRaju Lakkaraju #define PTP_INT_IO_FE_SET_(channel) BIT(24 + (channel)) 50360942c39SRaju Lakkaraju #define PTP_INT_IO_RE_MASK_ GENMASK(23, 16) 50460942c39SRaju Lakkaraju #define PTP_INT_IO_RE_SHIFT_ (16) 50560942c39SRaju Lakkaraju #define PTP_INT_IO_RE_SET_(channel) BIT(16 + (channel)) 506e432dd3bSRaju Lakkaraju #define PTP_INT_TX_TS_OVRFL_INT_ BIT(14) 507e432dd3bSRaju Lakkaraju #define PTP_INT_TX_SWTS_ERR_INT_ BIT(13) 508e432dd3bSRaju Lakkaraju #define PTP_INT_TX_TS_INT_ BIT(12) 509e432dd3bSRaju Lakkaraju #define PTP_INT_RX_TS_OVRFL_INT_ BIT(9) 510e432dd3bSRaju Lakkaraju #define PTP_INT_RX_TS_INT_ BIT(8) 511e432dd3bSRaju Lakkaraju #define PTP_INT_TIMER_INT_B_ BIT(1) 512e432dd3bSRaju Lakkaraju #define PTP_INT_TIMER_INT_A_ BIT(0) 51307624df1SBryan Whitehead #define PTP_INT_EN_SET (0x0A0C) 51460942c39SRaju Lakkaraju #define PTP_INT_EN_FE_EN_SET_(channel) BIT(24 + (channel)) 51560942c39SRaju Lakkaraju #define PTP_INT_EN_RE_EN_SET_(channel) BIT(16 + (channel)) 516e432dd3bSRaju Lakkaraju #define PTP_INT_EN_TIMER_SET_(channel) BIT(channel) 51707624df1SBryan Whitehead #define PTP_INT_EN_CLR (0x0A10) 51860942c39SRaju Lakkaraju #define PTP_INT_EN_FE_EN_CLR_(channel) BIT(24 + (channel)) 51960942c39SRaju Lakkaraju #define PTP_INT_EN_RE_EN_CLR_(channel) BIT(16 + (channel)) 52007624df1SBryan Whitehead #define PTP_INT_BIT_TX_SWTS_ERR_ BIT(13) 52107624df1SBryan Whitehead #define PTP_INT_BIT_TX_TS_ BIT(12) 52207624df1SBryan Whitehead #define PTP_INT_BIT_TIMER_B_ BIT(1) 52307624df1SBryan Whitehead #define PTP_INT_BIT_TIMER_A_ BIT(0) 52407624df1SBryan Whitehead 52507624df1SBryan Whitehead #define PTP_CLOCK_SEC (0x0A14) 52607624df1SBryan Whitehead #define PTP_CLOCK_NS (0x0A18) 52707624df1SBryan Whitehead #define PTP_CLOCK_SUBNS (0x0A1C) 52807624df1SBryan Whitehead #define PTP_CLOCK_RATE_ADJ (0x0A20) 52907624df1SBryan Whitehead #define PTP_CLOCK_RATE_ADJ_DIR_ BIT(31) 53007624df1SBryan Whitehead #define PTP_CLOCK_STEP_ADJ (0x0A2C) 53107624df1SBryan Whitehead #define PTP_CLOCK_STEP_ADJ_DIR_ BIT(31) 53207624df1SBryan Whitehead #define PTP_CLOCK_STEP_ADJ_VALUE_MASK_ (0x3FFFFFFF) 53307624df1SBryan Whitehead #define PTP_CLOCK_TARGET_SEC_X(channel) (0x0A30 + ((channel) << 4)) 53407624df1SBryan Whitehead #define PTP_CLOCK_TARGET_NS_X(channel) (0x0A34 + ((channel) << 4)) 53507624df1SBryan Whitehead #define PTP_CLOCK_TARGET_RELOAD_SEC_X(channel) (0x0A38 + ((channel) << 4)) 53607624df1SBryan Whitehead #define PTP_CLOCK_TARGET_RELOAD_NS_X(channel) (0x0A3C + ((channel) << 4)) 53760942c39SRaju Lakkaraju #define PTP_LTC_SET_SEC_HI (0x0A50) 53860942c39SRaju Lakkaraju #define PTP_LTC_SET_SEC_HI_SEC_47_32_MASK_ GENMASK(15, 0) 53960942c39SRaju Lakkaraju #define PTP_VERSION (0x0A54) 54060942c39SRaju Lakkaraju #define PTP_VERSION_TX_UP_MASK_ GENMASK(31, 24) 54160942c39SRaju Lakkaraju #define PTP_VERSION_TX_LO_MASK_ GENMASK(23, 16) 54260942c39SRaju Lakkaraju #define PTP_VERSION_RX_UP_MASK_ GENMASK(15, 8) 54360942c39SRaju Lakkaraju #define PTP_VERSION_RX_LO_MASK_ GENMASK(7, 0) 54460942c39SRaju Lakkaraju #define PTP_IO_SEL (0x0A58) 54560942c39SRaju Lakkaraju #define PTP_IO_SEL_MASK_ GENMASK(10, 8) 54660942c39SRaju Lakkaraju #define PTP_IO_SEL_SHIFT_ (8) 54707624df1SBryan Whitehead #define PTP_LATENCY (0x0A5C) 54807624df1SBryan Whitehead #define PTP_LATENCY_TX_SET_(tx_latency) (((u32)(tx_latency)) << 16) 54907624df1SBryan Whitehead #define PTP_LATENCY_RX_SET_(rx_latency) \ 55007624df1SBryan Whitehead (((u32)(rx_latency)) & 0x0000FFFF) 55107624df1SBryan Whitehead #define PTP_CAP_INFO (0x0A60) 55207624df1SBryan Whitehead #define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val) (((reg_val) & 0x00000070) >> 4) 55307624df1SBryan Whitehead 55407624df1SBryan Whitehead #define PTP_TX_MOD (0x0AA4) 55507624df1SBryan Whitehead #define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_ (0x10000000) 55607624df1SBryan Whitehead 55707624df1SBryan Whitehead #define PTP_TX_MOD2 (0x0AA8) 55807624df1SBryan Whitehead #define PTP_TX_MOD2_TX_PTP_CLR_UDPV4_CHKSUM_ (0x00000001) 55907624df1SBryan Whitehead 56007624df1SBryan Whitehead #define PTP_TX_EGRESS_SEC (0x0AAC) 56107624df1SBryan Whitehead #define PTP_TX_EGRESS_NS (0x0AB0) 56207624df1SBryan Whitehead #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_MASK_ (0xC0000000) 56307624df1SBryan Whitehead #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_AUTO_ (0x00000000) 56407624df1SBryan Whitehead #define PTP_TX_EGRESS_NS_CAPTURE_CAUSE_SW_ (0x40000000) 56507624df1SBryan Whitehead #define PTP_TX_EGRESS_NS_TS_NS_MASK_ (0x3FFFFFFF) 56607624df1SBryan Whitehead 56707624df1SBryan Whitehead #define PTP_TX_MSG_HEADER (0x0AB4) 56807624df1SBryan Whitehead #define PTP_TX_MSG_HEADER_MSG_TYPE_ (0x000F0000) 56907624df1SBryan Whitehead #define PTP_TX_MSG_HEADER_MSG_TYPE_SYNC_ (0x00000000) 57007624df1SBryan Whitehead 57160942c39SRaju Lakkaraju #define PTP_TX_CAP_INFO (0x0AB8) 57260942c39SRaju Lakkaraju #define PTP_TX_CAP_INFO_TX_CH_MASK_ GENMASK(1, 0) 57360942c39SRaju Lakkaraju #define PTP_TX_DOMAIN (0x0ABC) 57460942c39SRaju Lakkaraju #define PTP_TX_DOMAIN_MASK_ GENMASK(23, 16) 57560942c39SRaju Lakkaraju #define PTP_TX_DOMAIN_RANGE_EN_ BIT(15) 57660942c39SRaju Lakkaraju #define PTP_TX_DOMAIN_RANGE_MASK_ GENMASK(7, 0) 57760942c39SRaju Lakkaraju #define PTP_TX_SDOID (0x0AC0) 57860942c39SRaju Lakkaraju #define PTP_TX_SDOID_MASK_ GENMASK(23, 16) 57960942c39SRaju Lakkaraju #define PTP_TX_SDOID_RANGE_EN_ BIT(15) 58060942c39SRaju Lakkaraju #define PTP_TX_SDOID_11_0_MASK_ GENMASK(7, 0) 58160942c39SRaju Lakkaraju #define PTP_IO_CAP_CONFIG (0x0AC4) 58260942c39SRaju Lakkaraju #define PTP_IO_CAP_CONFIG_LOCK_FE_(channel) BIT(24 + (channel)) 58360942c39SRaju Lakkaraju #define PTP_IO_CAP_CONFIG_LOCK_RE_(channel) BIT(16 + (channel)) 58460942c39SRaju Lakkaraju #define PTP_IO_CAP_CONFIG_FE_CAP_EN_(channel) BIT(8 + (channel)) 58560942c39SRaju Lakkaraju #define PTP_IO_CAP_CONFIG_RE_CAP_EN_(channel) BIT(0 + (channel)) 58660942c39SRaju Lakkaraju #define PTP_IO_RE_LTC_SEC_CAP_X (0x0AC8) 58760942c39SRaju Lakkaraju #define PTP_IO_RE_LTC_NS_CAP_X (0x0ACC) 58860942c39SRaju Lakkaraju #define PTP_IO_FE_LTC_SEC_CAP_X (0x0AD0) 58960942c39SRaju Lakkaraju #define PTP_IO_FE_LTC_NS_CAP_X (0x0AD4) 59060942c39SRaju Lakkaraju #define PTP_IO_EVENT_OUTPUT_CFG (0x0AD8) 59160942c39SRaju Lakkaraju #define PTP_IO_EVENT_OUTPUT_CFG_SEL_(channel) BIT(16 + (channel)) 59260942c39SRaju Lakkaraju #define PTP_IO_EVENT_OUTPUT_CFG_EN_(channel) BIT(0 + (channel)) 59360942c39SRaju Lakkaraju #define PTP_IO_PIN_CFG (0x0ADC) 59460942c39SRaju Lakkaraju #define PTP_IO_PIN_CFG_OBUF_TYPE_(channel) BIT(0 + (channel)) 59560942c39SRaju Lakkaraju #define PTP_LTC_RD_SEC_HI (0x0AF0) 59660942c39SRaju Lakkaraju #define PTP_LTC_RD_SEC_HI_SEC_47_32_MASK_ GENMASK(15, 0) 59760942c39SRaju Lakkaraju #define PTP_LTC_RD_SEC_LO (0x0AF4) 59860942c39SRaju Lakkaraju #define PTP_LTC_RD_NS (0x0AF8) 59960942c39SRaju Lakkaraju #define PTP_LTC_RD_NS_29_0_MASK_ GENMASK(29, 0) 60060942c39SRaju Lakkaraju #define PTP_LTC_RD_SUBNS (0x0AFC) 60160942c39SRaju Lakkaraju #define PTP_RX_USER_MAC_HI (0x0B00) 60260942c39SRaju Lakkaraju #define PTP_RX_USER_MAC_HI_47_32_MASK_ GENMASK(15, 0) 60360942c39SRaju Lakkaraju #define PTP_RX_USER_MAC_LO (0x0B04) 60460942c39SRaju Lakkaraju #define PTP_RX_USER_IP_ADDR_0 (0x0B20) 60560942c39SRaju Lakkaraju #define PTP_RX_USER_IP_ADDR_1 (0x0B24) 60660942c39SRaju Lakkaraju #define PTP_RX_USER_IP_ADDR_2 (0x0B28) 60760942c39SRaju Lakkaraju #define PTP_RX_USER_IP_ADDR_3 (0x0B2C) 60860942c39SRaju Lakkaraju #define PTP_RX_USER_IP_MASK_0 (0x0B30) 60960942c39SRaju Lakkaraju #define PTP_RX_USER_IP_MASK_1 (0x0B34) 61060942c39SRaju Lakkaraju #define PTP_RX_USER_IP_MASK_2 (0x0B38) 61160942c39SRaju Lakkaraju #define PTP_RX_USER_IP_MASK_3 (0x0B3C) 61260942c39SRaju Lakkaraju #define PTP_TX_USER_MAC_HI (0x0B40) 61360942c39SRaju Lakkaraju #define PTP_TX_USER_MAC_HI_47_32_MASK_ GENMASK(15, 0) 61460942c39SRaju Lakkaraju #define PTP_TX_USER_MAC_LO (0x0B44) 61560942c39SRaju Lakkaraju #define PTP_TX_USER_IP_ADDR_0 (0x0B60) 61660942c39SRaju Lakkaraju #define PTP_TX_USER_IP_ADDR_1 (0x0B64) 61760942c39SRaju Lakkaraju #define PTP_TX_USER_IP_ADDR_2 (0x0B68) 61860942c39SRaju Lakkaraju #define PTP_TX_USER_IP_ADDR_3 (0x0B6C) 61960942c39SRaju Lakkaraju #define PTP_TX_USER_IP_MASK_0 (0x0B70) 62060942c39SRaju Lakkaraju #define PTP_TX_USER_IP_MASK_1 (0x0B74) 62160942c39SRaju Lakkaraju #define PTP_TX_USER_IP_MASK_2 (0x0B78) 62260942c39SRaju Lakkaraju #define PTP_TX_USER_IP_MASK_3 (0x0B7C) 62360942c39SRaju Lakkaraju 62423f0703cSBryan Whitehead #define DMAC_CFG (0xC00) 62523f0703cSBryan Whitehead #define DMAC_CFG_COAL_EN_ BIT(16) 62623f0703cSBryan Whitehead #define DMAC_CFG_CH_ARB_SEL_RX_HIGH_ (0x00000000) 62723f0703cSBryan Whitehead #define DMAC_CFG_MAX_READ_REQ_MASK_ (0x00000070) 62823f0703cSBryan Whitehead #define DMAC_CFG_MAX_READ_REQ_SET_(val) \ 62923f0703cSBryan Whitehead ((((u32)(val)) << 4) & DMAC_CFG_MAX_READ_REQ_MASK_) 63023f0703cSBryan Whitehead #define DMAC_CFG_MAX_DSPACE_16_ (0x00000000) 63123f0703cSBryan Whitehead #define DMAC_CFG_MAX_DSPACE_32_ (0x00000001) 63223f0703cSBryan Whitehead #define DMAC_CFG_MAX_DSPACE_64_ BIT(1) 63323f0703cSBryan Whitehead #define DMAC_CFG_MAX_DSPACE_128_ (0x00000003) 63423f0703cSBryan Whitehead 63523f0703cSBryan Whitehead #define DMAC_COAL_CFG (0xC04) 63623f0703cSBryan Whitehead #define DMAC_COAL_CFG_TIMER_LIMIT_MASK_ (0xFFF00000) 63723f0703cSBryan Whitehead #define DMAC_COAL_CFG_TIMER_LIMIT_SET_(val) \ 63823f0703cSBryan Whitehead ((((u32)(val)) << 20) & DMAC_COAL_CFG_TIMER_LIMIT_MASK_) 63923f0703cSBryan Whitehead #define DMAC_COAL_CFG_TIMER_TX_START_ BIT(19) 64023f0703cSBryan Whitehead #define DMAC_COAL_CFG_FLUSH_INTS_ BIT(18) 64123f0703cSBryan Whitehead #define DMAC_COAL_CFG_INT_EXIT_COAL_ BIT(17) 64223f0703cSBryan Whitehead #define DMAC_COAL_CFG_CSR_EXIT_COAL_ BIT(16) 64323f0703cSBryan Whitehead #define DMAC_COAL_CFG_TX_THRES_MASK_ (0x0000FF00) 64423f0703cSBryan Whitehead #define DMAC_COAL_CFG_TX_THRES_SET_(val) \ 64523f0703cSBryan Whitehead ((((u32)(val)) << 8) & DMAC_COAL_CFG_TX_THRES_MASK_) 64623f0703cSBryan Whitehead #define DMAC_COAL_CFG_RX_THRES_MASK_ (0x000000FF) 64723f0703cSBryan Whitehead #define DMAC_COAL_CFG_RX_THRES_SET_(val) \ 64823f0703cSBryan Whitehead (((u32)(val)) & DMAC_COAL_CFG_RX_THRES_MASK_) 64923f0703cSBryan Whitehead 65023f0703cSBryan Whitehead #define DMAC_OBFF_CFG (0xC08) 65123f0703cSBryan Whitehead #define DMAC_OBFF_TX_THRES_MASK_ (0x0000FF00) 65223f0703cSBryan Whitehead #define DMAC_OBFF_TX_THRES_SET_(val) \ 65323f0703cSBryan Whitehead ((((u32)(val)) << 8) & DMAC_OBFF_TX_THRES_MASK_) 65423f0703cSBryan Whitehead #define DMAC_OBFF_RX_THRES_MASK_ (0x000000FF) 65523f0703cSBryan Whitehead #define DMAC_OBFF_RX_THRES_SET_(val) \ 65623f0703cSBryan Whitehead (((u32)(val)) & DMAC_OBFF_RX_THRES_MASK_) 65723f0703cSBryan Whitehead 65823f0703cSBryan Whitehead #define DMAC_CMD (0xC0C) 65923f0703cSBryan Whitehead #define DMAC_CMD_SWR_ BIT(31) 66023f0703cSBryan Whitehead #define DMAC_CMD_TX_SWR_(channel) BIT(24 + (channel)) 66123f0703cSBryan Whitehead #define DMAC_CMD_START_T_(channel) BIT(20 + (channel)) 66223f0703cSBryan Whitehead #define DMAC_CMD_STOP_T_(channel) BIT(16 + (channel)) 66323f0703cSBryan Whitehead #define DMAC_CMD_RX_SWR_(channel) BIT(8 + (channel)) 66423f0703cSBryan Whitehead #define DMAC_CMD_START_R_(channel) BIT(4 + (channel)) 66523f0703cSBryan Whitehead #define DMAC_CMD_STOP_R_(channel) BIT(0 + (channel)) 66623f0703cSBryan Whitehead 66723f0703cSBryan Whitehead #define DMAC_INT_STS (0xC10) 66823f0703cSBryan Whitehead #define DMAC_INT_EN_SET (0xC14) 66923f0703cSBryan Whitehead #define DMAC_INT_EN_CLR (0xC18) 67023f0703cSBryan Whitehead #define DMAC_INT_BIT_RXFRM_(channel) BIT(16 + (channel)) 67123f0703cSBryan Whitehead #define DMAC_INT_BIT_TX_IOC_(channel) BIT(0 + (channel)) 67223f0703cSBryan Whitehead 67323f0703cSBryan Whitehead #define RX_CFG_A(channel) (0xC40 + ((channel) << 6)) 67423f0703cSBryan Whitehead #define RX_CFG_A_RX_WB_ON_INT_TMR_ BIT(30) 67523f0703cSBryan Whitehead #define RX_CFG_A_RX_WB_THRES_MASK_ (0x1F000000) 67623f0703cSBryan Whitehead #define RX_CFG_A_RX_WB_THRES_SET_(val) \ 67723f0703cSBryan Whitehead ((((u32)(val)) << 24) & RX_CFG_A_RX_WB_THRES_MASK_) 67823f0703cSBryan Whitehead #define RX_CFG_A_RX_PF_THRES_MASK_ (0x001F0000) 67923f0703cSBryan Whitehead #define RX_CFG_A_RX_PF_THRES_SET_(val) \ 68023f0703cSBryan Whitehead ((((u32)(val)) << 16) & RX_CFG_A_RX_PF_THRES_MASK_) 68123f0703cSBryan Whitehead #define RX_CFG_A_RX_PF_PRI_THRES_MASK_ (0x00001F00) 68223f0703cSBryan Whitehead #define RX_CFG_A_RX_PF_PRI_THRES_SET_(val) \ 68323f0703cSBryan Whitehead ((((u32)(val)) << 8) & RX_CFG_A_RX_PF_PRI_THRES_MASK_) 68423f0703cSBryan Whitehead #define RX_CFG_A_RX_HP_WB_EN_ BIT(5) 68523f0703cSBryan Whitehead 68623f0703cSBryan Whitehead #define RX_CFG_B(channel) (0xC44 + ((channel) << 6)) 68723f0703cSBryan Whitehead #define RX_CFG_B_TS_ALL_RX_ BIT(29) 68823f0703cSBryan Whitehead #define RX_CFG_B_RX_PAD_MASK_ (0x03000000) 68923f0703cSBryan Whitehead #define RX_CFG_B_RX_PAD_0_ (0x00000000) 69023f0703cSBryan Whitehead #define RX_CFG_B_RX_PAD_2_ (0x02000000) 69123f0703cSBryan Whitehead #define RX_CFG_B_RDMABL_512_ (0x00040000) 69223f0703cSBryan Whitehead #define RX_CFG_B_RX_RING_LEN_MASK_ (0x0000FFFF) 69323f0703cSBryan Whitehead 69423f0703cSBryan Whitehead #define RX_BASE_ADDRH(channel) (0xC48 + ((channel) << 6)) 69523f0703cSBryan Whitehead 69623f0703cSBryan Whitehead #define RX_BASE_ADDRL(channel) (0xC4C + ((channel) << 6)) 69723f0703cSBryan Whitehead 69823f0703cSBryan Whitehead #define RX_HEAD_WRITEBACK_ADDRH(channel) (0xC50 + ((channel) << 6)) 69923f0703cSBryan Whitehead 70023f0703cSBryan Whitehead #define RX_HEAD_WRITEBACK_ADDRL(channel) (0xC54 + ((channel) << 6)) 70123f0703cSBryan Whitehead 70223f0703cSBryan Whitehead #define RX_HEAD(channel) (0xC58 + ((channel) << 6)) 70323f0703cSBryan Whitehead 70423f0703cSBryan Whitehead #define RX_TAIL(channel) (0xC5C + ((channel) << 6)) 70523f0703cSBryan Whitehead #define RX_TAIL_SET_TOP_INT_EN_ BIT(30) 70623f0703cSBryan Whitehead #define RX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29) 70723f0703cSBryan Whitehead 70823f0703cSBryan Whitehead #define RX_CFG_C(channel) (0xC64 + ((channel) << 6)) 70923f0703cSBryan Whitehead #define RX_CFG_C_RX_TOP_INT_EN_AUTO_CLR_ BIT(6) 71023f0703cSBryan Whitehead #define RX_CFG_C_RX_INT_EN_R2C_ BIT(4) 71123f0703cSBryan Whitehead #define RX_CFG_C_RX_DMA_INT_STS_AUTO_CLR_ BIT(3) 71223f0703cSBryan Whitehead #define RX_CFG_C_RX_INT_STS_R2C_MODE_MASK_ (0x00000007) 71323f0703cSBryan Whitehead 71423f0703cSBryan Whitehead #define TX_CFG_A(channel) (0xD40 + ((channel) << 6)) 71523f0703cSBryan Whitehead #define TX_CFG_A_TX_HP_WB_ON_INT_TMR_ BIT(30) 71623f0703cSBryan Whitehead #define TX_CFG_A_TX_TMR_HPWB_SEL_IOC_ (0x10000000) 71723f0703cSBryan Whitehead #define TX_CFG_A_TX_PF_THRES_MASK_ (0x001F0000) 71823f0703cSBryan Whitehead #define TX_CFG_A_TX_PF_THRES_SET_(value) \ 71923f0703cSBryan Whitehead ((((u32)(value)) << 16) & TX_CFG_A_TX_PF_THRES_MASK_) 72023f0703cSBryan Whitehead #define TX_CFG_A_TX_PF_PRI_THRES_MASK_ (0x00001F00) 72123f0703cSBryan Whitehead #define TX_CFG_A_TX_PF_PRI_THRES_SET_(value) \ 72223f0703cSBryan Whitehead ((((u32)(value)) << 8) & TX_CFG_A_TX_PF_PRI_THRES_MASK_) 72323f0703cSBryan Whitehead #define TX_CFG_A_TX_HP_WB_EN_ BIT(5) 72423f0703cSBryan Whitehead #define TX_CFG_A_TX_HP_WB_THRES_MASK_ (0x0000000F) 72523f0703cSBryan Whitehead #define TX_CFG_A_TX_HP_WB_THRES_SET_(value) \ 72623f0703cSBryan Whitehead (((u32)(value)) & TX_CFG_A_TX_HP_WB_THRES_MASK_) 72723f0703cSBryan Whitehead 72823f0703cSBryan Whitehead #define TX_CFG_B(channel) (0xD44 + ((channel) << 6)) 72923f0703cSBryan Whitehead #define TX_CFG_B_TDMABL_512_ (0x00040000) 73023f0703cSBryan Whitehead #define TX_CFG_B_TX_RING_LEN_MASK_ (0x0000FFFF) 73123f0703cSBryan Whitehead 73223f0703cSBryan Whitehead #define TX_BASE_ADDRH(channel) (0xD48 + ((channel) << 6)) 73323f0703cSBryan Whitehead 73423f0703cSBryan Whitehead #define TX_BASE_ADDRL(channel) (0xD4C + ((channel) << 6)) 73523f0703cSBryan Whitehead 73623f0703cSBryan Whitehead #define TX_HEAD_WRITEBACK_ADDRH(channel) (0xD50 + ((channel) << 6)) 73723f0703cSBryan Whitehead 73823f0703cSBryan Whitehead #define TX_HEAD_WRITEBACK_ADDRL(channel) (0xD54 + ((channel) << 6)) 73923f0703cSBryan Whitehead 74023f0703cSBryan Whitehead #define TX_HEAD(channel) (0xD58 + ((channel) << 6)) 74123f0703cSBryan Whitehead 74223f0703cSBryan Whitehead #define TX_TAIL(channel) (0xD5C + ((channel) << 6)) 74323f0703cSBryan Whitehead #define TX_TAIL_SET_DMAC_INT_EN_ BIT(31) 74423f0703cSBryan Whitehead #define TX_TAIL_SET_TOP_INT_EN_ BIT(30) 74523f0703cSBryan Whitehead #define TX_TAIL_SET_TOP_INT_VEC_EN_ BIT(29) 74623f0703cSBryan Whitehead 74723f0703cSBryan Whitehead #define TX_CFG_C(channel) (0xD64 + ((channel) << 6)) 74823f0703cSBryan Whitehead #define TX_CFG_C_TX_TOP_INT_EN_AUTO_CLR_ BIT(6) 74923f0703cSBryan Whitehead #define TX_CFG_C_TX_DMA_INT_EN_AUTO_CLR_ BIT(5) 75023f0703cSBryan Whitehead #define TX_CFG_C_TX_INT_EN_R2C_ BIT(4) 75123f0703cSBryan Whitehead #define TX_CFG_C_TX_DMA_INT_STS_AUTO_CLR_ BIT(3) 75223f0703cSBryan Whitehead #define TX_CFG_C_TX_INT_STS_R2C_MODE_MASK_ (0x00000007) 75323f0703cSBryan Whitehead 75469584604SBryan Whitehead #define OTP_PWR_DN (0x1000) 75569584604SBryan Whitehead #define OTP_PWR_DN_PWRDN_N_ BIT(0) 75669584604SBryan Whitehead 757662a14d0SBryan Whitehead #define OTP_ADDR_HIGH (0x1004) 758662a14d0SBryan Whitehead #define OTP_ADDR_LOW (0x1008) 75969584604SBryan Whitehead 76069584604SBryan Whitehead #define OTP_PRGM_DATA (0x1010) 76169584604SBryan Whitehead 76269584604SBryan Whitehead #define OTP_PRGM_MODE (0x1014) 76369584604SBryan Whitehead #define OTP_PRGM_MODE_BYTE_ BIT(0) 76469584604SBryan Whitehead 765662a14d0SBryan Whitehead #define OTP_READ_DATA (0x1018) 766662a14d0SBryan Whitehead 767662a14d0SBryan Whitehead #define OTP_FUNC_CMD (0x1020) 768662a14d0SBryan Whitehead #define OTP_FUNC_CMD_READ_ BIT(0) 769662a14d0SBryan Whitehead 77069584604SBryan Whitehead #define OTP_TST_CMD (0x1024) 77169584604SBryan Whitehead #define OTP_TST_CMD_PRGVRFY_ BIT(3) 77269584604SBryan Whitehead 77369584604SBryan Whitehead #define OTP_CMD_GO (0x1028) 77469584604SBryan Whitehead #define OTP_CMD_GO_GO_ BIT(0) 77569584604SBryan Whitehead 77669584604SBryan Whitehead #define OTP_STATUS (0x1030) 77769584604SBryan Whitehead #define OTP_STATUS_BUSY_ BIT(0) 77869584604SBryan Whitehead 779d808f7caSRaju Lakkaraju /* Hearthstone OTP block registers */ 780d808f7caSRaju Lakkaraju #define HS_OTP_BLOCK_BASE (ETH_SYS_REG_ADDR_BASE + \ 781d808f7caSRaju Lakkaraju ETH_OTP_REG_ADDR_BASE) 782d808f7caSRaju Lakkaraju #define HS_OTP_PWR_DN (HS_OTP_BLOCK_BASE + 0x0) 783d808f7caSRaju Lakkaraju #define HS_OTP_ADDR_HIGH (HS_OTP_BLOCK_BASE + 0x4) 784d808f7caSRaju Lakkaraju #define HS_OTP_ADDR_LOW (HS_OTP_BLOCK_BASE + 0x8) 785d808f7caSRaju Lakkaraju #define HS_OTP_PRGM_DATA (HS_OTP_BLOCK_BASE + 0x10) 786d808f7caSRaju Lakkaraju #define HS_OTP_PRGM_MODE (HS_OTP_BLOCK_BASE + 0x14) 787d808f7caSRaju Lakkaraju #define HS_OTP_READ_DATA (HS_OTP_BLOCK_BASE + 0x18) 788d808f7caSRaju Lakkaraju #define HS_OTP_FUNC_CMD (HS_OTP_BLOCK_BASE + 0x20) 789d808f7caSRaju Lakkaraju #define HS_OTP_TST_CMD (HS_OTP_BLOCK_BASE + 0x24) 790d808f7caSRaju Lakkaraju #define HS_OTP_CMD_GO (HS_OTP_BLOCK_BASE + 0x28) 791d808f7caSRaju Lakkaraju #define HS_OTP_STATUS (HS_OTP_BLOCK_BASE + 0x30) 792d808f7caSRaju Lakkaraju 79323f0703cSBryan Whitehead /* MAC statistics registers */ 79423f0703cSBryan Whitehead #define STAT_RX_FCS_ERRORS (0x1200) 79523f0703cSBryan Whitehead #define STAT_RX_ALIGNMENT_ERRORS (0x1204) 7968114e8a2SBryan Whitehead #define STAT_RX_FRAGMENT_ERRORS (0x1208) 79723f0703cSBryan Whitehead #define STAT_RX_JABBER_ERRORS (0x120C) 79823f0703cSBryan Whitehead #define STAT_RX_UNDERSIZE_FRAME_ERRORS (0x1210) 79923f0703cSBryan Whitehead #define STAT_RX_OVERSIZE_FRAME_ERRORS (0x1214) 80023f0703cSBryan Whitehead #define STAT_RX_DROPPED_FRAMES (0x1218) 80123f0703cSBryan Whitehead #define STAT_RX_UNICAST_BYTE_COUNT (0x121C) 80223f0703cSBryan Whitehead #define STAT_RX_BROADCAST_BYTE_COUNT (0x1220) 80323f0703cSBryan Whitehead #define STAT_RX_MULTICAST_BYTE_COUNT (0x1224) 8048114e8a2SBryan Whitehead #define STAT_RX_UNICAST_FRAMES (0x1228) 8058114e8a2SBryan Whitehead #define STAT_RX_BROADCAST_FRAMES (0x122C) 80623f0703cSBryan Whitehead #define STAT_RX_MULTICAST_FRAMES (0x1230) 8078114e8a2SBryan Whitehead #define STAT_RX_PAUSE_FRAMES (0x1234) 8088114e8a2SBryan Whitehead #define STAT_RX_64_BYTE_FRAMES (0x1238) 8098114e8a2SBryan Whitehead #define STAT_RX_65_127_BYTE_FRAMES (0x123C) 8108114e8a2SBryan Whitehead #define STAT_RX_128_255_BYTE_FRAMES (0x1240) 8118114e8a2SBryan Whitehead #define STAT_RX_256_511_BYTES_FRAMES (0x1244) 8128114e8a2SBryan Whitehead #define STAT_RX_512_1023_BYTE_FRAMES (0x1248) 8138114e8a2SBryan Whitehead #define STAT_RX_1024_1518_BYTE_FRAMES (0x124C) 8148114e8a2SBryan Whitehead #define STAT_RX_GREATER_1518_BYTE_FRAMES (0x1250) 81523f0703cSBryan Whitehead #define STAT_RX_TOTAL_FRAMES (0x1254) 8168114e8a2SBryan Whitehead #define STAT_EEE_RX_LPI_TRANSITIONS (0x1258) 8178114e8a2SBryan Whitehead #define STAT_EEE_RX_LPI_TIME (0x125C) 8188114e8a2SBryan Whitehead #define STAT_RX_COUNTER_ROLLOVER_STATUS (0x127C) 81923f0703cSBryan Whitehead 82023f0703cSBryan Whitehead #define STAT_TX_FCS_ERRORS (0x1280) 82123f0703cSBryan Whitehead #define STAT_TX_EXCESS_DEFERRAL_ERRORS (0x1284) 82223f0703cSBryan Whitehead #define STAT_TX_CARRIER_ERRORS (0x1288) 8238114e8a2SBryan Whitehead #define STAT_TX_BAD_BYTE_COUNT (0x128C) 82423f0703cSBryan Whitehead #define STAT_TX_SINGLE_COLLISIONS (0x1290) 82523f0703cSBryan Whitehead #define STAT_TX_MULTIPLE_COLLISIONS (0x1294) 82623f0703cSBryan Whitehead #define STAT_TX_EXCESSIVE_COLLISION (0x1298) 82723f0703cSBryan Whitehead #define STAT_TX_LATE_COLLISIONS (0x129C) 82823f0703cSBryan Whitehead #define STAT_TX_UNICAST_BYTE_COUNT (0x12A0) 82923f0703cSBryan Whitehead #define STAT_TX_BROADCAST_BYTE_COUNT (0x12A4) 83023f0703cSBryan Whitehead #define STAT_TX_MULTICAST_BYTE_COUNT (0x12A8) 8318114e8a2SBryan Whitehead #define STAT_TX_UNICAST_FRAMES (0x12AC) 8328114e8a2SBryan Whitehead #define STAT_TX_BROADCAST_FRAMES (0x12B0) 83323f0703cSBryan Whitehead #define STAT_TX_MULTICAST_FRAMES (0x12B4) 8348114e8a2SBryan Whitehead #define STAT_TX_PAUSE_FRAMES (0x12B8) 8358114e8a2SBryan Whitehead #define STAT_TX_64_BYTE_FRAMES (0x12BC) 8368114e8a2SBryan Whitehead #define STAT_TX_65_127_BYTE_FRAMES (0x12C0) 8378114e8a2SBryan Whitehead #define STAT_TX_128_255_BYTE_FRAMES (0x12C4) 8388114e8a2SBryan Whitehead #define STAT_TX_256_511_BYTES_FRAMES (0x12C8) 8398114e8a2SBryan Whitehead #define STAT_TX_512_1023_BYTE_FRAMES (0x12CC) 8408114e8a2SBryan Whitehead #define STAT_TX_1024_1518_BYTE_FRAMES (0x12D0) 8418114e8a2SBryan Whitehead #define STAT_TX_GREATER_1518_BYTE_FRAMES (0x12D4) 84223f0703cSBryan Whitehead #define STAT_TX_TOTAL_FRAMES (0x12D8) 8438114e8a2SBryan Whitehead #define STAT_EEE_TX_LPI_TRANSITIONS (0x12DC) 8448114e8a2SBryan Whitehead #define STAT_EEE_TX_LPI_TIME (0x12E0) 8458114e8a2SBryan Whitehead #define STAT_TX_COUNTER_ROLLOVER_STATUS (0x12FC) 84623f0703cSBryan Whitehead 84723f0703cSBryan Whitehead /* End of Register definitions */ 84823f0703cSBryan Whitehead 84923f0703cSBryan Whitehead #define LAN743X_MAX_RX_CHANNELS (4) 85023f0703cSBryan Whitehead #define LAN743X_MAX_TX_CHANNELS (1) 851cf9aaea8SRaju Lakkaraju #define PCI11X1X_MAX_TX_CHANNELS (4) 85223f0703cSBryan Whitehead struct lan743x_adapter; 85323f0703cSBryan Whitehead 85423f0703cSBryan Whitehead #define LAN743X_USED_RX_CHANNELS (4) 85523f0703cSBryan Whitehead #define LAN743X_USED_TX_CHANNELS (1) 856cf9aaea8SRaju Lakkaraju #define PCI11X1X_USED_TX_CHANNELS (4) 85723f0703cSBryan Whitehead #define LAN743X_INT_MOD (400) 85823f0703cSBryan Whitehead 85923f0703cSBryan Whitehead #if (LAN743X_USED_RX_CHANNELS > LAN743X_MAX_RX_CHANNELS) 86023f0703cSBryan Whitehead #error Invalid LAN743X_USED_RX_CHANNELS 86123f0703cSBryan Whitehead #endif 86223f0703cSBryan Whitehead #if (LAN743X_USED_TX_CHANNELS > LAN743X_MAX_TX_CHANNELS) 86323f0703cSBryan Whitehead #error Invalid LAN743X_USED_TX_CHANNELS 86423f0703cSBryan Whitehead #endif 865cf9aaea8SRaju Lakkaraju #if (PCI11X1X_USED_TX_CHANNELS > PCI11X1X_MAX_TX_CHANNELS) 866cf9aaea8SRaju Lakkaraju #error Invalid PCI11X1X_USED_TX_CHANNELS 867cf9aaea8SRaju Lakkaraju #endif 86823f0703cSBryan Whitehead 86923f0703cSBryan Whitehead /* PCI */ 87023f0703cSBryan Whitehead /* SMSC acquired EFAR late 1990's, MCHP acquired SMSC 2012 */ 87123f0703cSBryan Whitehead #define PCI_VENDOR_ID_SMSC PCI_VENDOR_ID_EFAR 87223f0703cSBryan Whitehead #define PCI_DEVICE_ID_SMSC_LAN7430 (0x7430) 8734df5ce9bSBryan Whitehead #define PCI_DEVICE_ID_SMSC_LAN7431 (0x7431) 874bb4f6bffSRaju Lakkaraju #define PCI_DEVICE_ID_SMSC_A011 (0xA011) 875bb4f6bffSRaju Lakkaraju #define PCI_DEVICE_ID_SMSC_A041 (0xA041) 87623f0703cSBryan Whitehead 87723f0703cSBryan Whitehead #define PCI_CONFIG_LENGTH (0x1000) 87823f0703cSBryan Whitehead 87923f0703cSBryan Whitehead /* CSR */ 88023f0703cSBryan Whitehead #define CSR_LENGTH (0x2000) 88123f0703cSBryan Whitehead 88223f0703cSBryan Whitehead #define LAN743X_CSR_FLAG_IS_A0 BIT(0) 88323f0703cSBryan Whitehead #define LAN743X_CSR_FLAG_IS_B0 BIT(1) 88423f0703cSBryan Whitehead #define LAN743X_CSR_FLAG_SUPPORTS_INTR_AUTO_SET_CLR BIT(8) 88523f0703cSBryan Whitehead 88623f0703cSBryan Whitehead struct lan743x_csr { 88723f0703cSBryan Whitehead u32 flags; 88823f0703cSBryan Whitehead u8 __iomem *csr_address; 88923f0703cSBryan Whitehead u32 id_rev; 89023f0703cSBryan Whitehead u32 fpga_rev; 89123f0703cSBryan Whitehead }; 89223f0703cSBryan Whitehead 89323f0703cSBryan Whitehead /* INTERRUPTS */ 89423f0703cSBryan Whitehead typedef void(*lan743x_vector_handler)(void *context, u32 int_sts, u32 flags); 89523f0703cSBryan Whitehead 89623f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_IRQ_SHARED BIT(0) 89723f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_READ BIT(1) 89823f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_R2C BIT(2) 89923f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_W2C BIT(3) 90023f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CHECK BIT(4) 90123f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_CLEAR BIT(5) 90223f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_R2C BIT(6) 90323f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_CLEAR BIT(7) 90423f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_MASTER_ENABLE_SET BIT(8) 90523f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_CLEAR BIT(9) 90623f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_ISR_SET BIT(10) 90723f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_CLEAR BIT(11) 90823f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_VECTOR_ENABLE_AUTO_SET BIT(12) 90923f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_CLEAR BIT(13) 91023f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_ENABLE_AUTO_SET BIT(14) 91123f0703cSBryan Whitehead #define LAN743X_VECTOR_FLAG_SOURCE_STATUS_AUTO_CLEAR BIT(15) 91223f0703cSBryan Whitehead 91323f0703cSBryan Whitehead struct lan743x_vector { 91423f0703cSBryan Whitehead int irq; 91523f0703cSBryan Whitehead u32 flags; 91623f0703cSBryan Whitehead struct lan743x_adapter *adapter; 91723f0703cSBryan Whitehead int vector_index; 91823f0703cSBryan Whitehead u32 int_mask; 91923f0703cSBryan Whitehead lan743x_vector_handler handler; 92023f0703cSBryan Whitehead void *context; 92123f0703cSBryan Whitehead }; 92223f0703cSBryan Whitehead 92323f0703cSBryan Whitehead #define LAN743X_MAX_VECTOR_COUNT (8) 924ac16b6ebSRaju Lakkaraju #define PCI11X1X_MAX_VECTOR_COUNT (16) 92523f0703cSBryan Whitehead 92623f0703cSBryan Whitehead struct lan743x_intr { 92723f0703cSBryan Whitehead int flags; 92823f0703cSBryan Whitehead 92923f0703cSBryan Whitehead unsigned int irq; 93023f0703cSBryan Whitehead 931ac16b6ebSRaju Lakkaraju struct lan743x_vector vector_list[PCI11X1X_MAX_VECTOR_COUNT]; 93223f0703cSBryan Whitehead int number_of_vectors; 93323f0703cSBryan Whitehead bool using_vectors; 93423f0703cSBryan Whitehead 935470dfd80SSven Van Asbroeck bool software_isr_flag; 936470dfd80SSven Van Asbroeck wait_queue_head_t software_isr_wq; 93723f0703cSBryan Whitehead }; 93823f0703cSBryan Whitehead 93923f0703cSBryan Whitehead #define LAN743X_MAX_FRAME_SIZE (9 * 1024) 94023f0703cSBryan Whitehead 94123f0703cSBryan Whitehead /* PHY */ 94223f0703cSBryan Whitehead struct lan743x_phy { 94323f0703cSBryan Whitehead bool fc_autoneg; 94423f0703cSBryan Whitehead u8 fc_request_control; 94523f0703cSBryan Whitehead }; 94623f0703cSBryan Whitehead 94723f0703cSBryan Whitehead /* TX */ 94823f0703cSBryan Whitehead struct lan743x_tx_descriptor; 94923f0703cSBryan Whitehead struct lan743x_tx_buffer_info; 95023f0703cSBryan Whitehead 95123f0703cSBryan Whitehead #define GPIO_QUEUE_STARTED (0) 95223f0703cSBryan Whitehead #define GPIO_TX_FUNCTION (1) 95323f0703cSBryan Whitehead #define GPIO_TX_COMPLETION (2) 95423f0703cSBryan Whitehead #define GPIO_TX_FRAGMENT (3) 95523f0703cSBryan Whitehead 95623f0703cSBryan Whitehead #define TX_FRAME_FLAG_IN_PROGRESS BIT(0) 95723f0703cSBryan Whitehead 95807624df1SBryan Whitehead #define TX_TS_FLAG_TIMESTAMPING_ENABLED BIT(0) 95907624df1SBryan Whitehead #define TX_TS_FLAG_ONE_STEP_SYNC BIT(1) 96007624df1SBryan Whitehead 96123f0703cSBryan Whitehead struct lan743x_tx { 96223f0703cSBryan Whitehead struct lan743x_adapter *adapter; 96307624df1SBryan Whitehead u32 ts_flags; 96423f0703cSBryan Whitehead u32 vector_flags; 96523f0703cSBryan Whitehead int channel_number; 96623f0703cSBryan Whitehead 96723f0703cSBryan Whitehead int ring_size; 96823f0703cSBryan Whitehead size_t ring_allocation_size; 96923f0703cSBryan Whitehead struct lan743x_tx_descriptor *ring_cpu_ptr; 97023f0703cSBryan Whitehead dma_addr_t ring_dma_ptr; 97123f0703cSBryan Whitehead /* ring_lock: used to prevent concurrent access to tx ring */ 97223f0703cSBryan Whitehead spinlock_t ring_lock; 97323f0703cSBryan Whitehead u32 frame_flags; 97423f0703cSBryan Whitehead u32 frame_first; 97523f0703cSBryan Whitehead u32 frame_data0; 97623f0703cSBryan Whitehead u32 frame_tail; 97723f0703cSBryan Whitehead 97823f0703cSBryan Whitehead struct lan743x_tx_buffer_info *buffer_info; 97923f0703cSBryan Whitehead 98046251282SAlexey Denisov __le32 *head_cpu_ptr; 98123f0703cSBryan Whitehead dma_addr_t head_dma_ptr; 98223f0703cSBryan Whitehead int last_head; 98323f0703cSBryan Whitehead int last_tail; 98423f0703cSBryan Whitehead 98523f0703cSBryan Whitehead struct napi_struct napi; 986bc1962e5SRaju Lakkaraju u32 frame_count; 987721f80c4SRaju Lakkaraju u32 rqd_descriptors; 98823f0703cSBryan Whitehead }; 98923f0703cSBryan Whitehead 99007624df1SBryan Whitehead void lan743x_tx_set_timestamping_mode(struct lan743x_tx *tx, 99107624df1SBryan Whitehead bool enable_timestamping, 99207624df1SBryan Whitehead bool enable_onestep_sync); 99307624df1SBryan Whitehead 99423f0703cSBryan Whitehead /* RX */ 99523f0703cSBryan Whitehead struct lan743x_rx_descriptor; 99623f0703cSBryan Whitehead struct lan743x_rx_buffer_info; 99723f0703cSBryan Whitehead 99823f0703cSBryan Whitehead struct lan743x_rx { 99923f0703cSBryan Whitehead struct lan743x_adapter *adapter; 100023f0703cSBryan Whitehead u32 vector_flags; 100123f0703cSBryan Whitehead int channel_number; 100223f0703cSBryan Whitehead 100323f0703cSBryan Whitehead int ring_size; 100423f0703cSBryan Whitehead size_t ring_allocation_size; 100523f0703cSBryan Whitehead struct lan743x_rx_descriptor *ring_cpu_ptr; 100623f0703cSBryan Whitehead dma_addr_t ring_dma_ptr; 100723f0703cSBryan Whitehead 100823f0703cSBryan Whitehead struct lan743x_rx_buffer_info *buffer_info; 100923f0703cSBryan Whitehead 101046251282SAlexey Denisov __le32 *head_cpu_ptr; 101123f0703cSBryan Whitehead dma_addr_t head_dma_ptr; 101223f0703cSBryan Whitehead u32 last_head; 101323f0703cSBryan Whitehead u32 last_tail; 101423f0703cSBryan Whitehead 101523f0703cSBryan Whitehead struct napi_struct napi; 101623f0703cSBryan Whitehead 101723f0703cSBryan Whitehead u32 frame_count; 1018a8db76d4SSven Van Asbroeck 1019a8db76d4SSven Van Asbroeck struct sk_buff *skb_head, *skb_tail; 102023f0703cSBryan Whitehead }; 102123f0703cSBryan Whitehead 102246b777adSRaju Lakkaraju /* SGMII Link Speed Duplex status */ 102346b777adSRaju Lakkaraju enum lan743x_sgmii_lsd { 102446b777adSRaju Lakkaraju POWER_DOWN = 0, 102546b777adSRaju Lakkaraju LINK_DOWN, 102646b777adSRaju Lakkaraju ANEG_BUSY, 102746b777adSRaju Lakkaraju LINK_10HD, 102846b777adSRaju Lakkaraju LINK_10FD, 102946b777adSRaju Lakkaraju LINK_100HD, 103046b777adSRaju Lakkaraju LINK_100FD, 103146b777adSRaju Lakkaraju LINK_1000_MASTER, 103246b777adSRaju Lakkaraju LINK_1000_SLAVE, 103346b777adSRaju Lakkaraju LINK_2500_MASTER, 103446b777adSRaju Lakkaraju LINK_2500_SLAVE 103546b777adSRaju Lakkaraju }; 103646b777adSRaju Lakkaraju 1037*de4fc109SRaju Lakkaraju #define MAC_SUPPORTED_WAKES (WAKE_BCAST | WAKE_UCAST | WAKE_MCAST | \ 1038*de4fc109SRaju Lakkaraju WAKE_MAGIC | WAKE_ARP) 103923f0703cSBryan Whitehead struct lan743x_adapter { 104023f0703cSBryan Whitehead struct net_device *netdev; 104123f0703cSBryan Whitehead struct mii_bus *mdiobus; 104223f0703cSBryan Whitehead int msg_enable; 10434d94282aSBryan Whitehead #ifdef CONFIG_PM 10444d94282aSBryan Whitehead u32 wolopts; 10456b3768acSRaju Lakkaraju u8 sopass[SOPASS_MAX]; 1046*de4fc109SRaju Lakkaraju u32 phy_wolopts; 1047*de4fc109SRaju Lakkaraju u32 phy_wol_supported; 10484d94282aSBryan Whitehead #endif 104923f0703cSBryan Whitehead struct pci_dev *pdev; 105023f0703cSBryan Whitehead struct lan743x_csr csr; 105123f0703cSBryan Whitehead struct lan743x_intr intr; 105223f0703cSBryan Whitehead 105307624df1SBryan Whitehead struct lan743x_gpio gpio; 105407624df1SBryan Whitehead struct lan743x_ptp ptp; 105507624df1SBryan Whitehead 105623f0703cSBryan Whitehead u8 mac_address[ETH_ALEN]; 105723f0703cSBryan Whitehead 105823f0703cSBryan Whitehead struct lan743x_phy phy; 1059cf9aaea8SRaju Lakkaraju struct lan743x_tx tx[PCI11X1X_USED_TX_CHANNELS]; 1060cf9aaea8SRaju Lakkaraju struct lan743x_rx rx[LAN743X_USED_RX_CHANNELS]; 1061cf9aaea8SRaju Lakkaraju bool is_pci11x1x; 1062a46d9d37SRaju Lakkaraju bool is_sgmii_en; 1063cdea83ccSRaju Lakkaraju /* protect ethernet syslock */ 1064cdea83ccSRaju Lakkaraju spinlock_t eth_syslock_spinlock; 1065cdea83ccSRaju Lakkaraju bool eth_syslock_en; 1066cdea83ccSRaju Lakkaraju u32 eth_syslock_acquire_cnt; 106746b777adSRaju Lakkaraju struct mutex sgmii_rw_lock; 106846b777adSRaju Lakkaraju /* SGMII Link Speed & Duplex status */ 106946b777adSRaju Lakkaraju enum lan743x_sgmii_lsd sgmii_lsd; 1070cf9aaea8SRaju Lakkaraju u8 max_tx_channels; 1071cf9aaea8SRaju Lakkaraju u8 used_tx_channels; 1072ac16b6ebSRaju Lakkaraju u8 max_vector_count; 1073662a14d0SBryan Whitehead 1074662a14d0SBryan Whitehead #define LAN743X_ADAPTER_FLAG_OTP BIT(0) 1075662a14d0SBryan Whitehead u32 flags; 10766b3768acSRaju Lakkaraju u32 hw_cfg; 1077e86c7210SPavithra Sathyanarayanan phy_interface_t phy_interface; 107823f0703cSBryan Whitehead }; 107923f0703cSBryan Whitehead 108023f0703cSBryan Whitehead #define LAN743X_COMPONENT_FLAG_RX(channel) BIT(20 + (channel)) 108123f0703cSBryan Whitehead 108223f0703cSBryan Whitehead #define INTR_FLAG_IRQ_REQUESTED(vector_index) BIT(0 + vector_index) 108323f0703cSBryan Whitehead #define INTR_FLAG_MSI_ENABLED BIT(8) 108423f0703cSBryan Whitehead #define INTR_FLAG_MSIX_ENABLED BIT(9) 108523f0703cSBryan Whitehead 108623f0703cSBryan Whitehead #define MAC_MII_READ 1 108723f0703cSBryan Whitehead #define MAC_MII_WRITE 0 108823f0703cSBryan Whitehead 108923f0703cSBryan Whitehead #define PHY_FLAG_OPENED BIT(0) 109023f0703cSBryan Whitehead #define PHY_FLAG_ATTACHED BIT(1) 109123f0703cSBryan Whitehead 109223f0703cSBryan Whitehead #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 109323f0703cSBryan Whitehead #define DMA_ADDR_HIGH32(dma_addr) ((u32)(((dma_addr) >> 32) & 0xFFFFFFFF)) 109423f0703cSBryan Whitehead #else 109523f0703cSBryan Whitehead #define DMA_ADDR_HIGH32(dma_addr) ((u32)(0)) 109623f0703cSBryan Whitehead #endif 109723f0703cSBryan Whitehead #define DMA_ADDR_LOW32(dma_addr) ((u32)((dma_addr) & 0xFFFFFFFF)) 109823f0703cSBryan Whitehead #define DMA_DESCRIPTOR_SPACING_16 (16) 109923f0703cSBryan Whitehead #define DMA_DESCRIPTOR_SPACING_32 (32) 110023f0703cSBryan Whitehead #define DMA_DESCRIPTOR_SPACING_64 (64) 110123f0703cSBryan Whitehead #define DMA_DESCRIPTOR_SPACING_128 (128) 110223f0703cSBryan Whitehead #define DEFAULT_DMA_DESCRIPTOR_SPACING (L1_CACHE_BYTES) 110323f0703cSBryan Whitehead 110423f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_SET(start_bit, stop_bit) \ 110523f0703cSBryan Whitehead (((start_bit) ? 2 : 0) | ((stop_bit) ? 1 : 0)) 110623f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_INITIAL DMAC_CHANNEL_STATE_SET(0, 0) 110723f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_STARTED DMAC_CHANNEL_STATE_SET(1, 0) 110823f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_STOP_PENDING DMAC_CHANNEL_STATE_SET(1, 1) 110923f0703cSBryan Whitehead #define DMAC_CHANNEL_STATE_STOPPED DMAC_CHANNEL_STATE_SET(0, 1) 111023f0703cSBryan Whitehead 111123f0703cSBryan Whitehead /* TX Descriptor bits */ 111223f0703cSBryan Whitehead #define TX_DESC_DATA0_DTYPE_MASK_ (0xC0000000) 111323f0703cSBryan Whitehead #define TX_DESC_DATA0_DTYPE_DATA_ (0x00000000) 111423f0703cSBryan Whitehead #define TX_DESC_DATA0_DTYPE_EXT_ (0x40000000) 111523f0703cSBryan Whitehead #define TX_DESC_DATA0_FS_ (0x20000000) 111623f0703cSBryan Whitehead #define TX_DESC_DATA0_LS_ (0x10000000) 111723f0703cSBryan Whitehead #define TX_DESC_DATA0_EXT_ (0x08000000) 111823f0703cSBryan Whitehead #define TX_DESC_DATA0_IOC_ (0x04000000) 111923f0703cSBryan Whitehead #define TX_DESC_DATA0_ICE_ (0x00400000) 112023f0703cSBryan Whitehead #define TX_DESC_DATA0_IPE_ (0x00200000) 112123f0703cSBryan Whitehead #define TX_DESC_DATA0_TPE_ (0x00100000) 112223f0703cSBryan Whitehead #define TX_DESC_DATA0_FCS_ (0x00020000) 112307624df1SBryan Whitehead #define TX_DESC_DATA0_TSE_ (0x00010000) 112423f0703cSBryan Whitehead #define TX_DESC_DATA0_BUF_LENGTH_MASK_ (0x0000FFFF) 112523f0703cSBryan Whitehead #define TX_DESC_DATA0_EXT_LSO_ (0x00200000) 112623f0703cSBryan Whitehead #define TX_DESC_DATA0_EXT_PAY_LENGTH_MASK_ (0x000FFFFF) 112723f0703cSBryan Whitehead #define TX_DESC_DATA3_FRAME_LENGTH_MSS_MASK_ (0x3FFF0000) 112823f0703cSBryan Whitehead 112923f0703cSBryan Whitehead struct lan743x_tx_descriptor { 113046251282SAlexey Denisov __le32 data0; 113146251282SAlexey Denisov __le32 data1; 113246251282SAlexey Denisov __le32 data2; 113346251282SAlexey Denisov __le32 data3; 113423f0703cSBryan Whitehead } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING); 113523f0703cSBryan Whitehead 113623f0703cSBryan Whitehead #define TX_BUFFER_INFO_FLAG_ACTIVE BIT(0) 113707624df1SBryan Whitehead #define TX_BUFFER_INFO_FLAG_TIMESTAMP_REQUESTED BIT(1) 113823f0703cSBryan Whitehead #define TX_BUFFER_INFO_FLAG_IGNORE_SYNC BIT(2) 113923f0703cSBryan Whitehead #define TX_BUFFER_INFO_FLAG_SKB_FRAGMENT BIT(3) 114023f0703cSBryan Whitehead struct lan743x_tx_buffer_info { 114123f0703cSBryan Whitehead int flags; 114223f0703cSBryan Whitehead struct sk_buff *skb; 114323f0703cSBryan Whitehead dma_addr_t dma_ptr; 114423f0703cSBryan Whitehead unsigned int buffer_length; 114523f0703cSBryan Whitehead }; 114623f0703cSBryan Whitehead 1147721f80c4SRaju Lakkaraju #define LAN743X_TX_RING_SIZE (128) 114823f0703cSBryan Whitehead 114923f0703cSBryan Whitehead /* OWN bit is set. ie, Descs are owned by RX DMAC */ 115023f0703cSBryan Whitehead #define RX_DESC_DATA0_OWN_ (0x00008000) 115123f0703cSBryan Whitehead /* OWN bit is clear. ie, Descs are owned by host */ 115223f0703cSBryan Whitehead #define RX_DESC_DATA0_FS_ (0x80000000) 115323f0703cSBryan Whitehead #define RX_DESC_DATA0_LS_ (0x40000000) 115423f0703cSBryan Whitehead #define RX_DESC_DATA0_FRAME_LENGTH_MASK_ (0x3FFF0000) 115523f0703cSBryan Whitehead #define RX_DESC_DATA0_FRAME_LENGTH_GET_(data0) \ 115623f0703cSBryan Whitehead (((data0) & RX_DESC_DATA0_FRAME_LENGTH_MASK_) >> 16) 115723f0703cSBryan Whitehead #define RX_DESC_DATA0_EXT_ (0x00004000) 115823f0703cSBryan Whitehead #define RX_DESC_DATA0_BUF_LENGTH_MASK_ (0x00003FFF) 1159cd691050SRaju Lakkaraju #define RX_DESC_DATA1_STATUS_ICE_ (0x00020000) 1160cd691050SRaju Lakkaraju #define RX_DESC_DATA1_STATUS_TCE_ (0x00010000) 1161cd691050SRaju Lakkaraju #define RX_DESC_DATA1_STATUS_ICSM_ (0x00000001) 116223f0703cSBryan Whitehead #define RX_DESC_DATA2_TS_NS_MASK_ (0x3FFFFFFF) 116323f0703cSBryan Whitehead 116423f0703cSBryan Whitehead #if ((NET_IP_ALIGN != 0) && (NET_IP_ALIGN != 2)) 116523f0703cSBryan Whitehead #error NET_IP_ALIGN must be 0 or 2 116623f0703cSBryan Whitehead #endif 116723f0703cSBryan Whitehead 116823f0703cSBryan Whitehead #define RX_HEAD_PADDING NET_IP_ALIGN 116923f0703cSBryan Whitehead 117023f0703cSBryan Whitehead struct lan743x_rx_descriptor { 117146251282SAlexey Denisov __le32 data0; 117246251282SAlexey Denisov __le32 data1; 117346251282SAlexey Denisov __le32 data2; 117446251282SAlexey Denisov __le32 data3; 117523f0703cSBryan Whitehead } __aligned(DEFAULT_DMA_DESCRIPTOR_SPACING); 117623f0703cSBryan Whitehead 117723f0703cSBryan Whitehead #define RX_BUFFER_INFO_FLAG_ACTIVE BIT(0) 117823f0703cSBryan Whitehead struct lan743x_rx_buffer_info { 117923f0703cSBryan Whitehead int flags; 118023f0703cSBryan Whitehead struct sk_buff *skb; 118123f0703cSBryan Whitehead 118223f0703cSBryan Whitehead dma_addr_t dma_ptr; 118323f0703cSBryan Whitehead unsigned int buffer_length; 118423f0703cSBryan Whitehead }; 118523f0703cSBryan Whitehead 1186a1f16275SYuiko Oshino #define LAN743X_RX_RING_SIZE (128) 118723f0703cSBryan Whitehead 118823f0703cSBryan Whitehead #define RX_PROCESS_RESULT_NOTHING_TO_DO (0) 1189a8db76d4SSven Van Asbroeck #define RX_PROCESS_RESULT_BUFFER_RECEIVED (1) 119023f0703cSBryan Whitehead 11918114e8a2SBryan Whitehead u32 lan743x_csr_read(struct lan743x_adapter *adapter, int offset); 11928114e8a2SBryan Whitehead void lan743x_csr_write(struct lan743x_adapter *adapter, int offset, u32 data); 119346b777adSRaju Lakkaraju int lan743x_hs_syslock_acquire(struct lan743x_adapter *adapter, u16 timeout); 119446b777adSRaju Lakkaraju void lan743x_hs_syslock_release(struct lan743x_adapter *adapter); 1195cdc04540SRaju Lakkaraju void lan743x_mac_flow_ctrl_set_enables(struct lan743x_adapter *adapter, 1196cdc04540SRaju Lakkaraju bool tx_enable, bool rx_enable); 119790452205SRaju Lakkaraju int lan743x_sgmii_read(struct lan743x_adapter *adapter, u8 mmd, u16 addr); 11988114e8a2SBryan Whitehead 119923f0703cSBryan Whitehead #endif /* _LAN743X_H */ 1200