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Searched +full:0 +full:xe0008000 (Results 1 – 22 of 22) sorted by relevance

/openbmc/u-boot/board/freescale/mpc837xerdb/
H A Dpci.c74 clk->occr |= 0xf8000000; in pci_init_board()
78 pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; in pci_init_board()
79 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; in pci_init_board()
95 out_be32(&sysconf->pecr1, 0xE0008000); in pci_init_board()
96 out_be32(&sysconf->pecr2, 0xE0008000); in pci_init_board()
100 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); in pci_init_board()
101 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); in pci_init_board()
/openbmc/u-boot/board/freescale/mpc837xemds/
H A Dpci.c73 return 0; in is_pex_x2()
92 clk->occr |= 0xf8000000; in pci_init_board()
96 pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; in pci_init_board()
97 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; in pci_init_board()
122 out_be32(&sysconf->pecr1, 0xE0008000); in pci_init_board()
124 out_be32(&sysconf->pecr2, 0xE0008000); in pci_init_board()
128 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); in pci_init_board()
129 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); in pci_init_board()
/openbmc/u-boot/board/freescale/mpc8315erdb/
H A Dmpc8315erdb.c30 return 0; in board_early_init_f()
38 i2c_set_bus_num(0); in read_board_info()
40 if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0) in read_board_info()
43 return 0; in read_board_info()
59 i = (!info) ? 4: info & 0x03; in checkboard()
63 return 0; in checkboard()
128 clk->occr |= 0xe0000000; in pci_init_board()
133 pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; in pci_init_board()
134 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; in pci_init_board()
146 out_be32(&sysconf->pecr1, 0xE0008000); in pci_init_board()
[all …]
/openbmc/u-boot/board/mpc8308_p1m/
H A Dmpc8308_p1m.c22 return 0; in checkboard()
51 out_be32(&sysconf->pecr1, 0xE0008000); in pci_init_board()
55 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); in pci_init_board()
56 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); in pci_init_board()
67 return 0; in ft_board_setup()
73 int rv, num_if = 0; in board_eth_init()
77 if (rv >= 0) in board_eth_init()
83 if (rv >= 0) in board_eth_init()
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dmpc8544ds.dts16 reg = <0 0 0 0>; // Filled by U-Boot
20 reg = <0 0xe0005000 0 0x1000>;
22 ranges = <0x0 0x0 0x0 0xff800000 0x800000>;
26 ranges = <0x0 0x0 0xe0000000 0x100000>;
30 reg = <0 0xe0008000 0 0x1000>;
31 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
32 0x1000000 0x0 0x00000000 0 0xe1000000 0x0 0x10000>;
34 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
37 /* IDSEL 0x11 J17 Slot 1 */
38 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
[all …]
H A Dmpc8568mds.dts22 reg = <0x0 0x0 0x0 0x0>;
26 reg = <0x0 0xe0005000 0x0 0x1000>;
27 ranges = <0x0 0x0 0xfe000000 0x02000000
28 0x1 0x0 0xf8000000 0x00008000
29 0x2 0x0 0xf0000000 0x04000000
30 0x4 0x0 0xf8008000 0x00008000
31 0x5 0x0 0xf8010000 0x00008000>;
33 nor@0,0 {
37 reg = <0x0 0x0 0x02000000>;
42 bcsr@1,0 {
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/can/
H A Dxilinx,can.yaml121 reg = <0xe0008000 0x1000>;
126 tx-fifo-depth = <0x40>;
127 rx-fifo-depth = <0x40>;
133 reg = <0x40000000 0x10000>;
134 clocks = <&clkc 0>, <&clkc 1>;
138 tx-fifo-depth = <0x40>;
139 rx-fifo-depth = <0x40>;
145 reg = <0x40000000 0x2000>;
146 clocks = <&clkc 0>, <&clkc 1>;
150 tx-mailbox-count = <0x20>;
[all …]
/openbmc/u-boot/board/freescale/mpc8308rdb/
H A Dmpc8308rdb.c27 #define SPI_CS_MASK 0x00400000
31 return bus == 0 && cs == 0; in spi_cs_is_valid()
39 clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK); in spi_cs_activate()
47 setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK); in spi_cs_deactivate()
61 i2c_set_bus_num(0); in read_board_info()
63 if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0) in read_board_info()
66 return 0; in read_board_info()
82 i = (!info) ? 4 : info & 0x03; in checkboard()
86 return 0; in checkboard()
115 out_be32(&sysconf->pecr1, 0xE0008000); in pci_init_board()
[all …]
/openbmc/linux/arch/mips/include/asm/
H A Djazz.h15 * but many hardware register are accessible at 0xb9000000 in
16 * instead of 0xe0000000.
19 #define JAZZ_LOCAL_IO_SPACE 0xe0000000
24 * 0xf0000000 - Rev1
25 * 0xf0000001 - Rev2
26 * 0xf0000002 - Rev3
28 #define PICA_ASIC_REVISION 0xe0000008
43 * --------- . (0)
45 #define PICA_LED 0xe000f000
54 #define LED_DOT 0x01
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dsocrates.dts27 #size-cells = <0>;
29 PowerPC,8544@0 {
31 reg = <0>;
34 d-cache-size = <0x8000>; // L1, 32K
35 i-cache-size = <0x8000>; // L1, 32K
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
45 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
53 ranges = <0x00000000 0xe0000000 0x00100000>;
[all …]
H A Dtqm8540.dts29 #size-cells = <0>;
31 PowerPC,8540@0 {
33 reg = <0>;
38 timebase-frequency = <0>;
39 bus-frequency = <0>;
40 clock-frequency = <0>;
47 reg = <0x00000000 0x10000000>;
54 ranges = <0x0 0xe0000000 0x100000>;
55 bus-frequency = <0>;
58 ecm-law@0 {
[all …]
H A Dtqm8541.dts28 #size-cells = <0>;
30 PowerPC,8541@0 {
32 reg = <0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
46 reg = <0x00000000 0x10000000>;
53 ranges = <0x0 0xe0000000 0x100000>;
54 bus-frequency = <0>;
57 ecm-law@0 {
[all …]
H A Dtqm8555.dts28 #size-cells = <0>;
30 PowerPC,8555@0 {
32 reg = <0>;
37 timebase-frequency = <0>;
38 bus-frequency = <0>;
39 clock-frequency = <0>;
46 reg = <0x00000000 0x10000000>;
53 ranges = <0x0 0xe0000000 0x100000>;
54 bus-frequency = <0>;
57 ecm-law@0 {
[all …]
H A Dtqm8560.dts30 #size-cells = <0>;
32 PowerPC,8560@0 {
34 reg = <0>;
39 timebase-frequency = <0>;
40 bus-frequency = <0>;
41 clock-frequency = <0>;
48 reg = <0x00000000 0x10000000>;
55 ranges = <0x0 0xe0000000 0x100000>;
56 bus-frequency = <0>;
59 ecm-law@0 {
[all …]
H A Dstxssa8555.dts30 #size-cells = <0>;
32 PowerPC,8555@0 {
34 reg = <0x0>;
37 d-cache-size = <0x8000>; // L1, 32K
38 i-cache-size = <0x8000>; // L1, 32K
39 timebase-frequency = <0>; // 33 MHz, from uboot
40 bus-frequency = <0>; // 166 MHz
41 clock-frequency = <0>; // 825 MHz, from uboot
48 reg = <0x00000000 0x10000000>;
56 ranges = <0x0 0xe0000000 0x100000>;
[all …]
H A Dtqm8548.dts31 #size-cells = <0>;
33 PowerPC,8548@0 {
35 reg = <0>;
38 d-cache-size = <0x8000>; // L1, 32K
39 i-cache-size = <0x8000>; // L1, 32K
46 reg = <0x00000000 0x00000000>; // Filled in by U-Boot
53 ranges = <0x0 0xe0000000 0x100000>;
54 bus-frequency = <0>;
57 ecm-law@0 {
59 reg = <0x0 0x1000>;
[all …]
/openbmc/u-boot/board/gdsys/mpc8308/
H A Dhrcon.c38 MCFPGA_DONE = 1 << 0,
63 case 0: in fpga_set_reg()
68 if (res < 0) { in fpga_set_reg()
76 return 0; in fpga_set_reg()
84 case 0: in fpga_get_reg()
91 if (res < 0) { in fpga_get_reg()
98 return 0; in fpga_get_reg()
104 bool hw_type_cat = pca9698_get_value(0x20, 20); in checkboard()
117 return 0; in checkboard()
125 unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e }; in last_stage_init()
[all …]
H A Dstrider.c41 MCFPGA_DONE = 1 << 0,
66 case 0: in fpga_set_reg()
71 if (res < 0) { in fpga_set_reg()
79 return 0; in fpga_set_reg()
87 case 0: in fpga_get_reg()
94 if (res < 0) { in fpga_get_reg()
101 return 0; in fpga_get_reg()
107 bool hw_type_cat = pca9698_get_value(0x20, 18); in checkboard()
120 return 0; in checkboard()
128 unsigned char mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e }; in last_stage_init()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dzynq-7000.dtsi16 #size-cells = <0>;
18 cpu0: cpu@0 {
21 reg = <0>;
50 interrupts = <0 5 4>, <0 6 4>;
52 reg = <0xf8891000 0x1000>,
53 <0xf8893000 0x1000>;
75 reg = <0xf8007100 0x20>;
76 interrupts = <0 7 4>;
86 reg = <0xe0008000 0x1000>;
87 interrupts = <0 28 4>;
[all …]
/openbmc/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-7000.dtsi13 #size-cells = <0>;
15 cpu0: cpu@0 {
18 reg = <0>;
47 interrupts = <0 5 4>, <0 6 4>;
49 reg = <0xf8891000 0x1000>,
50 <0xf8893000 0x1000>;
69 #size-cells = <0>;
72 port@0 {
73 reg = <0>;
104 reg = <0xf8007100 0x20>;
[all …]
/openbmc/qemu/hw/arm/
H A Dxilinx_zynq.c59 #define MPCORE_PERIPHBASE 0xF8F00000
60 #define ZYNQ_BOARD_MIDR 0x413FC090
66 #define BOARD_SETUP_ADDR 0x100
68 #define SLCR_LOCK_OFFSET 0x004
69 #define SLCR_UNLOCK_OFFSET 0x008
70 #define SLCR_ARM_PLL_OFFSET 0x100
72 #define SLCR_XILINX_UNLOCK_KEY 0xdf0d
73 #define SLCR_XILINX_LOCK_KEY 0x767b
75 #define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080 /* Datasheet: UG585 (v1.12.1) */
77 #define ARMV7_IMM16(x) (extract32((x), 0, 12) | \
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dsama7g5.dtsi31 #size-cells = <0>;
33 cpu0: cpu@0 {
36 reg = <0x0>;
88 hysteresis = <0>;
94 hysteresis = <0>;
100 hysteresis = <0>;
122 #clock-cells = <0>;
127 #clock-cells = <0>;
132 #clock-cells = <0>;
151 reg = <0x100000 0x20000>;
[all …]