41 	MCFPGA_DONE = 1 << 0,
66 	case 0:  in fpga_set_reg()
71 		if (res < 0) {  in fpga_set_reg()
79 	return 0;  in fpga_set_reg()
87 	case 0:  in fpga_get_reg()
94 		if (res < 0) {  in fpga_get_reg()
101 	return 0;  in fpga_get_reg()
107 	bool hw_type_cat = pca9698_get_value(0x20, 18);  in checkboard()
120 	return 0;  in checkboard()
128 	unsigned char mclink_controllers_dvi[] = { 0x3c, 0x3d, 0x3e };  in last_stage_init()
130 	unsigned char mclink_controllers_dp[] = { 0x24, 0x25, 0x26 };  in last_stage_init()
132 	bool hw_type_cat = pca9698_get_value(0x20, 18);  in last_stage_init()
134 	bool is_dh = pca9698_get_value(0x20, 25);  in last_stage_init()
139 	pca9698_direction_output(0x20, 8, 0);  in last_stage_init()
142 	pca9698_direction_output(0x20, 10, 1);  in last_stage_init()
143 	pca9698_direction_output(0x20, 11, 1);  in last_stage_init()
145 	ch0_sgmii2_present = !pca9698_get_value(0x20, 37);  in last_stage_init()
148 	for (k = 0; k < ARRAY_SIZE(mclink_controllers_dvi); ++k) {  in last_stage_init()
149 		unsigned int ctr = 0;  in last_stage_init()
171 		pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);  in last_stage_init()
172 		pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);  in last_stage_init()
183 		strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);  in last_stage_init()
188 		if (retval < 0)  in last_stage_init()
190 		for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {  in last_stage_init()
194 			setup_88e1514(bb_miiphy_buses[0].name, mux_ch);  in last_stage_init()
203 	mclink_fpgacount = 0;  in last_stage_init()
205 	ioep_fpga_print_info(0);  in last_stage_init()
207 	if (!adv7611_probe(0))  in last_stage_init()
211 	if (ioep_fpga_has_osd(0))  in last_stage_init()
212 		osd_probe(0);  in last_stage_init()
216 	if (ioep_fpga_has_osd(0)) {  in last_stage_init()
217 		osd_probe(0);  in last_stage_init()
224 	ch7301_probe(0, false);  in last_stage_init()
225 	dp501_probe(0, false);  in last_stage_init()
228 	if (slaves <= 0)  in last_stage_init()
229 		return 0;  in last_stage_init()
236 		FPGA_SET_REG(k, extended_control, 0x10); /* enable video */  in last_stage_init()
271 			if (retval < 0)  in last_stage_init()
273 			setup_88e1514(bb_miiphy_buses[k].name, 0);  in last_stage_init()
277 	for (k = 0; k < ARRAY_SIZE(strider_fans); ++k) {  in last_stage_init()
282 	return 0;  in last_stage_init()
328 	pca9698_direction_output(0x20, 26, 1);  in mpc8308_init()
333 	pca9698_set_value(0x20, 26, state ? 0 : 1);  in mpc8308_set_fpga_reset()
343 	setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));  in mpc8308_setup_hw()
344 	setbits_be32(&immr->gpio[0].dat, 1 << (31-12));  in mpc8308_setup_hw()
349 	return pca9698_get_value(0x20, 20);  in mpc8308_get_fpga_done()
359 	out_be32(&sysconf->sdhccr, 0x02000000);  in board_mmc_init()
391 	out_be32(&sysconf->pecr1, 0xE0008000);  in pci_init_board()
395 	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);  in pci_init_board()
396 	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);  in pci_init_board()
416 	return 0;  in ft_board_setup()
428 	{ 0, 1},
436 	return 0;  in mii_dummy_init()
448 	return 0;  in mii_mdio_active()
457 	return 0;  in mii_mdio_tristate()
471 	return 0;  in mii_set_mdio()
481 	*v = ((gpio & GPIO_MDIO) != 0);  in mii_get_mdio()
483 	return 0;  in mii_get_mdio()
495 	return 0;  in mii_set_mdc()
502 	return 0;  in mii_delay()
515 		.priv = &fpga_mii[0],
553 			  sizeof(bb_miiphy_buses[0]);