1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
4 */
5
6 #include <common.h>
7 #include <mpc83xx.h>
8 #include <pci.h>
9 #include <asm/io.h>
10
11 static struct pci_region pci_regions[] = {
12 {
13 bus_start: CONFIG_SYS_PCI_MEM_BASE,
14 phys_start: CONFIG_SYS_PCI_MEM_PHYS,
15 size: CONFIG_SYS_PCI_MEM_SIZE,
16 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
17 },
18 {
19 bus_start: CONFIG_SYS_PCI_MMIO_BASE,
20 phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
21 size: CONFIG_SYS_PCI_MMIO_SIZE,
22 flags: PCI_REGION_MEM
23 },
24 {
25 bus_start: CONFIG_SYS_PCI_IO_BASE,
26 phys_start: CONFIG_SYS_PCI_IO_PHYS,
27 size: CONFIG_SYS_PCI_IO_SIZE,
28 flags: PCI_REGION_IO
29 }
30 };
31
32 static struct pci_region pcie_regions_0[] = {
33 {
34 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
35 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
36 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
37 .flags = PCI_REGION_MEM,
38 },
39 {
40 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
41 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
42 .size = CONFIG_SYS_PCIE1_IO_SIZE,
43 .flags = PCI_REGION_IO,
44 },
45 };
46
47 static struct pci_region pcie_regions_1[] = {
48 {
49 .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
50 .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
51 .size = CONFIG_SYS_PCIE2_MEM_SIZE,
52 .flags = PCI_REGION_MEM,
53 },
54 {
55 .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
56 .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
57 .size = CONFIG_SYS_PCIE2_IO_SIZE,
58 .flags = PCI_REGION_IO,
59 },
60 };
61
pci_init_board(void)62 void pci_init_board(void)
63 {
64 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
65 volatile sysconf83xx_t *sysconf = &immr->sysconf;
66 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
67 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
68 volatile law83xx_t *pcie_law = sysconf->pcielaw;
69 struct pci_region *reg[] = { pci_regions };
70 struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
71 u32 spridr = in_be32(&immr->sysconf.spridr);
72
73 /* Enable all 5 PCI_CLK_OUTPUTS */
74 clk->occr |= 0xf8000000;
75 udelay(2000);
76
77 /* Configure PCI Local Access Windows */
78 pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
79 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
80
81 pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
82 pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
83
84 mpc83xx_pci_init(1, reg);
85
86 /* There is no PEX in MPC8379 parts. */
87 if (PARTID_NO_E(spridr) == SPR_8379)
88 return;
89
90 /* Configure the clock for PCIE controller */
91 clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
92 SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
93
94 /* Deassert the resets in the control register */
95 out_be32(&sysconf->pecr1, 0xE0008000);
96 out_be32(&sysconf->pecr2, 0xE0008000);
97 udelay(2000);
98
99 /* Configure PCI Express Local Access Windows */
100 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
101 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
102
103 out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
104 out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
105
106 mpc83xx_pcie_init(2, pcie_reg);
107 }
108