1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
25e918a98SKim Phillips /*
39993e196SKim Phillips * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
45e918a98SKim Phillips */
55e918a98SKim Phillips
65e918a98SKim Phillips #include <common.h>
75e918a98SKim Phillips #include <mpc83xx.h>
85e918a98SKim Phillips #include <pci.h>
97e915580SAnton Vorontsov #include <asm/io.h>
105e918a98SKim Phillips
115e918a98SKim Phillips static struct pci_region pci_regions[] = {
125e918a98SKim Phillips {
136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD bus_start: CONFIG_SYS_PCI_MEM_BASE,
146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD phys_start: CONFIG_SYS_PCI_MEM_PHYS,
156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD size: CONFIG_SYS_PCI_MEM_SIZE,
165e918a98SKim Phillips flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
175e918a98SKim Phillips },
185e918a98SKim Phillips {
196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD bus_start: CONFIG_SYS_PCI_MMIO_BASE,
206d0f6bcfSJean-Christophe PLAGNIOL-VILLARD phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD size: CONFIG_SYS_PCI_MMIO_SIZE,
225e918a98SKim Phillips flags: PCI_REGION_MEM
235e918a98SKim Phillips },
245e918a98SKim Phillips {
256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD bus_start: CONFIG_SYS_PCI_IO_BASE,
266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD phys_start: CONFIG_SYS_PCI_IO_PHYS,
276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD size: CONFIG_SYS_PCI_IO_SIZE,
285e918a98SKim Phillips flags: PCI_REGION_IO
295e918a98SKim Phillips }
305e918a98SKim Phillips };
315e918a98SKim Phillips
327e915580SAnton Vorontsov static struct pci_region pcie_regions_0[] = {
337e915580SAnton Vorontsov {
347e915580SAnton Vorontsov .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
357e915580SAnton Vorontsov .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
367e915580SAnton Vorontsov .size = CONFIG_SYS_PCIE1_MEM_SIZE,
377e915580SAnton Vorontsov .flags = PCI_REGION_MEM,
387e915580SAnton Vorontsov },
397e915580SAnton Vorontsov {
407e915580SAnton Vorontsov .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
417e915580SAnton Vorontsov .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
427e915580SAnton Vorontsov .size = CONFIG_SYS_PCIE1_IO_SIZE,
437e915580SAnton Vorontsov .flags = PCI_REGION_IO,
447e915580SAnton Vorontsov },
457e915580SAnton Vorontsov };
467e915580SAnton Vorontsov
477e915580SAnton Vorontsov static struct pci_region pcie_regions_1[] = {
487e915580SAnton Vorontsov {
497e915580SAnton Vorontsov .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
507e915580SAnton Vorontsov .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
517e915580SAnton Vorontsov .size = CONFIG_SYS_PCIE2_MEM_SIZE,
527e915580SAnton Vorontsov .flags = PCI_REGION_MEM,
537e915580SAnton Vorontsov },
547e915580SAnton Vorontsov {
557e915580SAnton Vorontsov .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
567e915580SAnton Vorontsov .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
577e915580SAnton Vorontsov .size = CONFIG_SYS_PCIE2_IO_SIZE,
587e915580SAnton Vorontsov .flags = PCI_REGION_IO,
597e915580SAnton Vorontsov },
607e915580SAnton Vorontsov };
617e915580SAnton Vorontsov
pci_init_board(void)625e918a98SKim Phillips void pci_init_board(void)
635e918a98SKim Phillips {
646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
657e915580SAnton Vorontsov volatile sysconf83xx_t *sysconf = &immr->sysconf;
665e918a98SKim Phillips volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
675e918a98SKim Phillips volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
687e915580SAnton Vorontsov volatile law83xx_t *pcie_law = sysconf->pcielaw;
695e918a98SKim Phillips struct pci_region *reg[] = { pci_regions };
707e915580SAnton Vorontsov struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
717e915580SAnton Vorontsov u32 spridr = in_be32(&immr->sysconf.spridr);
725e918a98SKim Phillips
735e918a98SKim Phillips /* Enable all 5 PCI_CLK_OUTPUTS */
745e918a98SKim Phillips clk->occr |= 0xf8000000;
755e918a98SKim Phillips udelay(2000);
765e918a98SKim Phillips
775e918a98SKim Phillips /* Configure PCI Local Access Windows */
786d0f6bcfSJean-Christophe PLAGNIOL-VILLARD pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
795e918a98SKim Phillips pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
805e918a98SKim Phillips
816d0f6bcfSJean-Christophe PLAGNIOL-VILLARD pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
825e918a98SKim Phillips pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
835e918a98SKim Phillips
846aa3d3bfSPeter Tyser mpc83xx_pci_init(1, reg);
857e915580SAnton Vorontsov
867e915580SAnton Vorontsov /* There is no PEX in MPC8379 parts. */
877e915580SAnton Vorontsov if (PARTID_NO_E(spridr) == SPR_8379)
887e915580SAnton Vorontsov return;
897e915580SAnton Vorontsov
907e915580SAnton Vorontsov /* Configure the clock for PCIE controller */
917e915580SAnton Vorontsov clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
927e915580SAnton Vorontsov SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
937e915580SAnton Vorontsov
947e915580SAnton Vorontsov /* Deassert the resets in the control register */
957e915580SAnton Vorontsov out_be32(&sysconf->pecr1, 0xE0008000);
967e915580SAnton Vorontsov out_be32(&sysconf->pecr2, 0xE0008000);
977e915580SAnton Vorontsov udelay(2000);
987e915580SAnton Vorontsov
997e915580SAnton Vorontsov /* Configure PCI Express Local Access Windows */
1007e915580SAnton Vorontsov out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
1017e915580SAnton Vorontsov out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
1027e915580SAnton Vorontsov
1037e915580SAnton Vorontsov out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
1047e915580SAnton Vorontsov out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
1057e915580SAnton Vorontsov
1066aa3d3bfSPeter Tyser mpc83xx_pcie_init(2, pcie_reg);
1075e918a98SKim Phillips }
108