38 	MCFPGA_DONE = 1 << 0,
63 	case 0:  in fpga_set_reg()
68 		if (res < 0) {  in fpga_set_reg()
76 	return 0;  in fpga_set_reg()
84 	case 0:  in fpga_get_reg()
91 		if (res < 0) {  in fpga_get_reg()
98 	return 0;  in fpga_get_reg()
104 	bool hw_type_cat = pca9698_get_value(0x20, 20);  in checkboard()
117 	return 0;  in checkboard()
125 	unsigned char mclink_controllers[] = { 0x3c, 0x3d, 0x3e };  in last_stage_init()
127 	bool hw_type_cat = pca9698_get_value(0x20, 20);  in last_stage_init()
130 	FPGA_GET_REG(0, fpga_features, &fpga_features);  in last_stage_init()
133 	pca9698_direction_output(0x20, 10, 1);  in last_stage_init()
134 	pca9698_direction_output(0x20, 11, 1);  in last_stage_init()
136 	ch0_rgmii2_present = !pca9698_get_value(0x20, 30);  in last_stage_init()
139 	for (k = 0; k < ARRAY_SIZE(mclink_controllers); ++k) {  in last_stage_init()
140 		unsigned int ctr = 0;  in last_stage_init()
154 		pca953x_set_dir(mclink_controllers[k], MCFPGA_RESET_N, 0);  in last_stage_init()
155 		pca953x_set_val(mclink_controllers[k], MCFPGA_RESET_N, 0);  in last_stage_init()
166 		strncpy(mdiodev->name, bb_miiphy_buses[0].name, MDIO_NAME_LEN);  in last_stage_init()
171 		if (retval < 0)  in last_stage_init()
173 		for (mux_ch = 0; mux_ch < MAX_MUX_CHANNELS; ++mux_ch) {  in last_stage_init()
177 			setup_88e1514(bb_miiphy_buses[0].name, mux_ch);  in last_stage_init()
186 	mclink_fpgacount = 0;  in last_stage_init()
188 	ioep_fpga_print_info(0);  in last_stage_init()
189 	osd_probe(0);  in last_stage_init()
194 	if (slaves <= 0)  in last_stage_init()
195 		return 0;  in last_stage_init()
218 			if (retval < 0)  in last_stage_init()
220 			setup_88e1514(bb_miiphy_buses[k].name, 0);  in last_stage_init()
224 	for (k = 0; k < ARRAY_SIZE(hrcon_fans); ++k) {  in last_stage_init()
229 	return 0;  in last_stage_init()
273 	pca9698_direction_output(0x20, 4, 1);  in mpc8308_init()
278 	pca9698_set_value(0x20, 4, state ? 0 : 1);  in mpc8308_set_fpga_reset()
288 	setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12)));  in mpc8308_setup_hw()
289 	setbits_be32(&immr->gpio[0].dat, 1 << (31-12));  in mpc8308_setup_hw()
294 	return pca9698_get_value(0x20, 19);  in mpc8308_get_fpga_done()
304 	out_be32(&sysconf->sdhccr, 0x02000000);  in board_mmc_init()
336 	out_be32(&sysconf->pecr1, 0xE0008000);  in pci_init_board()
340 	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);  in pci_init_board()
341 	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);  in pci_init_board()
361 	return 0;  in ft_board_setup()
373 	{ 0, 1},
381 	return 0;  in mii_dummy_init()
393 	return 0;  in mii_mdio_active()
402 	return 0;  in mii_mdio_tristate()
416 	return 0;  in mii_set_mdio()
426 	*v = ((gpio & GPIO_MDIO) != 0);  in mii_get_mdio()
428 	return 0;  in mii_get_mdio()
440 	return 0;  in mii_set_mdc()
447 	return 0;  in mii_delay()
460 		.priv = &fpga_mii[0],
498 			  sizeof(bb_miiphy_buses[0]);