Home
last modified time | relevance | path

Searched +full:0 +full:xc2000000 (Results 1 – 23 of 23) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Dnvidia,tegra20-pcie.txt27 - cell 0 specifies the bus and device numbers of the root port:
30 - cell 1 denotes the upper 32 address bits and should be 0
45 - 0x81000000: I/O memory region
46 - 0x82000000: non-prefetchable memory region
47 - 0xc2000000: prefetchable memory region
73 - pinctrl-0: phandle for the default/active state of pin configurations.
104 - If lanes 0 to 3 are used:
150 - Root port 0 uses 4 lanes, root port 1 is unused.
158 "pcie-N": where N ranges from 0 to the value specified in nvidia,num-lanes.
171 reg = <0x80003000 0x00000800 /* PADS registers */
[all …]
H A Dnvidia,tegra194-pcie.yaml85 - const: p2u-0
123 0: C0
132 0 : C0
260 bus@0 {
263 ranges = <0x0 0x0 0x0 0x8 0x0>;
268 reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
269 <0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
270 <0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
271 <0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
278 linux,pci-domain = <0>;
[all …]
/openbmc/linux/tools/testing/selftests/kvm/s390x/
H A Dresets.c28 unsigned long cr2_59 = 0x10; /* enable guarded storage */ in guest_code_initial()
29 unsigned long cr8_63 = 0x1; /* monitor mask = 1 */ in guest_code_initial()
36 " lghi 2,0x11\n" /* Round toward 0 */ in guest_code_initial()
37 " sfpc 2\n" /* set fpc to !=0 */ in guest_code_initial()
38 " lctlg 2,2,%0\n" in guest_code_initial()
43 " llihh 0,0xffff\n" in guest_code_initial()
44 " llihl 1,0x5555\n" in guest_code_initial()
45 " llilh 2,0xaaaa\n" in guest_code_initial()
46 " llill 3,0x0000\n" in guest_code_initial()
48 " lghi 4,0x1\n" in guest_code_initial()
[all …]
/openbmc/u-boot/include/configs/
H A Ds32v234evb.h17 #define GICD_BASE 0x7D001000
18 #define GICC_BASE 0x7D002000
28 #define DDR_BASE_ADDR 0x80000000
30 #define DDR_BASE_ADDR 0xC0000000
46 #define CPU_RELEASE_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
75 #if 0
82 #define CONFIG_FEC_MXC_PHYADDR 0
85 #if 0 /* Disable until the FLASH will be implemented */
94 #define CONFIG_SYS_NAND_BASE 0x400E0000
101 #define CONFIG_LOADADDR 0xC307FFC0
[all …]
H A DMPC8540ADS.h21 * default CCARBAR is at 0xff700000
61 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
62 #define CONFIG_SYS_MEMTEST_END 0x00400000
64 #define CONFIG_SYS_CCSRBAR 0xe0000000
71 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
73 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
80 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
84 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
85 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
86 #define CONFIG_SYS_DDR_TIMING_1 0x37344321
[all …]
H A DMPC8560ADS.h24 * default CCARBAR is at 0xff700000
60 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
61 #define CONFIG_SYS_MEMTEST_END 0x00400000
63 #define CONFIG_SYS_CCSRBAR 0xe0000000
70 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
72 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
79 #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
83 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
84 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
85 #define CONFIG_SYS_DDR_TIMING_1 0x37344321
[all …]
H A Dsbc8349.h49 #define CONFIG_SYS_IMMR 0xE0000000
52 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
53 #define CONFIG_SYS_MEMTEST_END 0x00100000
75 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
86 #define SPD_EEPROM_ADDRESS 0x52 /* DDR DIMM */
97 #define CONFIG_SYS_DDR_TIMING_1 0x36332321
98 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
99 #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
100 #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */
105 #define CONFIG_SYS_DDR_MODE 0x00000023
[all …]
H A DMPC8349EMDS.h43 #define CONFIG_SYS_IMMR 0xE0000000
46 #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
47 #define CONFIG_SYS_MEMTEST_END 0x00100000
60 #define CONFIG_SYS_SPD_BUS_NUM 0
61 #define SPD_EEPROM_ADDRESS1 0x52
62 #define SPD_EEPROM_ADDRESS2 0x51
66 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
80 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/
90 #define CONFIG_SYS_DDRCDR_VALUE 0x80080001
96 #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
[all …]
/openbmc/linux/arch/arm/boot/dts/arm/
H A Dintegratorap-im-pd1.dts21 reg = <0xc2000000 0x00100000>;
28 syscon@0 {
30 reg = <0x00000000 0x1000>;
35 vco1: clock-controller@0 {
37 reg = <0x00 0x04>;
38 #clock-cells = <0>;
39 lock-offset = <0x08>;
40 vco-offset = <0x00>;
47 reg = <0x04 0x04>;
48 #clock-cells = <0>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dtegra186.dtsi19 <0x0 0x2200000 0x0 0x10000>,
20 <0x0 0x2210000 0x0 0x10000>;
36 reg = <0x0 0x02490000 0x0 0x10000>;
56 reg = <0x0 0x03100000 0x0 0x10000>;
63 reg = <0x0 0x3160000 0x0 0x100>;
66 #size-cells = <0>;
76 reg = <0x0 0x3180000 0x0 0x100>;
79 #size-cells = <0>;
89 reg = <0x0 0x3190000 0x0 0x100>;
92 #size-cells = <0>;
[all …]
H A Dtegra20.dtsi14 reg = <0x50000000 0x00024000>;
24 ranges = <0x54000000 0x54000000 0x04000000>;
28 reg = <0x54040000 0x00040000>;
37 reg = <0x54080000 0x00040000>;
46 reg = <0x540c0000 0x00040000>;
55 reg = <0x54100000 0x00040000>;
64 reg = <0x54140000 0x00040000>;
73 reg = <0x54180000 0x00040000>;
81 reg = <0x54200000 0x00040000>;
89 nvidia,head = <0>;
[all …]
H A Dtegra210.dtsi17 reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
18 0x0 0x01003800 0x0 0x00000800 /* AFI registers */
19 0x0 0x02000000 0x0 0x10000000>; /* configuration space */
26 interrupt-map-mask = <0 0 0 0>;
27 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
29 bus-range = <0x00 0xff>;
33 ranges = <0x82000000 0 0x01000000 0x0 0x01000000 0 0x00001000 /* port 0 configuration space */
34 0x82000000 0 0x01001000 0x0 0x01001000 0 0x00001000 /* port 1 configuration space */
35 0x81000000 0 0x0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
36 0x82000000 0 0x13000000 0x0 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
[all …]
H A Dtegra30.dtsi16 reg = <0x00003000 0x00000800 /* PADS registers */
17 0x00003800 0x00000200 /* AFI registers */
18 0x10000000 0x10000000>; /* configuration space */
25 interrupt-map-mask = <0 0 0 0>;
26 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
28 bus-range = <0x00 0xff>;
32 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
33 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
34 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
35 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
[all …]
H A Dtegra124.dtsi20 reg = <0x01003000 0x00000800 /* PADS registers */
21 0x01003800 0x00000800 /* AFI registers */
22 0x02000000 0x10000000>; /* configuration space */
29 interrupt-map-mask = <0 0 0 0>;
30 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
32 bus-range = <0x00 0xff>;
36 ranges = <0x82000000 0 0x01000000 0x01000000 0 0x00001000 /* port 0 configuration space */
37 0x82000000 0 0x01001000 0x01001000 0 0x00001000 /* port 1 configuration space */
38 0x81000000 0 0x0 0x12000000 0 0x00010000 /* downstream I/O (64 KiB) */
39 0x82000000 0 0x13000000 0x13000000 0 0x0d000000 /* non-prefetchable memory (208 MiB) */
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a.dtsi23 #size-cells = <0>;
25 cpu0: cpu@0 {
28 reg = <0x0>;
30 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
31 i-cache-size = <0xc000>;
34 d-cache-size = <0x8000>;
45 reg = <0x1>;
47 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
48 i-cache-size = <0xc000>;
51 d-cache-size = <0x8000>;
[all …]
/openbmc/linux/include/linux/firmware/
H A Dxlnx-zynqmp.h20 #define ZYNQMP_PM_VERSION_MINOR 0
26 #define ZYNQMP_TZ_VERSION_MINOR 0
32 #define PM_SIP_SVC 0xC2000000
39 #define ZYNQMP_FAMILY_CODE 0x23
40 #define VERSAL_FAMILY_CODE 0x26
43 #define ALL_SUB_FAMILY_CODE 0x00
44 #define VERSAL_SUB_FAMILY_CODE 0x01
45 #define VERSALNET_SUB_FAMILY_CODE 0x03
51 #define TF_A_PM_REGISTER_SGI 0xa04
52 #define PM_GET_TRUSTZONE_VERSION 0xa03
[all …]
/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dr8a7740.dtsi20 #size-cells = <0>;
21 cpu@0 {
24 reg = <0x0>;
35 reg = <0xc2800000 0x1000>,
36 <0xc2000000 0x1000>;
41 reg = <0xf0100000 0x1000>;
53 reg = <0xfe400000 0x400>;
68 reg = <0xfe910000 0x3000>;
77 reg = <0xfe914000 0x3000>;
87 reg = <0xe6138000 0x170>;
[all …]
/openbmc/linux/arch/powerpc/
H A DKconfig274 …-flag) -mstack-protector-guard=tls -mstack-protector-guard-reg=r2 -mstack-protector-guard-offset=0)
275 …flag) -mstack-protector-guard=tls -mstack-protector-guard-reg=r13 -mstack-protector-guard-offset=0)
461 default 0
774 default 0x5deadbeef0000000 if PPC64
775 default 0
829 definition from 0x10000 to 0x40000 in older versions.
1184 default "0x30000000"
1236 default "0xc0000000"
1252 default "0xc2000000" if CRASH_DUMP && !NONSTATIC_KERNEL
1253 default "0xc0000000"
[all …]
/openbmc/linux/crypto/
H A Daes_generic.c67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]
/openbmc/linux/sound/pci/mixart/
H A Dmixart_mixer.c24 0xc2c00000, /* [000] -96.0 dB */
25 0xc2bf0000, /* [001] -95.5 dB */
26 0xc2be0000, /* [002] -95.0 dB */
27 0xc2bd0000, /* [003] -94.5 dB */
28 0xc2bc0000, /* [004] -94.0 dB */
29 0xc2bb0000, /* [005] -93.5 dB */
30 0xc2ba0000, /* [006] -93.0 dB */
31 0xc2b90000, /* [007] -92.5 dB */
32 0xc2b80000, /* [008] -92.0 dB */
33 0xc2b70000, /* [009] -91.5 dB */
[all …]
/openbmc/linux/arch/s390/net/
H A Dbpf_jit_comp.c58 #define SEEN_MEM BIT(0) /* use mem[] for temporary storage */
66 #define REG_W0 (MAX_BPF_JIT_REG + 0) /* Work register 1 (even) */
70 #define REG_0 REG_W0 /* Register 0 */
101 [REG_W0] = 0,
174 unsigned int __disp = (disp) & 0xfff; \
188 unsigned int __imm = (imm) & 0xffff; \
195 long __pcrel = ((pcrel) >> 1) & 0xffff; \
202 _EMIT4((op) | (mask) << 20 | (__rel & 0xffff)); \
216 unsigned int __disp = (disp) & 0xfff; \
223 unsigned int __disp_h = _disp & 0xff000; \
[all …]
/openbmc/linux/sound/pci/hda/
H A Dpatch_ca0132.c37 #define FLOAT_ZERO 0x00000000
38 #define FLOAT_ONE 0x3f800000
39 #define FLOAT_TWO 0x40000000
40 #define FLOAT_THREE 0x40400000
41 #define FLOAT_FIVE 0x40a00000
42 #define FLOAT_SIX 0x40c00000
43 #define FLOAT_EIGHT 0x41000000
44 #define FLOAT_MINUS_5 0xc0a00000
46 #define UNSOL_TAG_DSP 0x16
55 #define MASTERCONTROL 0x80
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/
H A Dtg3.c71 #define BAR_0 0
105 #define RESET_KIND_SHUTDOWN 0
109 #define TG3_DEF_RX_MODE 0
110 #define TG3_DEF_TX_MODE 0
195 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
201 #if (NET_IP_ALIGN != 0)
234 module_param(tg3_debug, int, 0);
237 #define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
238 #define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
355 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
[all …]