1c7ba99c8SStephen Warren#include "skeleton.dtsi" 219014203SStephen Warren#include <dt-bindings/clock/tegra186-clock.h> 30388634aSStephen Warren#include <dt-bindings/gpio/tegra186-gpio.h> 4c7ba99c8SStephen Warren#include <dt-bindings/interrupt-controller/arm-gic.h> 5729c2db7SStephen Warren#include <dt-bindings/mailbox/tegra186-hsp.h> 620bbde06SStephen Warren#include <dt-bindings/power/tegra186-powergate.h> 719014203SStephen Warren#include <dt-bindings/reset/tegra186-reset.h> 8c7ba99c8SStephen Warren 9c7ba99c8SStephen Warren/ { 10c7ba99c8SStephen Warren compatible = "nvidia,tegra186"; 1120bbde06SStephen Warren interrupt-parent = <&gic>; 12c7ba99c8SStephen Warren #address-cells = <2>; 13c7ba99c8SStephen Warren #size-cells = <2>; 14c7ba99c8SStephen Warren 1519014203SStephen Warren gpio_main: gpio@2200000 { 16c7ba99c8SStephen Warren compatible = "nvidia,tegra186-gpio"; 17c7ba99c8SStephen Warren reg-names = "security", "gpio"; 18c7ba99c8SStephen Warren reg = 19c7ba99c8SStephen Warren <0x0 0x2200000 0x0 0x10000>, 20c7ba99c8SStephen Warren <0x0 0x2210000 0x0 0x10000>; 21c7ba99c8SStephen Warren interrupts = 22c7ba99c8SStephen Warren <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 23c7ba99c8SStephen Warren <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 24c7ba99c8SStephen Warren <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 25c7ba99c8SStephen Warren <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 26c7ba99c8SStephen Warren <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 27c7ba99c8SStephen Warren <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 28c7ba99c8SStephen Warren gpio-controller; 29c7ba99c8SStephen Warren #gpio-cells = <2>; 30c7ba99c8SStephen Warren interrupt-controller; 31c7ba99c8SStephen Warren #interrupt-cells = <2>; 32c7ba99c8SStephen Warren }; 33c7ba99c8SStephen Warren 34*31c1ff90SStephen Warren ethernet@2490000 { 35*31c1ff90SStephen Warren compatible = "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"; 36*31c1ff90SStephen Warren reg = <0x0 0x02490000 0x0 0x10000>; 37*31c1ff90SStephen Warren interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 38*31c1ff90SStephen Warren clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, 39*31c1ff90SStephen Warren <&bpmp TEGRA186_CLK_EQOS_AXI>, 40*31c1ff90SStephen Warren <&bpmp TEGRA186_CLK_EQOS_RX>, 41*31c1ff90SStephen Warren <&bpmp TEGRA186_CLK_EQOS_PTP_REF>, 42*31c1ff90SStephen Warren <&bpmp TEGRA186_CLK_EQOS_TX>; 43*31c1ff90SStephen Warren clock-names = "slave_bus", 44*31c1ff90SStephen Warren "master_bus", 45*31c1ff90SStephen Warren "rx", 46*31c1ff90SStephen Warren "ptp_ref", 47*31c1ff90SStephen Warren "tx"; 48*31c1ff90SStephen Warren resets = <&bpmp TEGRA186_RESET_EQOS>; 49*31c1ff90SStephen Warren reset-names = "eqos"; 50*31c1ff90SStephen Warren phy-mode = "rgmii"; 51*31c1ff90SStephen Warren status = "disabled"; 52*31c1ff90SStephen Warren }; 53*31c1ff90SStephen Warren 54c7ba99c8SStephen Warren uarta: serial@3100000 { 55c7ba99c8SStephen Warren compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; 56c7ba99c8SStephen Warren reg = <0x0 0x03100000 0x0 0x10000>; 57c7ba99c8SStephen Warren reg-shift = <2>; 58c7ba99c8SStephen Warren status = "disabled"; 59c7ba99c8SStephen Warren }; 60c7ba99c8SStephen Warren 619e613de0SBryan Wu gen1_i2c: i2c@3160000 { 629e613de0SBryan Wu compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 639e613de0SBryan Wu reg = <0x0 0x3160000 0x0 0x100>; 649e613de0SBryan Wu interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 659e613de0SBryan Wu #address-cells = <1>; 669e613de0SBryan Wu #size-cells = <0>; 679e613de0SBryan Wu clocks = <&bpmp TEGRA186_CLK_I2C1>; 68b4ee081eSStephen Warren clock-names = "div-clk"; 699e613de0SBryan Wu resets = <&bpmp TEGRA186_RESET_I2C1>; 709e613de0SBryan Wu reset-names = "i2c"; 719e613de0SBryan Wu status = "disabled"; 729e613de0SBryan Wu }; 739e613de0SBryan Wu 749e613de0SBryan Wu cam_i2c: i2c@3180000 { 759e613de0SBryan Wu compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 769e613de0SBryan Wu reg = <0x0 0x3180000 0x0 0x100>; 779e613de0SBryan Wu interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 789e613de0SBryan Wu #address-cells = <1>; 799e613de0SBryan Wu #size-cells = <0>; 809e613de0SBryan Wu clocks = <&bpmp TEGRA186_CLK_I2C3>; 81b4ee081eSStephen Warren clock-names = "div-clk"; 829e613de0SBryan Wu resets = <&bpmp TEGRA186_RESET_I2C3>; 839e613de0SBryan Wu reset-names = "i2c"; 849e613de0SBryan Wu status = "disabled"; 859e613de0SBryan Wu }; 869e613de0SBryan Wu 879e613de0SBryan Wu dp_aux_ch1_i2c: i2c@3190000 { 889e613de0SBryan Wu compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 899e613de0SBryan Wu reg = <0x0 0x3190000 0x0 0x100>; 909e613de0SBryan Wu interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 919e613de0SBryan Wu #address-cells = <1>; 929e613de0SBryan Wu #size-cells = <0>; 939e613de0SBryan Wu clocks = <&bpmp TEGRA186_CLK_I2C4>; 94b4ee081eSStephen Warren clock-names = "div-clk"; 959e613de0SBryan Wu resets = <&bpmp TEGRA186_RESET_I2C4>; 969e613de0SBryan Wu reset-names = "i2c"; 979e613de0SBryan Wu status = "disabled"; 989e613de0SBryan Wu }; 999e613de0SBryan Wu 1009e613de0SBryan Wu dp_aux_ch0_i2c: i2c@31b0000 { 1019e613de0SBryan Wu compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 1029e613de0SBryan Wu reg = <0x0 0x31b0000 0x0 0x100>; 1039e613de0SBryan Wu interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1049e613de0SBryan Wu #address-cells = <1>; 1059e613de0SBryan Wu #size-cells = <0>; 1069e613de0SBryan Wu clocks = <&bpmp TEGRA186_CLK_I2C6>; 107b4ee081eSStephen Warren clock-names = "div-clk"; 1089e613de0SBryan Wu resets = <&bpmp TEGRA186_RESET_I2C6>; 1099e613de0SBryan Wu reset-names = "i2c"; 1109e613de0SBryan Wu status = "disabled"; 1119e613de0SBryan Wu }; 1129e613de0SBryan Wu 1139e613de0SBryan Wu gen7_i2c: i2c@31c0000 { 1149e613de0SBryan Wu compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 1159e613de0SBryan Wu reg = <0x0 0x31c0000 0x0 0x100>; 1169e613de0SBryan Wu interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1179e613de0SBryan Wu #address-cells = <1>; 1189e613de0SBryan Wu #size-cells = <0>; 1199e613de0SBryan Wu clocks = <&bpmp TEGRA186_CLK_I2C7>; 120b4ee081eSStephen Warren clock-names = "div-clk"; 1219e613de0SBryan Wu resets = <&bpmp TEGRA186_RESET_I2C7>; 1229e613de0SBryan Wu reset-names = "i2c"; 1239e613de0SBryan Wu status = "disabled"; 1249e613de0SBryan Wu }; 1259e613de0SBryan Wu 1269e613de0SBryan Wu gen9_i2c: i2c@31e0000 { 1279e613de0SBryan Wu compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 1289e613de0SBryan Wu reg = <0x0 0x31e0000 0x0 0x100>; 1299e613de0SBryan Wu interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1309e613de0SBryan Wu #address-cells = <1>; 1319e613de0SBryan Wu #size-cells = <0>; 1329e613de0SBryan Wu clocks = <&bpmp TEGRA186_CLK_I2C9>; 133b4ee081eSStephen Warren clock-names = "div-clk"; 1349e613de0SBryan Wu resets = <&bpmp TEGRA186_RESET_I2C9>; 1359e613de0SBryan Wu reset-names = "i2c"; 1369e613de0SBryan Wu status = "disabled"; 1379e613de0SBryan Wu }; 1389e613de0SBryan Wu 13919014203SStephen Warren sdhci@3400000 { 14019014203SStephen Warren compatible = "nvidia,tegra186-sdhci"; 14119014203SStephen Warren reg = <0x0 0x03400000 0x0 0x200>; 14219014203SStephen Warren resets = <&bpmp TEGRA186_RESET_SDMMC1>; 143eb3f68afSStephen Warren reset-names = "sdhci"; 14419014203SStephen Warren clocks = <&bpmp TEGRA186_CLK_SDMMC1>; 14519014203SStephen Warren interrupts = <GIC_SPI 62 0x04>; 14619014203SStephen Warren status = "disabled"; 14719014203SStephen Warren }; 14819014203SStephen Warren 149c7ba99c8SStephen Warren sdhci@3460000 { 150c7ba99c8SStephen Warren compatible = "nvidia,tegra186-sdhci"; 151c7ba99c8SStephen Warren reg = <0x0 0x03460000 0x0 0x200>; 15219014203SStephen Warren resets = <&bpmp TEGRA186_RESET_SDMMC4>; 153eb3f68afSStephen Warren reset-names = "sdhci"; 15419014203SStephen Warren clocks = <&bpmp TEGRA186_CLK_SDMMC4>; 155c7ba99c8SStephen Warren interrupts = <GIC_SPI 31 0x04>; 156c7ba99c8SStephen Warren status = "disabled"; 157c7ba99c8SStephen Warren }; 158c7ba99c8SStephen Warren 15920bbde06SStephen Warren gic: interrupt-controller@3881000 { 16020bbde06SStephen Warren compatible = "arm,gic-400"; 16120bbde06SStephen Warren #interrupt-cells = <3>; 16220bbde06SStephen Warren interrupt-controller; 16320bbde06SStephen Warren reg = <0x0 0x3881000 0x0 0x1000>, 16420bbde06SStephen Warren <0x0 0x3882000 0x0 0x2000>, 16520bbde06SStephen Warren <0x0 0x3884000 0x0 0x2000>, 16620bbde06SStephen Warren <0x0 0x3886000 0x0 0x2000>; 16720bbde06SStephen Warren interrupts = <GIC_PPI 9 16820bbde06SStephen Warren (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 16920bbde06SStephen Warren interrupt-parent = <&gic>; 17020bbde06SStephen Warren }; 17120bbde06SStephen Warren 1720f67e239SStephen Warren hsp: hsp@3c00000 { 1730f67e239SStephen Warren compatible = "nvidia,tegra186-hsp"; 1740f67e239SStephen Warren reg = <0x0 0x03c00000 0x0 0xa0000>; 1750f67e239SStephen Warren interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 176729c2db7SStephen Warren interrupt-names = "doorbell"; 177729c2db7SStephen Warren #mbox-cells = <2>; 1780f67e239SStephen Warren }; 1790f67e239SStephen Warren 1809e613de0SBryan Wu gen2_i2c: i2c@c240000 { 1819e613de0SBryan Wu compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 1829e613de0SBryan Wu reg = <0x0 0xc240000 0x0 0x100>; 1839e613de0SBryan Wu interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1849e613de0SBryan Wu #address-cells = <1>; 1859e613de0SBryan Wu #size-cells = <0>; 1869e613de0SBryan Wu clocks = <&bpmp TEGRA186_CLK_I2C2>; 187b4ee081eSStephen Warren clock-names = "div-clk"; 1889e613de0SBryan Wu resets = <&bpmp TEGRA186_RESET_I2C2>; 1899e613de0SBryan Wu reset-names = "i2c"; 1909e613de0SBryan Wu status = "disabled"; 1919e613de0SBryan Wu }; 1929e613de0SBryan Wu 1939e613de0SBryan Wu gen8_i2c: i2c@c250000 { 1949e613de0SBryan Wu compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; 1959e613de0SBryan Wu reg = <0x0 0xc250000 0x0 0x100>; 1969e613de0SBryan Wu interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1979e613de0SBryan Wu #address-cells = <1>; 1989e613de0SBryan Wu #size-cells = <0>; 1999e613de0SBryan Wu clocks = <&bpmp TEGRA186_CLK_I2C8>; 200b4ee081eSStephen Warren clock-names = "div-clk"; 2019e613de0SBryan Wu resets = <&bpmp TEGRA186_RESET_I2C8>; 2029e613de0SBryan Wu reset-names = "i2c"; 2039e613de0SBryan Wu status = "disabled"; 2049e613de0SBryan Wu }; 2059e613de0SBryan Wu 20619014203SStephen Warren gpio_aon: gpio@c2f0000 { 207c7ba99c8SStephen Warren compatible = "nvidia,tegra186-gpio-aon"; 208c7ba99c8SStephen Warren reg-names = "security", "gpio"; 209c7ba99c8SStephen Warren reg = 210c7ba99c8SStephen Warren <0x0 0xc2f0000 0x0 0x1000>, 211c7ba99c8SStephen Warren <0x0 0xc2f1000 0x0 0x1000>; 212c7ba99c8SStephen Warren interrupts = 213c7ba99c8SStephen Warren <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 214c7ba99c8SStephen Warren gpio-controller; 215c7ba99c8SStephen Warren #gpio-cells = <2>; 216c7ba99c8SStephen Warren interrupt-controller; 217c7ba99c8SStephen Warren #interrupt-cells = <2>; 218c7ba99c8SStephen Warren }; 21919014203SStephen Warren 22020bbde06SStephen Warren pcie-controller@10003000 { 22120bbde06SStephen Warren compatible = "nvidia,tegra186-pcie"; 22220bbde06SStephen Warren device_type = "pci"; 22320bbde06SStephen Warren reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ 22420bbde06SStephen Warren 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ 22520bbde06SStephen Warren 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ 22620bbde06SStephen Warren reg-names = "pads", "afi", "cs"; 22720bbde06SStephen Warren interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 22820bbde06SStephen Warren <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, /* MSI interrupt */ 22920bbde06SStephen Warren <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; /* Wake interrupt */ 23020bbde06SStephen Warren interrupt-names = "intr", "msi", "wake"; 23120bbde06SStephen Warren 23220bbde06SStephen Warren #interrupt-cells = <1>; 23320bbde06SStephen Warren interrupt-map-mask = <0 0 0 0>; 23420bbde06SStephen Warren interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 23520bbde06SStephen Warren 23620bbde06SStephen Warren bus-range = <0x00 0xff>; 23720bbde06SStephen Warren #address-cells = <3>; 23820bbde06SStephen Warren #size-cells = <2>; 23920bbde06SStephen Warren 24020bbde06SStephen Warren ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ 24120bbde06SStephen Warren 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ 24220bbde06SStephen Warren 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ 24320bbde06SStephen Warren 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ 24420bbde06SStephen Warren 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07f00000 /* non-prefetchable memory (127 MiB) */ 24520bbde06SStephen Warren 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ 24620bbde06SStephen Warren 24720bbde06SStephen Warren clocks = <&bpmp TEGRA186_CLK_PCIE>, 24820bbde06SStephen Warren <&bpmp TEGRA186_CLK_AFI>; 24920bbde06SStephen Warren clock-names = "pex", "afi"; 25020bbde06SStephen Warren resets = <&bpmp TEGRA186_RESET_PCIE>, 25120bbde06SStephen Warren <&bpmp TEGRA186_RESET_AFI>, 25220bbde06SStephen Warren <&bpmp TEGRA186_RESET_PCIEXCLK>; 25320bbde06SStephen Warren reset-names = "pex", "afi", "pcie_x"; 25420bbde06SStephen Warren power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; 25520bbde06SStephen Warren status = "disabled"; 25620bbde06SStephen Warren 25720bbde06SStephen Warren pci@1,0 { 25820bbde06SStephen Warren device_type = "pci"; 25920bbde06SStephen Warren assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; 26020bbde06SStephen Warren reg = <0x000800 0 0 0 0>; 26120bbde06SStephen Warren status = "disabled"; 26220bbde06SStephen Warren 26320bbde06SStephen Warren #address-cells = <3>; 26420bbde06SStephen Warren #size-cells = <2>; 26520bbde06SStephen Warren ranges; 26620bbde06SStephen Warren 26720bbde06SStephen Warren nvidia,num-lanes = <2>; 26820bbde06SStephen Warren }; 26920bbde06SStephen Warren 27020bbde06SStephen Warren pci@2,0 { 27120bbde06SStephen Warren device_type = "pci"; 27220bbde06SStephen Warren assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; 27320bbde06SStephen Warren reg = <0x001000 0 0 0 0>; 27420bbde06SStephen Warren status = "disabled"; 27520bbde06SStephen Warren 27620bbde06SStephen Warren #address-cells = <3>; 27720bbde06SStephen Warren #size-cells = <2>; 27820bbde06SStephen Warren ranges; 27920bbde06SStephen Warren 28020bbde06SStephen Warren nvidia,num-lanes = <1>; 28120bbde06SStephen Warren }; 28220bbde06SStephen Warren 28320bbde06SStephen Warren pci@3,0 { 28420bbde06SStephen Warren device_type = "pci"; 28520bbde06SStephen Warren assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; 28620bbde06SStephen Warren reg = <0x001800 0 0 0 0>; 28720bbde06SStephen Warren status = "disabled"; 28820bbde06SStephen Warren 28920bbde06SStephen Warren #address-cells = <3>; 29020bbde06SStephen Warren #size-cells = <2>; 29120bbde06SStephen Warren ranges; 29220bbde06SStephen Warren 29320bbde06SStephen Warren nvidia,num-lanes = <1>; 29420bbde06SStephen Warren }; 29520bbde06SStephen Warren }; 29620bbde06SStephen Warren 29719014203SStephen Warren sysram@30000000 { 29819014203SStephen Warren compatible = "nvidia,tegra186-sysram", "mmio-sram"; 29919014203SStephen Warren reg = <0x0 0x30000000 0x0 0x50000>; 30019014203SStephen Warren #address-cells = <2>; 30119014203SStephen Warren #size-cells = <2>; 30219014203SStephen Warren ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; 30319014203SStephen Warren 30419014203SStephen Warren sysram_cpu_bpmp_tx: shmem@4e000 { 30519014203SStephen Warren compatible = "nvidia,tegra186-bpmp-shmem"; 30619014203SStephen Warren reg = <0x0 0x4e000 0x0 0x1000>; 30719014203SStephen Warren }; 30819014203SStephen Warren 30919014203SStephen Warren sysram_cpu_bpmp_rx: shmem@4f000 { 31019014203SStephen Warren compatible = "nvidia,tegra186-bpmp-shmem"; 31119014203SStephen Warren reg = <0x0 0x4f000 0x0 0x1000>; 31219014203SStephen Warren }; 31319014203SStephen Warren }; 31419014203SStephen Warren 31519014203SStephen Warren bpmp: bpmp { 31619014203SStephen Warren compatible = "nvidia,tegra186-bpmp"; 31719014203SStephen Warren mboxes = <&hsp HSP_MBOX_TYPE_DB HSP_DB_MASTER_BPMP>; 31819014203SStephen Warren /* 31919014203SStephen Warren * In theory, these references, and the configuration in the 32019014203SStephen Warren * node these reference point at, are board-specific, since 32119014203SStephen Warren * they depend on the BCT's memory carve-out setup, the 32219014203SStephen Warren * firmware that's actually loaded onto the BPMP, etc. However, 32319014203SStephen Warren * in practice, all boards are likely to use identical values. 32419014203SStephen Warren */ 32519014203SStephen Warren shmem = <&sysram_cpu_bpmp_tx &sysram_cpu_bpmp_rx>; 32619014203SStephen Warren #clock-cells = <1>; 32719014203SStephen Warren #power-domain-cells = <1>; 32819014203SStephen Warren #reset-cells = <1>; 32923ab5bdaSStephen Warren 33023ab5bdaSStephen Warren bpmp_i2c: i2c { 33123ab5bdaSStephen Warren compatible = "nvidia,tegra186-bpmp-i2c"; 33223ab5bdaSStephen Warren nvidia,bpmp-bus-id = <5>; 33323ab5bdaSStephen Warren #address-cells = <1>; 33423ab5bdaSStephen Warren #size-cells = <0>; 33523ab5bdaSStephen Warren status = "disabled"; 33623ab5bdaSStephen Warren }; 33719014203SStephen Warren }; 338c7ba99c8SStephen Warren}; 339