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/openbmc/u-boot/include/configs/
H A Dib62x0.h37 #define CONFIG_ENV_SECT_SIZE 0x20000
39 #define CONFIG_ENV_SIZE 0x20000
40 #define CONFIG_ENV_OFFSET 0xe0000
49 "ubifsload 0x800000 ${kernel}; " \
50 "ubifsload 0x700000 ${fdt}; " \
52 "fdt addr 0x700000; fdt resize; fdt chosen; " \
53 "bootz 0x800000 - 0x700000"
56 "console=console=ttyS0,115200\0" \
57 "mtdids=nand0=orion_nand\0" \
59 "kernel=/boot/zImage\0" \
[all …]
H A Dnsa310s.h31 #define CONFIG_ENV_SECT_SIZE 0x20000
33 #define CONFIG_ENV_SIZE 0x20000
34 #define CONFIG_ENV_OFFSET 0xe0000
41 "ubifsload 0x800000 ${kernel}; " \
42 "ubifsload 0x700000 ${fdt}; " \
44 "fdt addr 0x700000; fdt resize; fdt chosen; " \
45 "bootz 0x800000 - 0x700000"
48 "console=console=ttyS0,115200\0" \
49 "mtdids=nand0=orion_nand\0" \
51 "kernel=/boot/zImage\0" \
[all …]
H A Dguruplug.h32 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
38 #define CONFIG_ENV_SIZE 0x20000 /* 128k */
39 #define CONFIG_ENV_OFFSET 0xE0000 /* env starts here */
53 "ubifsload 0x800000 ${kernel}; " \
54 "ubifsload 0x700000 ${fdt}; " \
56 "fdt addr 0x700000; fdt resize; fdt chosen; " \
57 "bootz 0x800000 - 0x700000"
60 "console=console=ttyS0,115200\0" \
61 "mtdids=nand0=orion_nand\0" \
63 "kernel=/boot/zImage\0" \
[all …]
H A Dstmark2.h14 #define CONFIG_SYS_UART_PORT 0
29 "sf probe 0:1 50000000; " \
30 "sf read ${loadaddr} 0x100000 ${kern_size}; " \
34 "kern_size=0x700000\0" \
35 "loadaddr=0x40001000\0" \
36 "-(rootfs)\0" \
38 "sf probe 0:1 50000000; " \
39 "sf erase 0 0x80000; " \
40 "sf write ${loadaddr} 0 ${filesize}\0" \
43 "sf probe 0:1 50000000; " \
[all …]
H A Deagle.h22 #define CONFIG_ENV_OFFSET 0x700000
29 #define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
H A Dds414.h28 #define CONFIG_SYS_I2C_SLAVE 0x0
34 #define CONFIG_ENV_OFFSET 0x7E0000 /* RedBoot config partition in DTS */
72 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
73 * 0x4000.4030 bin_hdr start address
74 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
75 * 0x4007.fffc BootROM stack top
77 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
83 #define CONFIG_SPL_TEXT_BASE 0x40004030
84 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
86 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
[all …]
H A Dr7780mp.h23 #define CONFIG_SYS_SDRAM_BASE (0x08000000)
29 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
32 #define CONFIG_SYS_FLASH_BASE (0xA0000000)
39 CONFIG_SYS_FLASH_BASE + 0x100000,\
40 CONFIG_SYS_FLASH_BASE + 0x400000,\
41 CONFIG_SYS_FLASH_BASE + 0x700000, }
78 #define CONFIG_SH7780_PCI_LSR 0x07f00001
84 #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
86 #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
88 #define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/instmem/
H A Dnv04.c50 nvkm_wr32(device, 0x700000 + iobj->node->offset + offset, data); in nv04_instobj_wr32()
58 return nvkm_rd32(device, 0x700000 + iobj->node->offset + offset); in nv04_instobj_rd32()
77 return device->pri + 0x700000 + iobj->node->offset; in nv04_instobj_acquire()
136 ret = nvkm_mm_head(&imem->heap, 0, 1, size, size, align ? align : 1, &iobj->node); in nv04_instobj_new()
148 return nvkm_rd32(imem->subdev.device, 0x700000 + addr); in nv04_instmem_rd32()
154 nvkm_wr32(imem->subdev.device, 0x700000 + addr, data); in nv04_instmem_wr32()
167 ret = nvkm_mm_init(&imem->heap, 0, 0, imem->base.reserved, 1); in nv04_instmem_oneinit()
171 /* 0x00000-0x10000: reserve for probable vbios image */ in nv04_instmem_oneinit()
172 ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST, 0x10000, 0, false, in nv04_instmem_oneinit()
177 /* 0x10000-0x18000: reserve for RAMHT */ in nv04_instmem_oneinit()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_5_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_6_0_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_4_2_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
H A Duvd_3_1_sh_mask.h27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff
28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0
29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff
30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0
31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf
32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0
33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30
34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4
35 #define UVD_SEMA_CMD__MODE_MASK 0x40
36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6
[all …]
/openbmc/qemu/hw/ppc/
H A Dpnv_homer.c38 for (i = 0; i <= homer->chip->nr_cores; i++) { in core_max_array()
48 #define PNV8_OCC_PSTATE_VERSION 0x1f8001
49 #define PNV8_OCC_PSTATE_MIN 0x1f8003
50 #define PNV8_OCC_PSTATE_VALID 0x1f8000
51 #define PNV8_OCC_PSTATE_THROTTLE 0x1f8002
52 #define PNV8_OCC_PSTATE_NOM 0x1f8004
53 #define PNV8_OCC_PSTATE_TURBO 0x1f8005
54 #define PNV8_OCC_PSTATE_ULTRA_TURBO 0x1f8006
55 #define PNV8_OCC_PSTATE_DATA 0x1f8008
56 #define PNV8_OCC_PSTATE_ID_ZERO 0x1f8010
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8994-huawei-angler-rev-101.dts17 qcom,msm-id = <207 0x20000>;
18 qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
19 qcom,board-id = <8026 0>;
35 reg = <0 0x03401000 0 0x1000000>;
40 reg = <0 0x04800000 0 0x1900000>;
45 reg = <0 0x06300000 0 0x700000>;
54 pinctrl-0 = <&blsp1_uart2_default>;
/openbmc/linux/Documentation/devicetree/bindings/misc/
H A Dti,j721e-esm.yaml50 reg = <0x0 0x700000 0x0 0x1000>;
/openbmc/linux/drivers/staging/rtl8192e/rtl8192e/
H A Dr8192E_phyreg.h10 #define RF_DATA 0x1d4
12 #define rPMAC_Reset 0x100
13 #define rPMAC_TxStart 0x104
14 #define rPMAC_TxLegacySIG 0x108
15 #define rPMAC_TxHTSIG1 0x10c
16 #define rPMAC_TxHTSIG2 0x110
17 #define rPMAC_PHYDebug 0x114
18 #define rPMAC_TxPacketNum 0x118
19 #define rPMAC_TxIdle 0x11c
20 #define rPMAC_TxMACHeader0 0x120
[all …]
/openbmc/linux/arch/arm/mach-davinci/
H A Dda8xx.h33 #define DA8XX_CP_INTC_BASE 0xfffee000
37 #define DA8XX_SYSCFG0_BASE (IO_PHYS + 0x14000)
39 #define DA8XX_JTAG_ID_REG 0x18
40 #define DA8XX_HOST1CFG_REG 0x44
41 #define DA8XX_CHIPSIG_REG 0x174
42 #define DA8XX_CFGCHIP0_REG 0x17c
43 #define DA8XX_CFGCHIP1_REG 0x180
44 #define DA8XX_CFGCHIP2_REG 0x184
45 #define DA8XX_CFGCHIP3_REG 0x188
46 #define DA8XX_CFGCHIP4_REG 0x18c
[all …]
/openbmc/linux/arch/arm64/boot/dts/marvell/
H A Dac5-98dx35xx-rd.dts30 memory@0 {
32 reg = <0x2 0x00000000 0x0 0x40000000>;
37 #phy-cells = <0>;
42 phy0: ethernet-phy@0 {
43 reg = <0>;
76 spiflash0: flash@0 {
81 reg = <0>;
86 partition@0 {
88 reg = <0x0 0x800000>;
93 reg = <0x800000 0x700000>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/ti/
H A Dk3-j7200-som-p0.dtsi14 reg = <0x00 0x80000000 0x00 0x80000000>,
15 <0x08 0x80000000 0x00 0x80000000>;
24 reg = <0x00 0x9e800000 0x00 0x01800000>;
25 alignment = <0x1000>;
31 reg = <0x00 0xa0000000 0x00 0x100000>;
37 reg = <0x00 0xa0100000 0x00 0xf00000>;
43 reg = <0x00 0xa1000000 0x00 0x100000>;
49 reg = <0x00 0xa1100000 0x00 0xf00000>;
55 reg = <0x00 0xa2000000 0x00 0x100000>;
61 reg = <0x00 0xa2100000 0x00 0xf00000>;
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/ls/
H A Dls1021a-tqmls1021a.dtsi33 /* MC34VR500 DC/DC regulator at 0x8, managed by PMIC */
34 /* On-board PMC at 0x11 */
38 reg = <0x4c>;
44 reg = <0x51>;
50 reg = <0x54>;
59 reg = <0x8>;
67 qflash0: flash@0 {
74 reg = <0>;
81 uboot@0 {
83 reg = <0x0 0xe0000>;
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-ls102xa/
H A Dconfig.h9 #define OCRAM_BASE_ADDR 0x10000000
10 #define OCRAM_SIZE 0x00010000
11 #define OCRAM_BASE_S_ADDR 0x10010000
12 #define OCRAM_S_SIZE 0x00010000
14 #define CONFIG_SYS_IMMR 0x01000000
15 #define CONFIG_SYS_DCSRBAR 0x20000000
17 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00220000)
18 #define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000)
20 #define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000)
21 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
[all …]
/openbmc/linux/arch/m68k/coldfire/
H A Dstmark2.c25 .size = 0x100000,
26 .offset = 0x0
29 .size = 0x700000,
49 .bus_num = 0,
56 /* SPI controller data, SPI (0) */
59 .bus_num = 0,
65 [0] = {
67 .end = MCFDSPI_BASE0 + 0xFF,
87 .id = 0,
107 __raw_writeb(0x80, MCFGPIO_PAR_DSPIOWL); in init_stmark2()
[all …]
/openbmc/u-boot/drivers/net/
H A Dnatsemi.c61 #define EEPROM_SIZE 0xb /*12 16-bit chunks, or 24 bytes*/
63 #define DSIZE 0x00000FFF
75 ChipCmd = 0x00,
76 ChipConfig = 0x04,
77 EECtrl = 0x08,
78 IntrMask = 0x14,
79 IntrEnable = 0x18,
80 TxRingPtr = 0x20,
81 TxConfig = 0x24,
82 RxRingPtr = 0x30,
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/
H A Dnv04.c36 0x0040053c,
37 0x00400544,
38 0x00400540,
39 0x00400548,
48 0x00400184,
49 0x004001a4,
50 0x004001c4,
51 0x004001e4,
52 0x00400188,
53 0x004001a8,
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dmmu_masks.h23 #define MMU_INPUT_FIFO_THRESHOLD_PCI_SHIFT 0
24 #define MMU_INPUT_FIFO_THRESHOLD_PCI_MASK 0x7
26 #define MMU_INPUT_FIFO_THRESHOLD_PSOC_MASK 0x70
28 #define MMU_INPUT_FIFO_THRESHOLD_DMA_MASK 0x700
30 #define MMU_INPUT_FIFO_THRESHOLD_CPU_MASK 0x7000
32 #define MMU_INPUT_FIFO_THRESHOLD_MME_MASK 0x70000
34 #define MMU_INPUT_FIFO_THRESHOLD_TPC_MASK 0x700000
36 #define MMU_INPUT_FIFO_THRESHOLD_OTHER_MASK 0x7000000
39 #define MMU_MMU_ENABLE_R_SHIFT 0
40 #define MMU_MMU_ENABLE_R_MASK 0x1
[all …]

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