1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2018 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef ASIC_REG_MMU_MASKS_H_ 14*e65e175bSOded Gabbay #define ASIC_REG_MMU_MASKS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay /* 17*e65e175bSOded Gabbay ***************************************** 18*e65e175bSOded Gabbay * MMU (Prototype: MMU) 19*e65e175bSOded Gabbay ***************************************** 20*e65e175bSOded Gabbay */ 21*e65e175bSOded Gabbay 22*e65e175bSOded Gabbay /* MMU_INPUT_FIFO_THRESHOLD */ 23*e65e175bSOded Gabbay #define MMU_INPUT_FIFO_THRESHOLD_PCI_SHIFT 0 24*e65e175bSOded Gabbay #define MMU_INPUT_FIFO_THRESHOLD_PCI_MASK 0x7 25*e65e175bSOded Gabbay #define MMU_INPUT_FIFO_THRESHOLD_PSOC_SHIFT 4 26*e65e175bSOded Gabbay #define MMU_INPUT_FIFO_THRESHOLD_PSOC_MASK 0x70 27*e65e175bSOded Gabbay #define MMU_INPUT_FIFO_THRESHOLD_DMA_SHIFT 8 28*e65e175bSOded Gabbay #define MMU_INPUT_FIFO_THRESHOLD_DMA_MASK 0x700 29*e65e175bSOded Gabbay #define MMU_INPUT_FIFO_THRESHOLD_CPU_SHIFT 12 30*e65e175bSOded Gabbay #define MMU_INPUT_FIFO_THRESHOLD_CPU_MASK 0x7000 31*e65e175bSOded Gabbay #define MMU_INPUT_FIFO_THRESHOLD_MME_SHIFT 16 32*e65e175bSOded Gabbay #define MMU_INPUT_FIFO_THRESHOLD_MME_MASK 0x70000 33*e65e175bSOded Gabbay #define MMU_INPUT_FIFO_THRESHOLD_TPC_SHIFT 20 34*e65e175bSOded Gabbay #define MMU_INPUT_FIFO_THRESHOLD_TPC_MASK 0x700000 35*e65e175bSOded Gabbay #define MMU_INPUT_FIFO_THRESHOLD_OTHER_SHIFT 24 36*e65e175bSOded Gabbay #define MMU_INPUT_FIFO_THRESHOLD_OTHER_MASK 0x7000000 37*e65e175bSOded Gabbay 38*e65e175bSOded Gabbay /* MMU_MMU_ENABLE */ 39*e65e175bSOded Gabbay #define MMU_MMU_ENABLE_R_SHIFT 0 40*e65e175bSOded Gabbay #define MMU_MMU_ENABLE_R_MASK 0x1 41*e65e175bSOded Gabbay 42*e65e175bSOded Gabbay /* MMU_FORCE_ORDERING */ 43*e65e175bSOded Gabbay #define MMU_FORCE_ORDERING_DMA_WEAK_ORDERING_SHIFT 0 44*e65e175bSOded Gabbay #define MMU_FORCE_ORDERING_DMA_WEAK_ORDERING_MASK 0x1 45*e65e175bSOded Gabbay #define MMU_FORCE_ORDERING_PSOC_WEAK_ORDERING_SHIFT 1 46*e65e175bSOded Gabbay #define MMU_FORCE_ORDERING_PSOC_WEAK_ORDERING_MASK 0x2 47*e65e175bSOded Gabbay #define MMU_FORCE_ORDERING_PCI_WEAK_ORDERING_SHIFT 2 48*e65e175bSOded Gabbay #define MMU_FORCE_ORDERING_PCI_WEAK_ORDERING_MASK 0x4 49*e65e175bSOded Gabbay #define MMU_FORCE_ORDERING_CPU_WEAK_ORDERING_SHIFT 3 50*e65e175bSOded Gabbay #define MMU_FORCE_ORDERING_CPU_WEAK_ORDERING_MASK 0x8 51*e65e175bSOded Gabbay #define MMU_FORCE_ORDERING_MME_WEAK_ORDERING_SHIFT 4 52*e65e175bSOded Gabbay #define MMU_FORCE_ORDERING_MME_WEAK_ORDERING_MASK 0x10 53*e65e175bSOded Gabbay #define MMU_FORCE_ORDERING_TPC_WEAK_ORDERING_SHIFT 5 54*e65e175bSOded Gabbay #define MMU_FORCE_ORDERING_TPC_WEAK_ORDERING_MASK 0x20 55*e65e175bSOded Gabbay #define MMU_FORCE_ORDERING_DEFAULT_WEAK_ORDERING_SHIFT 6 56*e65e175bSOded Gabbay #define MMU_FORCE_ORDERING_DEFAULT_WEAK_ORDERING_MASK 0x40 57*e65e175bSOded Gabbay #define MMU_FORCE_ORDERING_DMA_STRONG_ORDERING_SHIFT 8 58*e65e175bSOded Gabbay #define MMU_FORCE_ORDERING_DMA_STRONG_ORDERING_MASK 0x100 59*e65e175bSOded Gabbay #define MMU_FORCE_ORDERING_PSOC_STRONG_ORDERING_SHIFT 9 60*e65e175bSOded Gabbay #define MMU_FORCE_ORDERING_PSOC_STRONG_ORDERING_MASK 0x200 61*e65e175bSOded Gabbay #define MMU_FORCE_ORDERING_PCI_STRONG_ORDERING_SHIFT 10 62*e65e175bSOded Gabbay #define MMU_FORCE_ORDERING_PCI_STRONG_ORDERING_MASK 0x400 63*e65e175bSOded Gabbay #define MMU_FORCE_ORDERING_CPU_STRONG_ORDERING_SHIFT 11 64*e65e175bSOded Gabbay #define MMU_FORCE_ORDERING_CPU_STRONG_ORDERING_MASK 0x800 65*e65e175bSOded Gabbay #define MMU_FORCE_ORDERING_MME_STRONG_ORDERING_SHIFT 12 66*e65e175bSOded Gabbay #define MMU_FORCE_ORDERING_MME_STRONG_ORDERING_MASK 0x1000 67*e65e175bSOded Gabbay #define MMU_FORCE_ORDERING_TPC_STRONG_ORDERING_SHIFT 13 68*e65e175bSOded Gabbay #define MMU_FORCE_ORDERING_TPC_STRONG_ORDERING_MASK 0x2000 69*e65e175bSOded Gabbay #define MMU_FORCE_ORDERING_DEFAULT_STRONG_ORDERING_SHIFT 14 70*e65e175bSOded Gabbay #define MMU_FORCE_ORDERING_DEFAULT_STRONG_ORDERING_MASK 0x4000 71*e65e175bSOded Gabbay 72*e65e175bSOded Gabbay /* MMU_FEATURE_ENABLE */ 73*e65e175bSOded Gabbay #define MMU_FEATURE_ENABLE_VA_ORDERING_EN_SHIFT 0 74*e65e175bSOded Gabbay #define MMU_FEATURE_ENABLE_VA_ORDERING_EN_MASK 0x1 75*e65e175bSOded Gabbay #define MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_SHIFT 1 76*e65e175bSOded Gabbay #define MMU_FEATURE_ENABLE_CLEAN_LINK_LIST_MASK 0x2 77*e65e175bSOded Gabbay #define MMU_FEATURE_ENABLE_HOP_OFFSET_EN_SHIFT 2 78*e65e175bSOded Gabbay #define MMU_FEATURE_ENABLE_HOP_OFFSET_EN_MASK 0x4 79*e65e175bSOded Gabbay #define MMU_FEATURE_ENABLE_OBI_ORDERING_EN_SHIFT 3 80*e65e175bSOded Gabbay #define MMU_FEATURE_ENABLE_OBI_ORDERING_EN_MASK 0x8 81*e65e175bSOded Gabbay #define MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_SHIFT 4 82*e65e175bSOded Gabbay #define MMU_FEATURE_ENABLE_STRONG_ORDERING_READ_EN_MASK 0x10 83*e65e175bSOded Gabbay #define MMU_FEATURE_ENABLE_TRACE_ENABLE_SHIFT 5 84*e65e175bSOded Gabbay #define MMU_FEATURE_ENABLE_TRACE_ENABLE_MASK 0x20 85*e65e175bSOded Gabbay 86*e65e175bSOded Gabbay /* MMU_VA_ORDERING_MASK_31_7 */ 87*e65e175bSOded Gabbay #define MMU_VA_ORDERING_MASK_31_7_R_SHIFT 0 88*e65e175bSOded Gabbay #define MMU_VA_ORDERING_MASK_31_7_R_MASK 0x1FFFFFF 89*e65e175bSOded Gabbay 90*e65e175bSOded Gabbay /* MMU_VA_ORDERING_MASK_49_32 */ 91*e65e175bSOded Gabbay #define MMU_VA_ORDERING_MASK_49_32_R_SHIFT 0 92*e65e175bSOded Gabbay #define MMU_VA_ORDERING_MASK_49_32_R_MASK 0x3FFFF 93*e65e175bSOded Gabbay 94*e65e175bSOded Gabbay /* MMU_LOG2_DDR_SIZE */ 95*e65e175bSOded Gabbay #define MMU_LOG2_DDR_SIZE_R_SHIFT 0 96*e65e175bSOded Gabbay #define MMU_LOG2_DDR_SIZE_R_MASK 0xFF 97*e65e175bSOded Gabbay 98*e65e175bSOded Gabbay /* MMU_SCRAMBLER */ 99*e65e175bSOded Gabbay #define MMU_SCRAMBLER_ADDR_BIT_SHIFT 0 100*e65e175bSOded Gabbay #define MMU_SCRAMBLER_ADDR_BIT_MASK 0x3F 101*e65e175bSOded Gabbay #define MMU_SCRAMBLER_SINGLE_DDR_EN_SHIFT 6 102*e65e175bSOded Gabbay #define MMU_SCRAMBLER_SINGLE_DDR_EN_MASK 0x40 103*e65e175bSOded Gabbay #define MMU_SCRAMBLER_SINGLE_DDR_ID_SHIFT 7 104*e65e175bSOded Gabbay #define MMU_SCRAMBLER_SINGLE_DDR_ID_MASK 0x80 105*e65e175bSOded Gabbay 106*e65e175bSOded Gabbay /* MMU_MEM_INIT_BUSY */ 107*e65e175bSOded Gabbay #define MMU_MEM_INIT_BUSY_DATA_SHIFT 0 108*e65e175bSOded Gabbay #define MMU_MEM_INIT_BUSY_DATA_MASK 0x3 109*e65e175bSOded Gabbay #define MMU_MEM_INIT_BUSY_OBI0_SHIFT 2 110*e65e175bSOded Gabbay #define MMU_MEM_INIT_BUSY_OBI0_MASK 0x4 111*e65e175bSOded Gabbay #define MMU_MEM_INIT_BUSY_OBI1_SHIFT 3 112*e65e175bSOded Gabbay #define MMU_MEM_INIT_BUSY_OBI1_MASK 0x8 113*e65e175bSOded Gabbay 114*e65e175bSOded Gabbay /* MMU_SPI_MASK */ 115*e65e175bSOded Gabbay #define MMU_SPI_MASK_R_SHIFT 0 116*e65e175bSOded Gabbay #define MMU_SPI_MASK_R_MASK 0xFF 117*e65e175bSOded Gabbay 118*e65e175bSOded Gabbay /* MMU_SPI_CAUSE */ 119*e65e175bSOded Gabbay #define MMU_SPI_CAUSE_R_SHIFT 0 120*e65e175bSOded Gabbay #define MMU_SPI_CAUSE_R_MASK 0xFF 121*e65e175bSOded Gabbay 122*e65e175bSOded Gabbay /* MMU_PAGE_ERROR_CAPTURE */ 123*e65e175bSOded Gabbay #define MMU_PAGE_ERROR_CAPTURE_VA_49_32_SHIFT 0 124*e65e175bSOded Gabbay #define MMU_PAGE_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF 125*e65e175bSOded Gabbay #define MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_SHIFT 18 126*e65e175bSOded Gabbay #define MMU_PAGE_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000 127*e65e175bSOded Gabbay 128*e65e175bSOded Gabbay /* MMU_PAGE_ERROR_CAPTURE_VA */ 129*e65e175bSOded Gabbay #define MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_SHIFT 0 130*e65e175bSOded Gabbay #define MMU_PAGE_ERROR_CAPTURE_VA_VA_31_0_MASK 0xFFFFFFFF 131*e65e175bSOded Gabbay 132*e65e175bSOded Gabbay /* MMU_ACCESS_ERROR_CAPTURE */ 133*e65e175bSOded Gabbay #define MMU_ACCESS_ERROR_CAPTURE_VA_49_32_SHIFT 0 134*e65e175bSOded Gabbay #define MMU_ACCESS_ERROR_CAPTURE_VA_49_32_MASK 0x3FFFF 135*e65e175bSOded Gabbay #define MMU_ACCESS_ERROR_CAPTURE_ENTRY_VALID_SHIFT 18 136*e65e175bSOded Gabbay #define MMU_ACCESS_ERROR_CAPTURE_ENTRY_VALID_MASK 0x40000 137*e65e175bSOded Gabbay 138*e65e175bSOded Gabbay /* MMU_ACCESS_ERROR_CAPTURE_VA */ 139*e65e175bSOded Gabbay #define MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_SHIFT 0 140*e65e175bSOded Gabbay #define MMU_ACCESS_ERROR_CAPTURE_VA_VA_31_0_MASK 0xFFFFFFFF 141*e65e175bSOded Gabbay 142*e65e175bSOded Gabbay #endif /* ASIC_REG_MMU_MASKS_H_ */ 143