/openbmc/linux/drivers/accel/habanalabs/include/goya/asic_reg/ |
H A D | mme1_rtr_masks.h | 23 #define MME1_RTR_HBW_RD_RQ_E_ARB_W_SHIFT 0 24 #define MME1_RTR_HBW_RD_RQ_E_ARB_W_MASK 0x7 26 #define MME1_RTR_HBW_RD_RQ_E_ARB_S_MASK 0x700 28 #define MME1_RTR_HBW_RD_RQ_E_ARB_N_MASK 0x70000 30 #define MME1_RTR_HBW_RD_RQ_E_ARB_L_MASK 0x7000000 33 #define MME1_RTR_HBW_RD_RQ_W_ARB_E_SHIFT 0 34 #define MME1_RTR_HBW_RD_RQ_W_ARB_E_MASK 0x7 36 #define MME1_RTR_HBW_RD_RQ_W_ARB_S_MASK 0x700 38 #define MME1_RTR_HBW_RD_RQ_W_ARB_N_MASK 0x70000 40 #define MME1_RTR_HBW_RD_RQ_W_ARB_L_MASK 0x7000000 [all …]
|
H A D | dma_nrtr_masks.h | 23 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0 24 #define DMA_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F 26 #define DMA_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00 28 #define DMA_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000 30 #define DMA_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000 33 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0 34 #define DMA_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F 36 #define DMA_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00 38 #define DMA_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000 40 #define DMA_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000 [all …]
|
H A D | tpc0_nrtr_masks.h | 23 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0 24 #define TPC0_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F 26 #define TPC0_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00 28 #define TPC0_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000 30 #define TPC0_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000 33 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0 34 #define TPC0_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F 36 #define TPC0_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00 38 #define TPC0_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000 40 #define TPC0_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000 [all …]
|
H A D | pci_nrtr_masks.h | 23 #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0 24 #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F 26 #define PCI_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00 28 #define PCI_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000 30 #define PCI_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000 33 #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0 34 #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F 36 #define PCI_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00 38 #define PCI_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000 40 #define PCI_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000 [all …]
|
H A D | tpc0_cfg_masks.h | 23 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 0 24 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 27 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 0 28 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 31 #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_SHIFT 0 32 #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF 35 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 36 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK 0x3 38 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 40 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 [all …]
|
H A D | mme_masks.h | 23 #define MME_ARCH_STATUS_A_SHIFT 0 24 #define MME_ARCH_STATUS_A_MASK 0x1 26 #define MME_ARCH_STATUS_B_MASK 0x2 28 #define MME_ARCH_STATUS_CIN_MASK 0x4 30 #define MME_ARCH_STATUS_COUT_MASK 0x8 32 #define MME_ARCH_STATUS_TE_MASK 0x10 34 #define MME_ARCH_STATUS_LD_MASK 0x20 36 #define MME_ARCH_STATUS_ST_MASK 0x40 38 #define MME_ARCH_STATUS_SB_A_EMPTY_MASK 0x80 40 #define MME_ARCH_STATUS_SB_B_EMPTY_MASK 0x100 [all …]
|
/openbmc/linux/drivers/accel/habanalabs/include/gaudi/asic_reg/ |
H A D | tpc0_cfg_masks.h | 23 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 0 24 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 27 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 0 28 #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 31 #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_SHIFT 0 32 #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF 35 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 36 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 38 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 40 #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 [all …]
|
/openbmc/openbmc/meta-phosphor/dynamic-layers/aspeed-layer/recipes-bsp/u-boot/files/ |
H A D | 0001-configs-ast-Add-redundnant-env.patch | 22 #define CONFIG_ENV_ADDR (AST_FMC_CS0_BASE + 0x60000) 23 +#define CONFIG_ENV_ADDR_REDUND (AST_FMC_CS0_BASE + 0x70000) 25 #define CONFIG_ENV_OFFSET 0x60000 /* environment starts here */ 26 -#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ 27 +#define CONFIG_ENV_OFFSET_REDUND 0x70000 28 +#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ 29 +#define CONFIG_ENV_SIZE_REDUND 0x10000
|
H A D | 0003-config-ast-common-Add-bootopts-to-support-ubi-and-mt.patch | 1 From 0c77be343fc4781719dcc0748bc29a26ea83e0a3 Mon Sep 17 00:00:00 2001 32 #if 0 36 +#define CONFIG_BOOTARGS "console=ttyS4,115200n8 ubi.mtd=obmc-ubi,0,0,0 ubi.mtd=alt-obmc-ubi,0,0,… 42 #define CONFIG_ENV_ADDR (AST_FMC_CS0_BASE + 0x60000) 43 #define CONFIG_ENV_ADDR_REDUND (AST_FMC_CS0_BASE + 0x70000) 46 #define CONFIG_ENV_OFFSET 0x60000 /* environment starts here */ 47 #define CONFIG_ENV_OFFSET_REDUND 0x70000 48 #define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ 49 #define CONFIG_ENV_SIZE_REDUND 0x10000 56 + "ubiblock=0,1 \0" \ [all …]
|
/openbmc/u-boot/board/congatec/cgtqmx6eval/ |
H A D | README | 32 => tftp 0x12000000 SPL 34 => sf erase 0x0 0x10000 36 => sf write 0x12000000 0x400 0x10000 38 => tftp 0x12000000 u-boot.img 40 => sf erase 0x10000 0x70000 42 => sf write 0x12000000 0x10000 0x70000 72 => mw.l 0x20d8040 0x3850 73 => mw.l 0x020d8044 0x10000000
|
/openbmc/linux/drivers/clk/imx/ |
H A D | clk-imx8qxp-lpcg.h | 11 #define LSIO_PWM_0_LPCG 0x00000 12 #define LSIO_PWM_1_LPCG 0x10000 13 #define LSIO_PWM_2_LPCG 0x20000 14 #define LSIO_PWM_3_LPCG 0x30000 15 #define LSIO_PWM_4_LPCG 0x40000 16 #define LSIO_PWM_5_LPCG 0x50000 17 #define LSIO_PWM_6_LPCG 0x60000 18 #define LSIO_PWM_7_LPCG 0x70000 19 #define LSIO_GPIO_0_LPCG 0x80000 20 #define LSIO_GPIO_1_LPCG 0x90000 [all …]
|
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/ |
H A D | uvd_5_0_sh_mask.h | 27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff 28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0 29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff 30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0 31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf 32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30 34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 35 #define UVD_SEMA_CMD__MODE_MASK 0x40 36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6 [all …]
|
H A D | uvd_6_0_sh_mask.h | 27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff 28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0 29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff 30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0 31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf 32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30 34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 35 #define UVD_SEMA_CMD__MODE_MASK 0x40 36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6 [all …]
|
H A D | uvd_4_2_sh_mask.h | 27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff 28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0 29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff 30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0 31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf 32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30 34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 35 #define UVD_SEMA_CMD__MODE_MASK 0x40 36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6 [all …]
|
H A D | uvd_3_1_sh_mask.h | 27 #define UVD_SEMA_ADDR_LOW__ADDR_22_3_MASK 0xfffff 28 #define UVD_SEMA_ADDR_LOW__ADDR_22_3__SHIFT 0x0 29 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23_MASK 0xfffff 30 #define UVD_SEMA_ADDR_HIGH__ADDR_42_23__SHIFT 0x0 31 #define UVD_SEMA_CMD__REQ_CMD_MASK 0xf 32 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 33 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x30 34 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 35 #define UVD_SEMA_CMD__MODE_MASK 0x40 36 #define UVD_SEMA_CMD__MODE__SHIFT 0x6 [all …]
|
/openbmc/u-boot/include/configs/ |
H A D | lacie_kw.h | 79 #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */ 109 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 113 #define CONFIG_SYS_I2C_G762_ADDR 0x3e 128 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64KB */ 129 #define CONFIG_ENV_SIZE 0x1000 /* 4KB */ 130 #define CONFIG_ENV_ADDR 0x70000 131 #define CONFIG_ENV_OFFSET 0x70000 /* env starts here */ 141 "stdin=serial\0" \ 142 "stdout=serial\0" \ 143 "stderr=serial\0" \ [all …]
|
/openbmc/linux/drivers/gpu/drm/msm/disp/mdp5/ |
H A D | mdp5_cfg.c | 22 0, 35 .base = { 0x00500, 0x00600, 0x00700, 0x00800, 0x00900 }, 36 .flush_hw_mask = 0x0003ffff, 40 .base = { 0x01100, 0x01500, 0x01900 }, 45 0, 49 .base = { 0x01d00, 0x02100, 0x02500 }, 53 0, 57 .base = { 0x02900, 0x02d00 }, 60 0, 64 .base = { 0x03100, 0x03500, 0x03900, 0x03d00, 0x04100 }, [all …]
|
/openbmc/linux/arch/arm/boot/dts/realtek/ |
H A D | rtd1195.dtsi | 6 /memreserve/ 0x00000000 0x0000a800; /* boot code */ 7 /memreserve/ 0x0000a800 0x000f5800; 8 /memreserve/ 0x17fff000 0x00001000; 21 #size-cells = <0>; 23 cpu0: cpu@0 { 26 reg = <0x0>; 33 reg = <0x1>; 44 reg = <0x0000b000 0x1000>; 48 reg = <0x01b00000 0x400000>; 52 reg = <0x01ffe000 0x4000>; [all …]
|
/openbmc/linux/arch/arm/mach-orion5x/ |
H A D | orion5x.h | 36 #define ORION5X_REGS_PHYS_BASE 0xf1000000 37 #define ORION5X_REGS_VIRT_BASE IOMEM(0xfec00000) 40 #define ORION5X_PCIE_IO_PHYS_BASE 0xf2000000 41 #define ORION5X_PCIE_IO_BUS_BASE 0x00000000 44 #define ORION5X_PCI_IO_PHYS_BASE 0xf2100000 45 #define ORION5X_PCI_IO_BUS_BASE 0x00010000 48 #define ORION5X_SRAM_PHYS_BASE (0xf2200000) 52 #define ORION5X_PCIE_WA_PHYS_BASE 0xf0000000 53 #define ORION5X_PCIE_WA_VIRT_BASE IOMEM(0xfd000000) 56 #define ORION5X_PCIE_MEM_PHYS_BASE 0xe0000000 [all …]
|
/openbmc/linux/arch/arm/boot/dts/st/ |
H A D | spear600-evb.dts | 17 reg = <0 0x10000000>; 55 reg = <0xf8000000 0x800000>; 63 partition@0 { 65 reg = <0x0 0x10000>; 69 reg = <0x10000 0x50000>; 73 reg = <0x60000 0x10000>; 77 reg = <0x70000 0x10000>; 81 reg = <0x80000 0x310000>; 85 reg = <0x390000 0x0>;
|
/openbmc/linux/Documentation/devicetree/bindings/mmc/ |
H A D | amlogic,meson-gx-mmc.yaml | 70 reg = <0x70000 0x2000>; 74 pinctrl-0 = <&emm_pins>;
|
/openbmc/linux/Documentation/devicetree/bindings/usb/ |
H A D | ti,keystone-dwc3.yaml | 47 PHY specifier for the USB3.0 PHY. Some SoCs need the USB3.0 PHY 81 reg = <0x2680000 0x10000>; 88 reg = <0x2690000 0x70000>;
|
/openbmc/linux/arch/arm64/boot/dts/freescale/ |
H A D | qoriq-bman-portals.dtsi | 14 bman-portal@0 { 20 reg = <0x0 0x4000>, <0x4000000 0x4000>; 26 reg = <0x10000 0x4000>, <0x4010000 0x4000>; 32 reg = <0x20000 0x4000>, <0x4020000 0x4000>; 38 reg = <0x30000 0x4000>, <0x4030000 0x4000>; 44 reg = <0x40000 0x4000>, <0x4040000 0x4000>; 50 reg = <0x50000 0x4000>, <0x4050000 0x4000>; 56 reg = <0x60000 0x4000>, <0x4060000 0x4000>; 62 reg = <0x70000 0x4000>, <0x4070000 0x4000>; 68 reg = <0x80000 0x4000>, <0x4080000 0x4000>; [all …]
|
/openbmc/u-boot/arch/arm/dts/ |
H A D | zynq-topic-miami.dts | 23 memory@0 { 25 reg = <0x0 0x40000000>; 36 is-dual = <0>; 38 flash@0 { 41 reg = <0x0>; 49 reg = <0x00000 0x10000>; 53 reg = <0x10000 0x60000>; 57 reg = <0x70000 0x10000>; 61 reg = <0x80000 0x400000>; 65 reg = <0x480000 0x1b80000>;
|
/openbmc/linux/Documentation/devicetree/bindings/net/ |
H A D | marvell-armada-370-neta.txt | 41 reg = <0x70000 0x2500>; 48 bm,pool-long = <0>;
|