1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2018 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef ASIC_REG_PCI_NRTR_MASKS_H_ 14*e65e175bSOded Gabbay #define ASIC_REG_PCI_NRTR_MASKS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay /* 17*e65e175bSOded Gabbay ***************************************** 18*e65e175bSOded Gabbay * PCI_NRTR (Prototype: IF_NRTR) 19*e65e175bSOded Gabbay ***************************************** 20*e65e175bSOded Gabbay */ 21*e65e175bSOded Gabbay 22*e65e175bSOded Gabbay /* PCI_NRTR_HBW_MAX_CRED */ 23*e65e175bSOded Gabbay #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_SHIFT 0 24*e65e175bSOded Gabbay #define PCI_NRTR_HBW_MAX_CRED_WR_RQ_MASK 0x3F 25*e65e175bSOded Gabbay #define PCI_NRTR_HBW_MAX_CRED_WR_RS_SHIFT 8 26*e65e175bSOded Gabbay #define PCI_NRTR_HBW_MAX_CRED_WR_RS_MASK 0x3F00 27*e65e175bSOded Gabbay #define PCI_NRTR_HBW_MAX_CRED_RD_RQ_SHIFT 16 28*e65e175bSOded Gabbay #define PCI_NRTR_HBW_MAX_CRED_RD_RQ_MASK 0x3F0000 29*e65e175bSOded Gabbay #define PCI_NRTR_HBW_MAX_CRED_RD_RS_SHIFT 24 30*e65e175bSOded Gabbay #define PCI_NRTR_HBW_MAX_CRED_RD_RS_MASK 0x3F000000 31*e65e175bSOded Gabbay 32*e65e175bSOded Gabbay /* PCI_NRTR_LBW_MAX_CRED */ 33*e65e175bSOded Gabbay #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_SHIFT 0 34*e65e175bSOded Gabbay #define PCI_NRTR_LBW_MAX_CRED_WR_RQ_MASK 0x3F 35*e65e175bSOded Gabbay #define PCI_NRTR_LBW_MAX_CRED_WR_RS_SHIFT 8 36*e65e175bSOded Gabbay #define PCI_NRTR_LBW_MAX_CRED_WR_RS_MASK 0x3F00 37*e65e175bSOded Gabbay #define PCI_NRTR_LBW_MAX_CRED_RD_RQ_SHIFT 16 38*e65e175bSOded Gabbay #define PCI_NRTR_LBW_MAX_CRED_RD_RQ_MASK 0x3F0000 39*e65e175bSOded Gabbay #define PCI_NRTR_LBW_MAX_CRED_RD_RS_SHIFT 24 40*e65e175bSOded Gabbay #define PCI_NRTR_LBW_MAX_CRED_RD_RS_MASK 0x3F000000 41*e65e175bSOded Gabbay 42*e65e175bSOded Gabbay /* PCI_NRTR_DBG_E_ARB */ 43*e65e175bSOded Gabbay #define PCI_NRTR_DBG_E_ARB_W_SHIFT 0 44*e65e175bSOded Gabbay #define PCI_NRTR_DBG_E_ARB_W_MASK 0x7 45*e65e175bSOded Gabbay #define PCI_NRTR_DBG_E_ARB_S_SHIFT 8 46*e65e175bSOded Gabbay #define PCI_NRTR_DBG_E_ARB_S_MASK 0x700 47*e65e175bSOded Gabbay #define PCI_NRTR_DBG_E_ARB_N_SHIFT 16 48*e65e175bSOded Gabbay #define PCI_NRTR_DBG_E_ARB_N_MASK 0x70000 49*e65e175bSOded Gabbay #define PCI_NRTR_DBG_E_ARB_L_SHIFT 24 50*e65e175bSOded Gabbay #define PCI_NRTR_DBG_E_ARB_L_MASK 0x7000000 51*e65e175bSOded Gabbay 52*e65e175bSOded Gabbay /* PCI_NRTR_DBG_W_ARB */ 53*e65e175bSOded Gabbay #define PCI_NRTR_DBG_W_ARB_E_SHIFT 0 54*e65e175bSOded Gabbay #define PCI_NRTR_DBG_W_ARB_E_MASK 0x7 55*e65e175bSOded Gabbay #define PCI_NRTR_DBG_W_ARB_S_SHIFT 8 56*e65e175bSOded Gabbay #define PCI_NRTR_DBG_W_ARB_S_MASK 0x700 57*e65e175bSOded Gabbay #define PCI_NRTR_DBG_W_ARB_N_SHIFT 16 58*e65e175bSOded Gabbay #define PCI_NRTR_DBG_W_ARB_N_MASK 0x70000 59*e65e175bSOded Gabbay #define PCI_NRTR_DBG_W_ARB_L_SHIFT 24 60*e65e175bSOded Gabbay #define PCI_NRTR_DBG_W_ARB_L_MASK 0x7000000 61*e65e175bSOded Gabbay 62*e65e175bSOded Gabbay /* PCI_NRTR_DBG_N_ARB */ 63*e65e175bSOded Gabbay #define PCI_NRTR_DBG_N_ARB_W_SHIFT 0 64*e65e175bSOded Gabbay #define PCI_NRTR_DBG_N_ARB_W_MASK 0x7 65*e65e175bSOded Gabbay #define PCI_NRTR_DBG_N_ARB_E_SHIFT 8 66*e65e175bSOded Gabbay #define PCI_NRTR_DBG_N_ARB_E_MASK 0x700 67*e65e175bSOded Gabbay #define PCI_NRTR_DBG_N_ARB_S_SHIFT 16 68*e65e175bSOded Gabbay #define PCI_NRTR_DBG_N_ARB_S_MASK 0x70000 69*e65e175bSOded Gabbay #define PCI_NRTR_DBG_N_ARB_L_SHIFT 24 70*e65e175bSOded Gabbay #define PCI_NRTR_DBG_N_ARB_L_MASK 0x7000000 71*e65e175bSOded Gabbay 72*e65e175bSOded Gabbay /* PCI_NRTR_DBG_S_ARB */ 73*e65e175bSOded Gabbay #define PCI_NRTR_DBG_S_ARB_W_SHIFT 0 74*e65e175bSOded Gabbay #define PCI_NRTR_DBG_S_ARB_W_MASK 0x7 75*e65e175bSOded Gabbay #define PCI_NRTR_DBG_S_ARB_E_SHIFT 8 76*e65e175bSOded Gabbay #define PCI_NRTR_DBG_S_ARB_E_MASK 0x700 77*e65e175bSOded Gabbay #define PCI_NRTR_DBG_S_ARB_N_SHIFT 16 78*e65e175bSOded Gabbay #define PCI_NRTR_DBG_S_ARB_N_MASK 0x70000 79*e65e175bSOded Gabbay #define PCI_NRTR_DBG_S_ARB_L_SHIFT 24 80*e65e175bSOded Gabbay #define PCI_NRTR_DBG_S_ARB_L_MASK 0x7000000 81*e65e175bSOded Gabbay 82*e65e175bSOded Gabbay /* PCI_NRTR_DBG_L_ARB */ 83*e65e175bSOded Gabbay #define PCI_NRTR_DBG_L_ARB_W_SHIFT 0 84*e65e175bSOded Gabbay #define PCI_NRTR_DBG_L_ARB_W_MASK 0x7 85*e65e175bSOded Gabbay #define PCI_NRTR_DBG_L_ARB_E_SHIFT 8 86*e65e175bSOded Gabbay #define PCI_NRTR_DBG_L_ARB_E_MASK 0x700 87*e65e175bSOded Gabbay #define PCI_NRTR_DBG_L_ARB_S_SHIFT 16 88*e65e175bSOded Gabbay #define PCI_NRTR_DBG_L_ARB_S_MASK 0x70000 89*e65e175bSOded Gabbay #define PCI_NRTR_DBG_L_ARB_N_SHIFT 24 90*e65e175bSOded Gabbay #define PCI_NRTR_DBG_L_ARB_N_MASK 0x7000000 91*e65e175bSOded Gabbay 92*e65e175bSOded Gabbay /* PCI_NRTR_DBG_E_ARB_MAX */ 93*e65e175bSOded Gabbay #define PCI_NRTR_DBG_E_ARB_MAX_CREDIT_SHIFT 0 94*e65e175bSOded Gabbay #define PCI_NRTR_DBG_E_ARB_MAX_CREDIT_MASK 0x3F 95*e65e175bSOded Gabbay 96*e65e175bSOded Gabbay /* PCI_NRTR_DBG_W_ARB_MAX */ 97*e65e175bSOded Gabbay #define PCI_NRTR_DBG_W_ARB_MAX_CREDIT_SHIFT 0 98*e65e175bSOded Gabbay #define PCI_NRTR_DBG_W_ARB_MAX_CREDIT_MASK 0x3F 99*e65e175bSOded Gabbay 100*e65e175bSOded Gabbay /* PCI_NRTR_DBG_N_ARB_MAX */ 101*e65e175bSOded Gabbay #define PCI_NRTR_DBG_N_ARB_MAX_CREDIT_SHIFT 0 102*e65e175bSOded Gabbay #define PCI_NRTR_DBG_N_ARB_MAX_CREDIT_MASK 0x3F 103*e65e175bSOded Gabbay 104*e65e175bSOded Gabbay /* PCI_NRTR_DBG_S_ARB_MAX */ 105*e65e175bSOded Gabbay #define PCI_NRTR_DBG_S_ARB_MAX_CREDIT_SHIFT 0 106*e65e175bSOded Gabbay #define PCI_NRTR_DBG_S_ARB_MAX_CREDIT_MASK 0x3F 107*e65e175bSOded Gabbay 108*e65e175bSOded Gabbay /* PCI_NRTR_DBG_L_ARB_MAX */ 109*e65e175bSOded Gabbay #define PCI_NRTR_DBG_L_ARB_MAX_CREDIT_SHIFT 0 110*e65e175bSOded Gabbay #define PCI_NRTR_DBG_L_ARB_MAX_CREDIT_MASK 0x3F 111*e65e175bSOded Gabbay 112*e65e175bSOded Gabbay /* PCI_NRTR_SPLIT_COEF */ 113*e65e175bSOded Gabbay #define PCI_NRTR_SPLIT_COEF_VAL_SHIFT 0 114*e65e175bSOded Gabbay #define PCI_NRTR_SPLIT_COEF_VAL_MASK 0xFFFF 115*e65e175bSOded Gabbay 116*e65e175bSOded Gabbay /* PCI_NRTR_SPLIT_CFG */ 117*e65e175bSOded Gabbay #define PCI_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_SHIFT 0 118*e65e175bSOded Gabbay #define PCI_NRTR_SPLIT_CFG_FORCE_WAK_ORDER_MASK 0x1 119*e65e175bSOded Gabbay #define PCI_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_SHIFT 1 120*e65e175bSOded Gabbay #define PCI_NRTR_SPLIT_CFG_FORCE_STRONG_ORDER_MASK 0x2 121*e65e175bSOded Gabbay #define PCI_NRTR_SPLIT_CFG_DEFAULT_MESH_SHIFT 2 122*e65e175bSOded Gabbay #define PCI_NRTR_SPLIT_CFG_DEFAULT_MESH_MASK 0xC 123*e65e175bSOded Gabbay #define PCI_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_SHIFT 4 124*e65e175bSOded Gabbay #define PCI_NRTR_SPLIT_CFG_RD_RATE_LIM_EN_MASK 0x10 125*e65e175bSOded Gabbay #define PCI_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_SHIFT 5 126*e65e175bSOded Gabbay #define PCI_NRTR_SPLIT_CFG_WR_RATE_LIM_EN_MASK 0x20 127*e65e175bSOded Gabbay #define PCI_NRTR_SPLIT_CFG_B2B_OPT_SHIFT 6 128*e65e175bSOded Gabbay #define PCI_NRTR_SPLIT_CFG_B2B_OPT_MASK 0x1C0 129*e65e175bSOded Gabbay 130*e65e175bSOded Gabbay /* PCI_NRTR_SPLIT_RD_SAT */ 131*e65e175bSOded Gabbay #define PCI_NRTR_SPLIT_RD_SAT_VAL_SHIFT 0 132*e65e175bSOded Gabbay #define PCI_NRTR_SPLIT_RD_SAT_VAL_MASK 0xFFFF 133*e65e175bSOded Gabbay 134*e65e175bSOded Gabbay /* PCI_NRTR_SPLIT_RD_RST_TOKEN */ 135*e65e175bSOded Gabbay #define PCI_NRTR_SPLIT_RD_RST_TOKEN_VAL_SHIFT 0 136*e65e175bSOded Gabbay #define PCI_NRTR_SPLIT_RD_RST_TOKEN_VAL_MASK 0xFFFF 137*e65e175bSOded Gabbay 138*e65e175bSOded Gabbay /* PCI_NRTR_SPLIT_RD_TIMEOUT */ 139*e65e175bSOded Gabbay #define PCI_NRTR_SPLIT_RD_TIMEOUT_VAL_SHIFT 0 140*e65e175bSOded Gabbay #define PCI_NRTR_SPLIT_RD_TIMEOUT_VAL_MASK 0xFFFFFFFF 141*e65e175bSOded Gabbay 142*e65e175bSOded Gabbay /* PCI_NRTR_SPLIT_WR_SAT */ 143*e65e175bSOded Gabbay #define PCI_NRTR_SPLIT_WR_SAT_VAL_SHIFT 0 144*e65e175bSOded Gabbay #define PCI_NRTR_SPLIT_WR_SAT_VAL_MASK 0xFFFF 145*e65e175bSOded Gabbay 146*e65e175bSOded Gabbay /* PCI_NRTR_WPLIT_WR_TST_TOLEN */ 147*e65e175bSOded Gabbay #define PCI_NRTR_WPLIT_WR_TST_TOLEN_VAL_SHIFT 0 148*e65e175bSOded Gabbay #define PCI_NRTR_WPLIT_WR_TST_TOLEN_VAL_MASK 0xFFFF 149*e65e175bSOded Gabbay 150*e65e175bSOded Gabbay /* PCI_NRTR_SPLIT_WR_TIMEOUT */ 151*e65e175bSOded Gabbay #define PCI_NRTR_SPLIT_WR_TIMEOUT_VAL_SHIFT 0 152*e65e175bSOded Gabbay #define PCI_NRTR_SPLIT_WR_TIMEOUT_VAL_MASK 0xFFFFFFFF 153*e65e175bSOded Gabbay 154*e65e175bSOded Gabbay /* PCI_NRTR_HBW_RANGE_HIT */ 155*e65e175bSOded Gabbay #define PCI_NRTR_HBW_RANGE_HIT_IND_SHIFT 0 156*e65e175bSOded Gabbay #define PCI_NRTR_HBW_RANGE_HIT_IND_MASK 0xFF 157*e65e175bSOded Gabbay 158*e65e175bSOded Gabbay /* PCI_NRTR_HBW_RANGE_MASK_L */ 159*e65e175bSOded Gabbay #define PCI_NRTR_HBW_RANGE_MASK_L_VAL_SHIFT 0 160*e65e175bSOded Gabbay #define PCI_NRTR_HBW_RANGE_MASK_L_VAL_MASK 0xFFFFFFFF 161*e65e175bSOded Gabbay 162*e65e175bSOded Gabbay /* PCI_NRTR_HBW_RANGE_MASK_H */ 163*e65e175bSOded Gabbay #define PCI_NRTR_HBW_RANGE_MASK_H_VAL_SHIFT 0 164*e65e175bSOded Gabbay #define PCI_NRTR_HBW_RANGE_MASK_H_VAL_MASK 0x3FFFF 165*e65e175bSOded Gabbay 166*e65e175bSOded Gabbay /* PCI_NRTR_HBW_RANGE_BASE_L */ 167*e65e175bSOded Gabbay #define PCI_NRTR_HBW_RANGE_BASE_L_VAL_SHIFT 0 168*e65e175bSOded Gabbay #define PCI_NRTR_HBW_RANGE_BASE_L_VAL_MASK 0xFFFFFFFF 169*e65e175bSOded Gabbay 170*e65e175bSOded Gabbay /* PCI_NRTR_HBW_RANGE_BASE_H */ 171*e65e175bSOded Gabbay #define PCI_NRTR_HBW_RANGE_BASE_H_VAL_SHIFT 0 172*e65e175bSOded Gabbay #define PCI_NRTR_HBW_RANGE_BASE_H_VAL_MASK 0x3FFFF 173*e65e175bSOded Gabbay 174*e65e175bSOded Gabbay /* PCI_NRTR_LBW_RANGE_HIT */ 175*e65e175bSOded Gabbay #define PCI_NRTR_LBW_RANGE_HIT_IND_SHIFT 0 176*e65e175bSOded Gabbay #define PCI_NRTR_LBW_RANGE_HIT_IND_MASK 0xFFFF 177*e65e175bSOded Gabbay 178*e65e175bSOded Gabbay /* PCI_NRTR_LBW_RANGE_MASK */ 179*e65e175bSOded Gabbay #define PCI_NRTR_LBW_RANGE_MASK_VAL_SHIFT 0 180*e65e175bSOded Gabbay #define PCI_NRTR_LBW_RANGE_MASK_VAL_MASK 0x3FFFFFF 181*e65e175bSOded Gabbay 182*e65e175bSOded Gabbay /* PCI_NRTR_LBW_RANGE_BASE */ 183*e65e175bSOded Gabbay #define PCI_NRTR_LBW_RANGE_BASE_VAL_SHIFT 0 184*e65e175bSOded Gabbay #define PCI_NRTR_LBW_RANGE_BASE_VAL_MASK 0x3FFFFFF 185*e65e175bSOded Gabbay 186*e65e175bSOded Gabbay /* PCI_NRTR_RGLTR */ 187*e65e175bSOded Gabbay #define PCI_NRTR_RGLTR_WR_EN_SHIFT 0 188*e65e175bSOded Gabbay #define PCI_NRTR_RGLTR_WR_EN_MASK 0x1 189*e65e175bSOded Gabbay #define PCI_NRTR_RGLTR_RD_EN_SHIFT 4 190*e65e175bSOded Gabbay #define PCI_NRTR_RGLTR_RD_EN_MASK 0x10 191*e65e175bSOded Gabbay 192*e65e175bSOded Gabbay /* PCI_NRTR_RGLTR_WR_RESULT */ 193*e65e175bSOded Gabbay #define PCI_NRTR_RGLTR_WR_RESULT_VAL_SHIFT 0 194*e65e175bSOded Gabbay #define PCI_NRTR_RGLTR_WR_RESULT_VAL_MASK 0xFF 195*e65e175bSOded Gabbay 196*e65e175bSOded Gabbay /* PCI_NRTR_RGLTR_RD_RESULT */ 197*e65e175bSOded Gabbay #define PCI_NRTR_RGLTR_RD_RESULT_VAL_SHIFT 0 198*e65e175bSOded Gabbay #define PCI_NRTR_RGLTR_RD_RESULT_VAL_MASK 0xFF 199*e65e175bSOded Gabbay 200*e65e175bSOded Gabbay /* PCI_NRTR_SCRAMB_EN */ 201*e65e175bSOded Gabbay #define PCI_NRTR_SCRAMB_EN_VAL_SHIFT 0 202*e65e175bSOded Gabbay #define PCI_NRTR_SCRAMB_EN_VAL_MASK 0x1 203*e65e175bSOded Gabbay 204*e65e175bSOded Gabbay /* PCI_NRTR_NON_LIN_SCRAMB */ 205*e65e175bSOded Gabbay #define PCI_NRTR_NON_LIN_SCRAMB_EN_SHIFT 0 206*e65e175bSOded Gabbay #define PCI_NRTR_NON_LIN_SCRAMB_EN_MASK 0x1 207*e65e175bSOded Gabbay 208*e65e175bSOded Gabbay #endif /* ASIC_REG_PCI_NRTR_MASKS_H_ */ 209