1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2016-2018 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay /************************************ 9*e65e175bSOded Gabbay ** This is an auto-generated file ** 10*e65e175bSOded Gabbay ** DO NOT EDIT BELOW ** 11*e65e175bSOded Gabbay ************************************/ 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay #ifndef ASIC_REG_TPC0_CFG_MASKS_H_ 14*e65e175bSOded Gabbay #define ASIC_REG_TPC0_CFG_MASKS_H_ 15*e65e175bSOded Gabbay 16*e65e175bSOded Gabbay /* 17*e65e175bSOded Gabbay ***************************************** 18*e65e175bSOded Gabbay * TPC0_CFG (Prototype: TPC) 19*e65e175bSOded Gabbay ***************************************** 20*e65e175bSOded Gabbay */ 21*e65e175bSOded Gabbay 22*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW */ 23*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 0 24*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 25*e65e175bSOded Gabbay 26*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH */ 27*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 0 28*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 29*e65e175bSOded Gabbay 30*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE */ 31*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_SHIFT 0 32*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF 33*e65e175bSOded Gabbay 34*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG */ 35*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 36*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 37*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 38*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 39*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT 16 40*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 41*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_SET_SHIFT 19 42*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_SET_MASK 0x80000 43*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 44*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 45*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_OP_SHIFT 21 46*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG_RMW_OP_MASK 0x600000 47*e65e175bSOded Gabbay 48*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE */ 49*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_V_SHIFT 0 50*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_V_MASK 0xFFFFFFFF 51*e65e175bSOded Gabbay 52*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE */ 53*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE_V_SHIFT 0 54*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 55*e65e175bSOded Gabbay 56*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE */ 57*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_V_SHIFT 0 58*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_V_MASK 0xFFFFFFFF 59*e65e175bSOded Gabbay 60*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE */ 61*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE_V_SHIFT 0 62*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 63*e65e175bSOded Gabbay 64*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE */ 65*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_V_SHIFT 0 66*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_V_MASK 0xFFFFFFFF 67*e65e175bSOded Gabbay 68*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE */ 69*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE_V_SHIFT 0 70*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 71*e65e175bSOded Gabbay 72*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE */ 73*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_V_SHIFT 0 74*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_V_MASK 0xFFFFFFFF 75*e65e175bSOded Gabbay 76*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE */ 77*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE_V_SHIFT 0 78*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 79*e65e175bSOded Gabbay 80*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE */ 81*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_V_SHIFT 0 82*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_V_MASK 0xFFFFFFFF 83*e65e175bSOded Gabbay 84*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE */ 85*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE_V_SHIFT 0 86*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 87*e65e175bSOded Gabbay 88*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW */ 89*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW_V_SHIFT 0 90*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 91*e65e175bSOded Gabbay 92*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH */ 93*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT 0 94*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 95*e65e175bSOded Gabbay 96*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE */ 97*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE_V_SHIFT 0 98*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_PADDING_VALUE_V_MASK 0xFFFFFFFF 99*e65e175bSOded Gabbay 100*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG */ 101*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 102*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 103*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 104*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 105*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT 16 106*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 107*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_SET_SHIFT 19 108*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_SET_MASK 0x80000 109*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 110*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 111*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_OP_SHIFT 21 112*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG_RMW_OP_MASK 0x600000 113*e65e175bSOded Gabbay 114*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE */ 115*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE_V_SHIFT 0 116*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_SIZE_V_MASK 0xFFFFFFFF 117*e65e175bSOded Gabbay 118*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE */ 119*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE_V_SHIFT 0 120*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 121*e65e175bSOded Gabbay 122*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE */ 123*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE_V_SHIFT 0 124*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_SIZE_V_MASK 0xFFFFFFFF 125*e65e175bSOded Gabbay 126*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE */ 127*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE_V_SHIFT 0 128*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 129*e65e175bSOded Gabbay 130*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE */ 131*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE_V_SHIFT 0 132*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_SIZE_V_MASK 0xFFFFFFFF 133*e65e175bSOded Gabbay 134*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE */ 135*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE_V_SHIFT 0 136*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 137*e65e175bSOded Gabbay 138*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE */ 139*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE_V_SHIFT 0 140*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_SIZE_V_MASK 0xFFFFFFFF 141*e65e175bSOded Gabbay 142*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE */ 143*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE_V_SHIFT 0 144*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 145*e65e175bSOded Gabbay 146*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE */ 147*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE_V_SHIFT 0 148*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_SIZE_V_MASK 0xFFFFFFFF 149*e65e175bSOded Gabbay 150*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE */ 151*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE_V_SHIFT 0 152*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 153*e65e175bSOded Gabbay 154*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW */ 155*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW_V_SHIFT 0 156*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 157*e65e175bSOded Gabbay 158*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH */ 159*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT 0 160*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 161*e65e175bSOded Gabbay 162*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE */ 163*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE_V_SHIFT 0 164*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_PADDING_VALUE_V_MASK 0xFFFFFFFF 165*e65e175bSOded Gabbay 166*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG */ 167*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 168*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 169*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 170*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 171*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT 16 172*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 173*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_SET_SHIFT 19 174*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_SET_MASK 0x80000 175*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 176*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 177*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_OP_SHIFT 21 178*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG_RMW_OP_MASK 0x600000 179*e65e175bSOded Gabbay 180*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE */ 181*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE_V_SHIFT 0 182*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_SIZE_V_MASK 0xFFFFFFFF 183*e65e175bSOded Gabbay 184*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE */ 185*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE_V_SHIFT 0 186*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 187*e65e175bSOded Gabbay 188*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE */ 189*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE_V_SHIFT 0 190*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_SIZE_V_MASK 0xFFFFFFFF 191*e65e175bSOded Gabbay 192*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE */ 193*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE_V_SHIFT 0 194*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 195*e65e175bSOded Gabbay 196*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE */ 197*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE_V_SHIFT 0 198*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_SIZE_V_MASK 0xFFFFFFFF 199*e65e175bSOded Gabbay 200*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE */ 201*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE_V_SHIFT 0 202*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 203*e65e175bSOded Gabbay 204*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE */ 205*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE_V_SHIFT 0 206*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_SIZE_V_MASK 0xFFFFFFFF 207*e65e175bSOded Gabbay 208*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE */ 209*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE_V_SHIFT 0 210*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 211*e65e175bSOded Gabbay 212*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE */ 213*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE_V_SHIFT 0 214*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_SIZE_V_MASK 0xFFFFFFFF 215*e65e175bSOded Gabbay 216*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE */ 217*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE_V_SHIFT 0 218*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 219*e65e175bSOded Gabbay 220*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW */ 221*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW_V_SHIFT 0 222*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 223*e65e175bSOded Gabbay 224*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH */ 225*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT 0 226*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 227*e65e175bSOded Gabbay 228*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE */ 229*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE_V_SHIFT 0 230*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_PADDING_VALUE_V_MASK 0xFFFFFFFF 231*e65e175bSOded Gabbay 232*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG */ 233*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 234*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 235*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 236*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 237*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT 16 238*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 239*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_SET_SHIFT 19 240*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_SET_MASK 0x80000 241*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 242*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 243*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_OP_SHIFT 21 244*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG_RMW_OP_MASK 0x600000 245*e65e175bSOded Gabbay 246*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE */ 247*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE_V_SHIFT 0 248*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_SIZE_V_MASK 0xFFFFFFFF 249*e65e175bSOded Gabbay 250*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE */ 251*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE_V_SHIFT 0 252*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 253*e65e175bSOded Gabbay 254*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE */ 255*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE_V_SHIFT 0 256*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_SIZE_V_MASK 0xFFFFFFFF 257*e65e175bSOded Gabbay 258*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE */ 259*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE_V_SHIFT 0 260*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 261*e65e175bSOded Gabbay 262*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE */ 263*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE_V_SHIFT 0 264*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_SIZE_V_MASK 0xFFFFFFFF 265*e65e175bSOded Gabbay 266*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE */ 267*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE_V_SHIFT 0 268*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 269*e65e175bSOded Gabbay 270*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE */ 271*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE_V_SHIFT 0 272*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_SIZE_V_MASK 0xFFFFFFFF 273*e65e175bSOded Gabbay 274*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE */ 275*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE_V_SHIFT 0 276*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 277*e65e175bSOded Gabbay 278*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE */ 279*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE_V_SHIFT 0 280*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_SIZE_V_MASK 0xFFFFFFFF 281*e65e175bSOded Gabbay 282*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE */ 283*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE_V_SHIFT 0 284*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 285*e65e175bSOded Gabbay 286*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW */ 287*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW_V_SHIFT 0 288*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 289*e65e175bSOded Gabbay 290*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH */ 291*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT 0 292*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 293*e65e175bSOded Gabbay 294*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE */ 295*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE_V_SHIFT 0 296*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_PADDING_VALUE_V_MASK 0xFFFFFFFF 297*e65e175bSOded Gabbay 298*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG */ 299*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 300*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 301*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 302*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 303*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT 16 304*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 305*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_SET_SHIFT 19 306*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_SET_MASK 0x80000 307*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 308*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 309*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_OP_SHIFT 21 310*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG_RMW_OP_MASK 0x600000 311*e65e175bSOded Gabbay 312*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE */ 313*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE_V_SHIFT 0 314*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_SIZE_V_MASK 0xFFFFFFFF 315*e65e175bSOded Gabbay 316*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE */ 317*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE_V_SHIFT 0 318*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 319*e65e175bSOded Gabbay 320*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE */ 321*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE_V_SHIFT 0 322*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_SIZE_V_MASK 0xFFFFFFFF 323*e65e175bSOded Gabbay 324*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE */ 325*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE_V_SHIFT 0 326*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 327*e65e175bSOded Gabbay 328*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE */ 329*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE_V_SHIFT 0 330*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_SIZE_V_MASK 0xFFFFFFFF 331*e65e175bSOded Gabbay 332*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE */ 333*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE_V_SHIFT 0 334*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 335*e65e175bSOded Gabbay 336*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE */ 337*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE_V_SHIFT 0 338*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_SIZE_V_MASK 0xFFFFFFFF 339*e65e175bSOded Gabbay 340*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE */ 341*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE_V_SHIFT 0 342*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 343*e65e175bSOded Gabbay 344*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE */ 345*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE_V_SHIFT 0 346*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_SIZE_V_MASK 0xFFFFFFFF 347*e65e175bSOded Gabbay 348*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE */ 349*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE_V_SHIFT 0 350*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 351*e65e175bSOded Gabbay 352*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW */ 353*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW_V_SHIFT 0 354*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 355*e65e175bSOded Gabbay 356*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH */ 357*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT 0 358*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 359*e65e175bSOded Gabbay 360*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE */ 361*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE_V_SHIFT 0 362*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_PADDING_VALUE_V_MASK 0xFFFFFFFF 363*e65e175bSOded Gabbay 364*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG */ 365*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 366*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 367*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 368*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 369*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT 16 370*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 371*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_SET_SHIFT 19 372*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_SET_MASK 0x80000 373*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 374*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 375*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_OP_SHIFT 21 376*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG_RMW_OP_MASK 0x600000 377*e65e175bSOded Gabbay 378*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE */ 379*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE_V_SHIFT 0 380*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_SIZE_V_MASK 0xFFFFFFFF 381*e65e175bSOded Gabbay 382*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE */ 383*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE_V_SHIFT 0 384*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 385*e65e175bSOded Gabbay 386*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE */ 387*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE_V_SHIFT 0 388*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_SIZE_V_MASK 0xFFFFFFFF 389*e65e175bSOded Gabbay 390*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE */ 391*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE_V_SHIFT 0 392*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 393*e65e175bSOded Gabbay 394*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE */ 395*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE_V_SHIFT 0 396*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_SIZE_V_MASK 0xFFFFFFFF 397*e65e175bSOded Gabbay 398*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE */ 399*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE_V_SHIFT 0 400*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 401*e65e175bSOded Gabbay 402*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE */ 403*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE_V_SHIFT 0 404*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_SIZE_V_MASK 0xFFFFFFFF 405*e65e175bSOded Gabbay 406*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE */ 407*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE_V_SHIFT 0 408*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 409*e65e175bSOded Gabbay 410*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE */ 411*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE_V_SHIFT 0 412*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_SIZE_V_MASK 0xFFFFFFFF 413*e65e175bSOded Gabbay 414*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE */ 415*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE_V_SHIFT 0 416*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 417*e65e175bSOded Gabbay 418*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW */ 419*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW_V_SHIFT 0 420*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 421*e65e175bSOded Gabbay 422*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH */ 423*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT 0 424*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 425*e65e175bSOded Gabbay 426*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE */ 427*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE_V_SHIFT 0 428*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_PADDING_VALUE_V_MASK 0xFFFFFFFF 429*e65e175bSOded Gabbay 430*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG */ 431*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 432*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 433*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 434*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 435*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT 16 436*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 437*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_SET_SHIFT 19 438*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_SET_MASK 0x80000 439*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 440*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 441*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_OP_SHIFT 21 442*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG_RMW_OP_MASK 0x600000 443*e65e175bSOded Gabbay 444*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE */ 445*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE_V_SHIFT 0 446*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_SIZE_V_MASK 0xFFFFFFFF 447*e65e175bSOded Gabbay 448*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE */ 449*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE_V_SHIFT 0 450*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 451*e65e175bSOded Gabbay 452*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE */ 453*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE_V_SHIFT 0 454*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_SIZE_V_MASK 0xFFFFFFFF 455*e65e175bSOded Gabbay 456*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE */ 457*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE_V_SHIFT 0 458*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 459*e65e175bSOded Gabbay 460*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE */ 461*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE_V_SHIFT 0 462*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_SIZE_V_MASK 0xFFFFFFFF 463*e65e175bSOded Gabbay 464*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE */ 465*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE_V_SHIFT 0 466*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 467*e65e175bSOded Gabbay 468*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE */ 469*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE_V_SHIFT 0 470*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_SIZE_V_MASK 0xFFFFFFFF 471*e65e175bSOded Gabbay 472*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE */ 473*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE_V_SHIFT 0 474*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 475*e65e175bSOded Gabbay 476*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE */ 477*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE_V_SHIFT 0 478*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_SIZE_V_MASK 0xFFFFFFFF 479*e65e175bSOded Gabbay 480*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE */ 481*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE_V_SHIFT 0 482*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 483*e65e175bSOded Gabbay 484*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW */ 485*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW_V_SHIFT 0 486*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 487*e65e175bSOded Gabbay 488*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH */ 489*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT 0 490*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 491*e65e175bSOded Gabbay 492*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE */ 493*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE_V_SHIFT 0 494*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_PADDING_VALUE_V_MASK 0xFFFFFFFF 495*e65e175bSOded Gabbay 496*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG */ 497*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 498*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 499*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 500*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 501*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT 16 502*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 503*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_SET_SHIFT 19 504*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_SET_MASK 0x80000 505*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 506*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 507*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_OP_SHIFT 21 508*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG_RMW_OP_MASK 0x600000 509*e65e175bSOded Gabbay 510*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE */ 511*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE_V_SHIFT 0 512*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_SIZE_V_MASK 0xFFFFFFFF 513*e65e175bSOded Gabbay 514*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE */ 515*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE_V_SHIFT 0 516*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 517*e65e175bSOded Gabbay 518*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE */ 519*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE_V_SHIFT 0 520*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_SIZE_V_MASK 0xFFFFFFFF 521*e65e175bSOded Gabbay 522*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE */ 523*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE_V_SHIFT 0 524*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 525*e65e175bSOded Gabbay 526*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE */ 527*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE_V_SHIFT 0 528*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_SIZE_V_MASK 0xFFFFFFFF 529*e65e175bSOded Gabbay 530*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE */ 531*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE_V_SHIFT 0 532*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 533*e65e175bSOded Gabbay 534*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE */ 535*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE_V_SHIFT 0 536*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_SIZE_V_MASK 0xFFFFFFFF 537*e65e175bSOded Gabbay 538*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE */ 539*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE_V_SHIFT 0 540*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 541*e65e175bSOded Gabbay 542*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE */ 543*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE_V_SHIFT 0 544*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_SIZE_V_MASK 0xFFFFFFFF 545*e65e175bSOded Gabbay 546*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE */ 547*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE_V_SHIFT 0 548*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 549*e65e175bSOded Gabbay 550*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW */ 551*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW_V_SHIFT 0 552*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 553*e65e175bSOded Gabbay 554*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH */ 555*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH_V_SHIFT 0 556*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 557*e65e175bSOded Gabbay 558*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE */ 559*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE_V_SHIFT 0 560*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_PADDING_VALUE_V_MASK 0xFFFFFFFF 561*e65e175bSOded Gabbay 562*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG */ 563*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 564*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 565*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 566*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 567*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_LAST_DIM_SHIFT 16 568*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 569*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_SET_SHIFT 19 570*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_SET_MASK 0x80000 571*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 572*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 573*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_OP_SHIFT 21 574*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG_RMW_OP_MASK 0x600000 575*e65e175bSOded Gabbay 576*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE */ 577*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE_V_SHIFT 0 578*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_SIZE_V_MASK 0xFFFFFFFF 579*e65e175bSOded Gabbay 580*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE */ 581*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE_V_SHIFT 0 582*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 583*e65e175bSOded Gabbay 584*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE */ 585*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE_V_SHIFT 0 586*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_SIZE_V_MASK 0xFFFFFFFF 587*e65e175bSOded Gabbay 588*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE */ 589*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE_V_SHIFT 0 590*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 591*e65e175bSOded Gabbay 592*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE */ 593*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE_V_SHIFT 0 594*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_SIZE_V_MASK 0xFFFFFFFF 595*e65e175bSOded Gabbay 596*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE */ 597*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE_V_SHIFT 0 598*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 599*e65e175bSOded Gabbay 600*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE */ 601*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE_V_SHIFT 0 602*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_SIZE_V_MASK 0xFFFFFFFF 603*e65e175bSOded Gabbay 604*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE */ 605*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE_V_SHIFT 0 606*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 607*e65e175bSOded Gabbay 608*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE */ 609*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE_V_SHIFT 0 610*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_SIZE_V_MASK 0xFFFFFFFF 611*e65e175bSOded Gabbay 612*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE */ 613*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE_V_SHIFT 0 614*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 615*e65e175bSOded Gabbay 616*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW */ 617*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW_V_SHIFT 0 618*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 619*e65e175bSOded Gabbay 620*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH */ 621*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH_V_SHIFT 0 622*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 623*e65e175bSOded Gabbay 624*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE */ 625*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE_V_SHIFT 0 626*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_PADDING_VALUE_V_MASK 0xFFFFFFFF 627*e65e175bSOded Gabbay 628*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG */ 629*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 630*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 631*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 632*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 633*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_LAST_DIM_SHIFT 16 634*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 635*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_SET_SHIFT 19 636*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_SET_MASK 0x80000 637*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 638*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 639*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_OP_SHIFT 21 640*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG_RMW_OP_MASK 0x600000 641*e65e175bSOded Gabbay 642*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE */ 643*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE_V_SHIFT 0 644*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_SIZE_V_MASK 0xFFFFFFFF 645*e65e175bSOded Gabbay 646*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE */ 647*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE_V_SHIFT 0 648*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 649*e65e175bSOded Gabbay 650*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE */ 651*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE_V_SHIFT 0 652*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_SIZE_V_MASK 0xFFFFFFFF 653*e65e175bSOded Gabbay 654*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE */ 655*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE_V_SHIFT 0 656*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 657*e65e175bSOded Gabbay 658*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE */ 659*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE_V_SHIFT 0 660*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_SIZE_V_MASK 0xFFFFFFFF 661*e65e175bSOded Gabbay 662*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE */ 663*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE_V_SHIFT 0 664*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 665*e65e175bSOded Gabbay 666*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE */ 667*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE_V_SHIFT 0 668*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_SIZE_V_MASK 0xFFFFFFFF 669*e65e175bSOded Gabbay 670*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE */ 671*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE_V_SHIFT 0 672*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 673*e65e175bSOded Gabbay 674*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE */ 675*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE_V_SHIFT 0 676*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_SIZE_V_MASK 0xFFFFFFFF 677*e65e175bSOded Gabbay 678*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE */ 679*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE_V_SHIFT 0 680*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 681*e65e175bSOded Gabbay 682*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW */ 683*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW_V_SHIFT 0 684*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 685*e65e175bSOded Gabbay 686*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH */ 687*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH_V_SHIFT 0 688*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 689*e65e175bSOded Gabbay 690*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE */ 691*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE_V_SHIFT 0 692*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_PADDING_VALUE_V_MASK 0xFFFFFFFF 693*e65e175bSOded Gabbay 694*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG */ 695*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 696*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 697*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 698*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 699*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_LAST_DIM_SHIFT 16 700*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 701*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_SET_SHIFT 19 702*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_SET_MASK 0x80000 703*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 704*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 705*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_OP_SHIFT 21 706*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG_RMW_OP_MASK 0x600000 707*e65e175bSOded Gabbay 708*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE */ 709*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE_V_SHIFT 0 710*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_SIZE_V_MASK 0xFFFFFFFF 711*e65e175bSOded Gabbay 712*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE */ 713*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE_V_SHIFT 0 714*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 715*e65e175bSOded Gabbay 716*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE */ 717*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE_V_SHIFT 0 718*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_SIZE_V_MASK 0xFFFFFFFF 719*e65e175bSOded Gabbay 720*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE */ 721*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE_V_SHIFT 0 722*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 723*e65e175bSOded Gabbay 724*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE */ 725*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE_V_SHIFT 0 726*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_SIZE_V_MASK 0xFFFFFFFF 727*e65e175bSOded Gabbay 728*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE */ 729*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE_V_SHIFT 0 730*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 731*e65e175bSOded Gabbay 732*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE */ 733*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE_V_SHIFT 0 734*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_SIZE_V_MASK 0xFFFFFFFF 735*e65e175bSOded Gabbay 736*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE */ 737*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE_V_SHIFT 0 738*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 739*e65e175bSOded Gabbay 740*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE */ 741*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE_V_SHIFT 0 742*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_SIZE_V_MASK 0xFFFFFFFF 743*e65e175bSOded Gabbay 744*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE */ 745*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE_V_SHIFT 0 746*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 747*e65e175bSOded Gabbay 748*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW */ 749*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW_V_SHIFT 0 750*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 751*e65e175bSOded Gabbay 752*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH */ 753*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH_V_SHIFT 0 754*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 755*e65e175bSOded Gabbay 756*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE */ 757*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE_V_SHIFT 0 758*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_PADDING_VALUE_V_MASK 0xFFFFFFFF 759*e65e175bSOded Gabbay 760*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG */ 761*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 762*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 763*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 764*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 765*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_LAST_DIM_SHIFT 16 766*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 767*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_SET_SHIFT 19 768*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_SET_MASK 0x80000 769*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 770*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 771*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_OP_SHIFT 21 772*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG_RMW_OP_MASK 0x600000 773*e65e175bSOded Gabbay 774*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE */ 775*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE_V_SHIFT 0 776*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_SIZE_V_MASK 0xFFFFFFFF 777*e65e175bSOded Gabbay 778*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE */ 779*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE_V_SHIFT 0 780*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 781*e65e175bSOded Gabbay 782*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE */ 783*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE_V_SHIFT 0 784*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_SIZE_V_MASK 0xFFFFFFFF 785*e65e175bSOded Gabbay 786*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE */ 787*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE_V_SHIFT 0 788*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 789*e65e175bSOded Gabbay 790*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE */ 791*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE_V_SHIFT 0 792*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_SIZE_V_MASK 0xFFFFFFFF 793*e65e175bSOded Gabbay 794*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE */ 795*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE_V_SHIFT 0 796*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 797*e65e175bSOded Gabbay 798*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE */ 799*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE_V_SHIFT 0 800*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_SIZE_V_MASK 0xFFFFFFFF 801*e65e175bSOded Gabbay 802*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE */ 803*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE_V_SHIFT 0 804*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 805*e65e175bSOded Gabbay 806*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE */ 807*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE_V_SHIFT 0 808*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_SIZE_V_MASK 0xFFFFFFFF 809*e65e175bSOded Gabbay 810*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE */ 811*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE_V_SHIFT 0 812*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 813*e65e175bSOded Gabbay 814*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW */ 815*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW_V_SHIFT 0 816*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 817*e65e175bSOded Gabbay 818*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH */ 819*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH_V_SHIFT 0 820*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 821*e65e175bSOded Gabbay 822*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE */ 823*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE_V_SHIFT 0 824*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_PADDING_VALUE_V_MASK 0xFFFFFFFF 825*e65e175bSOded Gabbay 826*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG */ 827*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 828*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 829*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 830*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 831*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_LAST_DIM_SHIFT 16 832*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 833*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_SET_SHIFT 19 834*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_SET_MASK 0x80000 835*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 836*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 837*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_OP_SHIFT 21 838*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG_RMW_OP_MASK 0x600000 839*e65e175bSOded Gabbay 840*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE */ 841*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE_V_SHIFT 0 842*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_SIZE_V_MASK 0xFFFFFFFF 843*e65e175bSOded Gabbay 844*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE */ 845*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE_V_SHIFT 0 846*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 847*e65e175bSOded Gabbay 848*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE */ 849*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE_V_SHIFT 0 850*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_SIZE_V_MASK 0xFFFFFFFF 851*e65e175bSOded Gabbay 852*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE */ 853*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE_V_SHIFT 0 854*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 855*e65e175bSOded Gabbay 856*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE */ 857*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE_V_SHIFT 0 858*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_SIZE_V_MASK 0xFFFFFFFF 859*e65e175bSOded Gabbay 860*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE */ 861*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE_V_SHIFT 0 862*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 863*e65e175bSOded Gabbay 864*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE */ 865*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE_V_SHIFT 0 866*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_SIZE_V_MASK 0xFFFFFFFF 867*e65e175bSOded Gabbay 868*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE */ 869*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE_V_SHIFT 0 870*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 871*e65e175bSOded Gabbay 872*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE */ 873*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE_V_SHIFT 0 874*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_SIZE_V_MASK 0xFFFFFFFF 875*e65e175bSOded Gabbay 876*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE */ 877*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE_V_SHIFT 0 878*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 879*e65e175bSOded Gabbay 880*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW */ 881*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW_V_SHIFT 0 882*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 883*e65e175bSOded Gabbay 884*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH */ 885*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH_V_SHIFT 0 886*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 887*e65e175bSOded Gabbay 888*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE */ 889*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE_V_SHIFT 0 890*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_PADDING_VALUE_V_MASK 0xFFFFFFFF 891*e65e175bSOded Gabbay 892*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG */ 893*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 894*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 895*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 896*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 897*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_LAST_DIM_SHIFT 16 898*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 899*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_SET_SHIFT 19 900*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_SET_MASK 0x80000 901*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 902*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 903*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_OP_SHIFT 21 904*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG_RMW_OP_MASK 0x600000 905*e65e175bSOded Gabbay 906*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE */ 907*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE_V_SHIFT 0 908*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_SIZE_V_MASK 0xFFFFFFFF 909*e65e175bSOded Gabbay 910*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE */ 911*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE_V_SHIFT 0 912*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 913*e65e175bSOded Gabbay 914*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE */ 915*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE_V_SHIFT 0 916*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_SIZE_V_MASK 0xFFFFFFFF 917*e65e175bSOded Gabbay 918*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE */ 919*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE_V_SHIFT 0 920*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 921*e65e175bSOded Gabbay 922*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE */ 923*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE_V_SHIFT 0 924*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_SIZE_V_MASK 0xFFFFFFFF 925*e65e175bSOded Gabbay 926*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE */ 927*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE_V_SHIFT 0 928*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 929*e65e175bSOded Gabbay 930*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE */ 931*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE_V_SHIFT 0 932*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_SIZE_V_MASK 0xFFFFFFFF 933*e65e175bSOded Gabbay 934*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE */ 935*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE_V_SHIFT 0 936*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 937*e65e175bSOded Gabbay 938*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE */ 939*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE_V_SHIFT 0 940*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_SIZE_V_MASK 0xFFFFFFFF 941*e65e175bSOded Gabbay 942*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE */ 943*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE_V_SHIFT 0 944*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 945*e65e175bSOded Gabbay 946*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW */ 947*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW_V_SHIFT 0 948*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 949*e65e175bSOded Gabbay 950*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH */ 951*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH_V_SHIFT 0 952*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 953*e65e175bSOded Gabbay 954*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE */ 955*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE_V_SHIFT 0 956*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_PADDING_VALUE_V_MASK 0xFFFFFFFF 957*e65e175bSOded Gabbay 958*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG */ 959*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 960*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 961*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 962*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 963*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_LAST_DIM_SHIFT 16 964*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 965*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_SET_SHIFT 19 966*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_SET_MASK 0x80000 967*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 968*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 969*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_OP_SHIFT 21 970*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG_RMW_OP_MASK 0x600000 971*e65e175bSOded Gabbay 972*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE */ 973*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE_V_SHIFT 0 974*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_SIZE_V_MASK 0xFFFFFFFF 975*e65e175bSOded Gabbay 976*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE */ 977*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE_V_SHIFT 0 978*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 979*e65e175bSOded Gabbay 980*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE */ 981*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE_V_SHIFT 0 982*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_SIZE_V_MASK 0xFFFFFFFF 983*e65e175bSOded Gabbay 984*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE */ 985*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE_V_SHIFT 0 986*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 987*e65e175bSOded Gabbay 988*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE */ 989*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE_V_SHIFT 0 990*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_SIZE_V_MASK 0xFFFFFFFF 991*e65e175bSOded Gabbay 992*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE */ 993*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE_V_SHIFT 0 994*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 995*e65e175bSOded Gabbay 996*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE */ 997*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE_V_SHIFT 0 998*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_SIZE_V_MASK 0xFFFFFFFF 999*e65e175bSOded Gabbay 1000*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE */ 1001*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE_V_SHIFT 0 1002*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 1003*e65e175bSOded Gabbay 1004*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE */ 1005*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE_V_SHIFT 0 1006*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_SIZE_V_MASK 0xFFFFFFFF 1007*e65e175bSOded Gabbay 1008*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE */ 1009*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE_V_SHIFT 0 1010*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 1011*e65e175bSOded Gabbay 1012*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW */ 1013*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW_V_SHIFT 0 1014*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 1015*e65e175bSOded Gabbay 1016*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH */ 1017*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH_V_SHIFT 0 1018*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 1019*e65e175bSOded Gabbay 1020*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE */ 1021*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE_V_SHIFT 0 1022*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_PADDING_VALUE_V_MASK 0xFFFFFFFF 1023*e65e175bSOded Gabbay 1024*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG */ 1025*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 1026*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 1027*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 1028*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 1029*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_LAST_DIM_SHIFT 16 1030*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 1031*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_SET_SHIFT 19 1032*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_SET_MASK 0x80000 1033*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 1034*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 1035*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_OP_SHIFT 21 1036*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG_RMW_OP_MASK 0x600000 1037*e65e175bSOded Gabbay 1038*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE */ 1039*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE_V_SHIFT 0 1040*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_SIZE_V_MASK 0xFFFFFFFF 1041*e65e175bSOded Gabbay 1042*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE */ 1043*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE_V_SHIFT 0 1044*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 1045*e65e175bSOded Gabbay 1046*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE */ 1047*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE_V_SHIFT 0 1048*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_SIZE_V_MASK 0xFFFFFFFF 1049*e65e175bSOded Gabbay 1050*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE */ 1051*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE_V_SHIFT 0 1052*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 1053*e65e175bSOded Gabbay 1054*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE */ 1055*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE_V_SHIFT 0 1056*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_SIZE_V_MASK 0xFFFFFFFF 1057*e65e175bSOded Gabbay 1058*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE */ 1059*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE_V_SHIFT 0 1060*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 1061*e65e175bSOded Gabbay 1062*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE */ 1063*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE_V_SHIFT 0 1064*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_SIZE_V_MASK 0xFFFFFFFF 1065*e65e175bSOded Gabbay 1066*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE */ 1067*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE_V_SHIFT 0 1068*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 1069*e65e175bSOded Gabbay 1070*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE */ 1071*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE_V_SHIFT 0 1072*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_SIZE_V_MASK 0xFFFFFFFF 1073*e65e175bSOded Gabbay 1074*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE */ 1075*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE_V_SHIFT 0 1076*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 1077*e65e175bSOded Gabbay 1078*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE */ 1079*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT 0 1080*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK 0xFFFF 1081*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_RSV_SHIFT 16 1082*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_RSV_MASK 0x1FFF0000 1083*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT 29 1084*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK 0xE0000000 1085*e65e175bSOded Gabbay 1086*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_SYNC_OBJECT_ADDR */ 1087*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_SYNC_OBJECT_ADDR_V_SHIFT 0 1088*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_SYNC_OBJECT_ADDR_V_MASK 0xFFFFFFFF 1089*e65e175bSOded Gabbay 1090*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW */ 1091*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW_V_SHIFT 0 1092*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW_V_MASK 0xFFFFFFFF 1093*e65e175bSOded Gabbay 1094*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH */ 1095*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT 0 1096*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF 1097*e65e175bSOded Gabbay 1098*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TID_BASE_DIM_0 */ 1099*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TID_BASE_DIM_0_V_SHIFT 0 1100*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TID_BASE_DIM_0_V_MASK 0xFFFFFFFF 1101*e65e175bSOded Gabbay 1102*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TID_SIZE_DIM_0 */ 1103*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TID_SIZE_DIM_0_V_SHIFT 0 1104*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TID_SIZE_DIM_0_V_MASK 0xFFFFFFFF 1105*e65e175bSOded Gabbay 1106*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TID_BASE_DIM_1 */ 1107*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TID_BASE_DIM_1_V_SHIFT 0 1108*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TID_BASE_DIM_1_V_MASK 0xFFFFFFFF 1109*e65e175bSOded Gabbay 1110*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TID_SIZE_DIM_1 */ 1111*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TID_SIZE_DIM_1_V_SHIFT 0 1112*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TID_SIZE_DIM_1_V_MASK 0xFFFFFFFF 1113*e65e175bSOded Gabbay 1114*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TID_BASE_DIM_2 */ 1115*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TID_BASE_DIM_2_V_SHIFT 0 1116*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TID_BASE_DIM_2_V_MASK 0xFFFFFFFF 1117*e65e175bSOded Gabbay 1118*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TID_SIZE_DIM_2 */ 1119*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TID_SIZE_DIM_2_V_SHIFT 0 1120*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TID_SIZE_DIM_2_V_MASK 0xFFFFFFFF 1121*e65e175bSOded Gabbay 1122*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TID_BASE_DIM_3 */ 1123*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TID_BASE_DIM_3_V_SHIFT 0 1124*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TID_BASE_DIM_3_V_MASK 0xFFFFFFFF 1125*e65e175bSOded Gabbay 1126*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TID_SIZE_DIM_3 */ 1127*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TID_SIZE_DIM_3_V_SHIFT 0 1128*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TID_SIZE_DIM_3_V_MASK 0xFFFFFFFF 1129*e65e175bSOded Gabbay 1130*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TID_BASE_DIM_4 */ 1131*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TID_BASE_DIM_4_V_SHIFT 0 1132*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TID_BASE_DIM_4_V_MASK 0xFFFFFFFF 1133*e65e175bSOded Gabbay 1134*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_TID_SIZE_DIM_4 */ 1135*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TID_SIZE_DIM_4_V_SHIFT 0 1136*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_TID_SIZE_DIM_4_V_MASK 0xFFFFFFFF 1137*e65e175bSOded Gabbay 1138*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_KERNEL_CONFIG */ 1139*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_KERNEL_CONFIG_SMALL_VLM_SHIFT 0 1140*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_KERNEL_CONFIG_SMALL_VLM_MASK 0x1 1141*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT 1 1142*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_KERNEL_CONFIG_ASO_EVICT_L0_MASK 0x2 1143*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT 2 1144*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_KERNEL_CONFIG_NUM_VALID_SRFS_MASK 0xFC 1145*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_SHIFT 8 1146*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_MASK 0xFF00 1147*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_SHIFT 16 1148*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_MASK 0xFF0000 1149*e65e175bSOded Gabbay 1150*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_KERNEL_ID */ 1151*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_KERNEL_ID_V_SHIFT 0 1152*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_KERNEL_ID_V_MASK 0xFFFF 1153*e65e175bSOded Gabbay 1154*e65e175bSOded Gabbay /* TPC0_CFG_KERNEL_SRF */ 1155*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_SRF_V_SHIFT 0 1156*e65e175bSOded Gabbay #define TPC0_CFG_KERNEL_SRF_V_MASK 0xFFFFFFFF 1157*e65e175bSOded Gabbay 1158*e65e175bSOded Gabbay /* TPC0_CFG_ROUND_CSR */ 1159*e65e175bSOded Gabbay #define TPC0_CFG_ROUND_CSR_MODE_SHIFT 0 1160*e65e175bSOded Gabbay #define TPC0_CFG_ROUND_CSR_MODE_MASK 0x7 1161*e65e175bSOded Gabbay 1162*e65e175bSOded Gabbay /* TPC0_CFG_PROT */ 1163*e65e175bSOded Gabbay #define TPC0_CFG_PROT_AWPROT_SHIFT 0 1164*e65e175bSOded Gabbay #define TPC0_CFG_PROT_AWPROT_MASK 0x7 1165*e65e175bSOded Gabbay #define TPC0_CFG_PROT_ARPROT_SHIFT 3 1166*e65e175bSOded Gabbay #define TPC0_CFG_PROT_ARPROT_MASK 0x38 1167*e65e175bSOded Gabbay 1168*e65e175bSOded Gabbay /* TPC0_CFG_SEMAPHORE */ 1169*e65e175bSOded Gabbay #define TPC0_CFG_SEMAPHORE_V_SHIFT 0 1170*e65e175bSOded Gabbay #define TPC0_CFG_SEMAPHORE_V_MASK 0xFFFFFFFF 1171*e65e175bSOded Gabbay 1172*e65e175bSOded Gabbay /* TPC0_CFG_VFLAGS */ 1173*e65e175bSOded Gabbay #define TPC0_CFG_VFLAGS_V_SHIFT 0 1174*e65e175bSOded Gabbay #define TPC0_CFG_VFLAGS_V_MASK 0xF 1175*e65e175bSOded Gabbay 1176*e65e175bSOded Gabbay /* TPC0_CFG_SFLAGS */ 1177*e65e175bSOded Gabbay #define TPC0_CFG_SFLAGS_V_SHIFT 0 1178*e65e175bSOded Gabbay #define TPC0_CFG_SFLAGS_V_MASK 0xF 1179*e65e175bSOded Gabbay 1180*e65e175bSOded Gabbay /* TPC0_CFG_LFSR_POLYNOM */ 1181*e65e175bSOded Gabbay #define TPC0_CFG_LFSR_POLYNOM_V_SHIFT 0 1182*e65e175bSOded Gabbay #define TPC0_CFG_LFSR_POLYNOM_V_MASK 0xFFFFFFFF 1183*e65e175bSOded Gabbay 1184*e65e175bSOded Gabbay /* TPC0_CFG_STATUS */ 1185*e65e175bSOded Gabbay #define TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_SHIFT 1 1186*e65e175bSOded Gabbay #define TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK 0x2 1187*e65e175bSOded Gabbay #define TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_SHIFT 2 1188*e65e175bSOded Gabbay #define TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK 0x4 1189*e65e175bSOded Gabbay #define TPC0_CFG_STATUS_IQ_EMPTY_SHIFT 3 1190*e65e175bSOded Gabbay #define TPC0_CFG_STATUS_IQ_EMPTY_MASK 0x8 1191*e65e175bSOded Gabbay #define TPC0_CFG_STATUS_SB_EMPTY_SHIFT 5 1192*e65e175bSOded Gabbay #define TPC0_CFG_STATUS_SB_EMPTY_MASK 0x20 1193*e65e175bSOded Gabbay #define TPC0_CFG_STATUS_QM_IDLE_SHIFT 6 1194*e65e175bSOded Gabbay #define TPC0_CFG_STATUS_QM_IDLE_MASK 0x40 1195*e65e175bSOded Gabbay #define TPC0_CFG_STATUS_QM_RDY_SHIFT 7 1196*e65e175bSOded Gabbay #define TPC0_CFG_STATUS_QM_RDY_MASK 0x80 1197*e65e175bSOded Gabbay 1198*e65e175bSOded Gabbay /* TPC0_CFG_CFG_BASE_ADDRESS_HIGH */ 1199*e65e175bSOded Gabbay #define TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_SHIFT 0 1200*e65e175bSOded Gabbay #define TPC0_CFG_CFG_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF 1201*e65e175bSOded Gabbay 1202*e65e175bSOded Gabbay /* TPC0_CFG_CFG_SUBTRACT_VALUE */ 1203*e65e175bSOded Gabbay #define TPC0_CFG_CFG_SUBTRACT_VALUE_V_SHIFT 0 1204*e65e175bSOded Gabbay #define TPC0_CFG_CFG_SUBTRACT_VALUE_V_MASK 0xFFFFFFFF 1205*e65e175bSOded Gabbay 1206*e65e175bSOded Gabbay /* TPC0_CFG_SM_BASE_ADDRESS_HIGH */ 1207*e65e175bSOded Gabbay #define TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_SHIFT 0 1208*e65e175bSOded Gabbay #define TPC0_CFG_SM_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF 1209*e65e175bSOded Gabbay 1210*e65e175bSOded Gabbay /* TPC0_CFG_TPC_CMD */ 1211*e65e175bSOded Gabbay #define TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_SHIFT 0 1212*e65e175bSOded Gabbay #define TPC0_CFG_TPC_CMD_ICACHE_INVALIDATE_MASK 0x1 1213*e65e175bSOded Gabbay #define TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_SHIFT 1 1214*e65e175bSOded Gabbay #define TPC0_CFG_TPC_CMD_DCACHE_INVALIDATE_MASK 0x2 1215*e65e175bSOded Gabbay #define TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_SHIFT 2 1216*e65e175bSOded Gabbay #define TPC0_CFG_TPC_CMD_LCACHE_INVALIDATE_MASK 0x4 1217*e65e175bSOded Gabbay #define TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_SHIFT 3 1218*e65e175bSOded Gabbay #define TPC0_CFG_TPC_CMD_TCACHE_INVALIDATE_MASK 0x8 1219*e65e175bSOded Gabbay #define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_SHIFT 4 1220*e65e175bSOded Gabbay #define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_64KB_MASK 0x10 1221*e65e175bSOded Gabbay #define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_SHIFT 5 1222*e65e175bSOded Gabbay #define TPC0_CFG_TPC_CMD_ICACHE_PREFETCH_32KB_MASK 0x20 1223*e65e175bSOded Gabbay #define TPC0_CFG_TPC_CMD_QMAN_STOP_SHIFT 6 1224*e65e175bSOded Gabbay #define TPC0_CFG_TPC_CMD_QMAN_STOP_MASK 0x40 1225*e65e175bSOded Gabbay 1226*e65e175bSOded Gabbay /* TPC0_CFG_TPC_EXECUTE */ 1227*e65e175bSOded Gabbay #define TPC0_CFG_TPC_EXECUTE_V_SHIFT 0 1228*e65e175bSOded Gabbay #define TPC0_CFG_TPC_EXECUTE_V_MASK 0x1 1229*e65e175bSOded Gabbay 1230*e65e175bSOded Gabbay /* TPC0_CFG_TPC_STALL */ 1231*e65e175bSOded Gabbay #define TPC0_CFG_TPC_STALL_V_SHIFT 0 1232*e65e175bSOded Gabbay #define TPC0_CFG_TPC_STALL_V_MASK 0x1 1233*e65e175bSOded Gabbay 1234*e65e175bSOded Gabbay /* TPC0_CFG_ICACHE_BASE_ADDERESS_LOW */ 1235*e65e175bSOded Gabbay #define TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_SHIFT 0 1236*e65e175bSOded Gabbay #define TPC0_CFG_ICACHE_BASE_ADDERESS_LOW_V_MASK 0xFFFFFFFF 1237*e65e175bSOded Gabbay 1238*e65e175bSOded Gabbay /* TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH */ 1239*e65e175bSOded Gabbay #define TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_SHIFT 0 1240*e65e175bSOded Gabbay #define TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH_V_MASK 0xFFFFFFFF 1241*e65e175bSOded Gabbay 1242*e65e175bSOded Gabbay /* TPC0_CFG_RD_RATE_LIMIT */ 1243*e65e175bSOded Gabbay #define TPC0_CFG_RD_RATE_LIMIT_ENABLE_SHIFT 0 1244*e65e175bSOded Gabbay #define TPC0_CFG_RD_RATE_LIMIT_ENABLE_MASK 0x1 1245*e65e175bSOded Gabbay #define TPC0_CFG_RD_RATE_LIMIT_SATURATION_SHIFT 1 1246*e65e175bSOded Gabbay #define TPC0_CFG_RD_RATE_LIMIT_SATURATION_MASK 0x1FE 1247*e65e175bSOded Gabbay #define TPC0_CFG_RD_RATE_LIMIT_TIMEOUT_SHIFT 9 1248*e65e175bSOded Gabbay #define TPC0_CFG_RD_RATE_LIMIT_TIMEOUT_MASK 0x1FE00 1249*e65e175bSOded Gabbay 1250*e65e175bSOded Gabbay /* TPC0_CFG_WR_RATE_LIMIT */ 1251*e65e175bSOded Gabbay #define TPC0_CFG_WR_RATE_LIMIT_ENABLE_SHIFT 0 1252*e65e175bSOded Gabbay #define TPC0_CFG_WR_RATE_LIMIT_ENABLE_MASK 0x1 1253*e65e175bSOded Gabbay #define TPC0_CFG_WR_RATE_LIMIT_SATURATION_SHIFT 1 1254*e65e175bSOded Gabbay #define TPC0_CFG_WR_RATE_LIMIT_SATURATION_MASK 0x1FE 1255*e65e175bSOded Gabbay #define TPC0_CFG_WR_RATE_LIMIT_TIMEOUT_SHIFT 9 1256*e65e175bSOded Gabbay #define TPC0_CFG_WR_RATE_LIMIT_TIMEOUT_MASK 0x1FE00 1257*e65e175bSOded Gabbay 1258*e65e175bSOded Gabbay /* TPC0_CFG_MSS_CONFIG */ 1259*e65e175bSOded Gabbay #define TPC0_CFG_MSS_CONFIG_AWCACHE_SHIFT 0 1260*e65e175bSOded Gabbay #define TPC0_CFG_MSS_CONFIG_AWCACHE_MASK 0xF 1261*e65e175bSOded Gabbay #define TPC0_CFG_MSS_CONFIG_ARCACHE_SHIFT 4 1262*e65e175bSOded Gabbay #define TPC0_CFG_MSS_CONFIG_ARCACHE_MASK 0xF0 1263*e65e175bSOded Gabbay #define TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_SHIFT 8 1264*e65e175bSOded Gabbay #define TPC0_CFG_MSS_CONFIG_ICACHE_FETCH_LINE_NUM_MASK 0x300 1265*e65e175bSOded Gabbay #define TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_SHIFT 10 1266*e65e175bSOded Gabbay #define TPC0_CFG_MSS_CONFIG_EXPOSED_PIPE_DIS_MASK 0x400 1267*e65e175bSOded Gabbay #define TPC0_CFG_MSS_CONFIG_DCACHE_PREFETCH_DIS_SHIFT 11 1268*e65e175bSOded Gabbay #define TPC0_CFG_MSS_CONFIG_DCACHE_PREFETCH_DIS_MASK 0x800 1269*e65e175bSOded Gabbay 1270*e65e175bSOded Gabbay /* TPC0_CFG_TPC_INTR_CAUSE */ 1271*e65e175bSOded Gabbay #define TPC0_CFG_TPC_INTR_CAUSE_CAUSE_SHIFT 0 1272*e65e175bSOded Gabbay #define TPC0_CFG_TPC_INTR_CAUSE_CAUSE_MASK 0xFFFFF 1273*e65e175bSOded Gabbay 1274*e65e175bSOded Gabbay /* TPC0_CFG_TPC_INTR_MASK */ 1275*e65e175bSOded Gabbay #define TPC0_CFG_TPC_INTR_MASK_MASK_SHIFT 0 1276*e65e175bSOded Gabbay #define TPC0_CFG_TPC_INTR_MASK_MASK_MASK 0xFFFFF 1277*e65e175bSOded Gabbay 1278*e65e175bSOded Gabbay /* TPC0_CFG_WQ_CREDITS */ 1279*e65e175bSOded Gabbay #define TPC0_CFG_WQ_CREDITS_ST_G_SHIFT 0 1280*e65e175bSOded Gabbay #define TPC0_CFG_WQ_CREDITS_ST_G_MASK 0xF 1281*e65e175bSOded Gabbay #define TPC0_CFG_WQ_CREDITS_KERNEL_FIFO_SHIFT 4 1282*e65e175bSOded Gabbay #define TPC0_CFG_WQ_CREDITS_KERNEL_FIFO_MASK 0x70 1283*e65e175bSOded Gabbay 1284*e65e175bSOded Gabbay /* TPC0_CFG_ARUSER_LO */ 1285*e65e175bSOded Gabbay #define TPC0_CFG_ARUSER_LO_V_SHIFT 0 1286*e65e175bSOded Gabbay #define TPC0_CFG_ARUSER_LO_V_MASK 0x7FF 1287*e65e175bSOded Gabbay 1288*e65e175bSOded Gabbay /* TPC0_CFG_ARUSER_HI */ 1289*e65e175bSOded Gabbay #define TPC0_CFG_ARUSER_HI_V_SHIFT 11 1290*e65e175bSOded Gabbay #define TPC0_CFG_ARUSER_HI_V_MASK 0x1800 1291*e65e175bSOded Gabbay #define TPC0_CFG_ARUSER_HI_RSRV_SHIFT 13 1292*e65e175bSOded Gabbay #define TPC0_CFG_ARUSER_HI_RSRV_MASK 0xFFFFE000 1293*e65e175bSOded Gabbay 1294*e65e175bSOded Gabbay /* TPC0_CFG_AWUSER_LO */ 1295*e65e175bSOded Gabbay #define TPC0_CFG_AWUSER_LO_V_SHIFT 0 1296*e65e175bSOded Gabbay #define TPC0_CFG_AWUSER_LO_V_MASK 0x7FF 1297*e65e175bSOded Gabbay 1298*e65e175bSOded Gabbay /* TPC0_CFG_AWUSER_HI */ 1299*e65e175bSOded Gabbay #define TPC0_CFG_AWUSER_HI_V_SHIFT 11 1300*e65e175bSOded Gabbay #define TPC0_CFG_AWUSER_HI_V_MASK 0x1800 1301*e65e175bSOded Gabbay #define TPC0_CFG_AWUSER_HI_RSRV_SHIFT 13 1302*e65e175bSOded Gabbay #define TPC0_CFG_AWUSER_HI_RSRV_MASK 0xFFFFE000 1303*e65e175bSOded Gabbay 1304*e65e175bSOded Gabbay /* TPC0_CFG_OPCODE_EXEC */ 1305*e65e175bSOded Gabbay #define TPC0_CFG_OPCODE_EXEC_SPU_OP_SHIFT 0 1306*e65e175bSOded Gabbay #define TPC0_CFG_OPCODE_EXEC_SPU_OP_MASK 0x7F 1307*e65e175bSOded Gabbay #define TPC0_CFG_OPCODE_EXEC_SPU_EN_SHIFT 7 1308*e65e175bSOded Gabbay #define TPC0_CFG_OPCODE_EXEC_SPU_EN_MASK 0x80 1309*e65e175bSOded Gabbay #define TPC0_CFG_OPCODE_EXEC_VPU_OP_SHIFT 8 1310*e65e175bSOded Gabbay #define TPC0_CFG_OPCODE_EXEC_VPU_OP_MASK 0x7F00 1311*e65e175bSOded Gabbay #define TPC0_CFG_OPCODE_EXEC_VPU_EN_SHIFT 15 1312*e65e175bSOded Gabbay #define TPC0_CFG_OPCODE_EXEC_VPU_EN_MASK 0x8000 1313*e65e175bSOded Gabbay #define TPC0_CFG_OPCODE_EXEC_LD_OP_SHIFT 16 1314*e65e175bSOded Gabbay #define TPC0_CFG_OPCODE_EXEC_LD_OP_MASK 0x7F0000 1315*e65e175bSOded Gabbay #define TPC0_CFG_OPCODE_EXEC_LD_EN_SHIFT 23 1316*e65e175bSOded Gabbay #define TPC0_CFG_OPCODE_EXEC_LD_EN_MASK 0x800000 1317*e65e175bSOded Gabbay #define TPC0_CFG_OPCODE_EXEC_ST_OP_SHIFT 24 1318*e65e175bSOded Gabbay #define TPC0_CFG_OPCODE_EXEC_ST_OP_MASK 0x7F000000 1319*e65e175bSOded Gabbay #define TPC0_CFG_OPCODE_EXEC_ST_EN_SHIFT 31 1320*e65e175bSOded Gabbay #define TPC0_CFG_OPCODE_EXEC_ST_EN_MASK 0x80000000 1321*e65e175bSOded Gabbay 1322*e65e175bSOded Gabbay /* TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO */ 1323*e65e175bSOded Gabbay #define TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO_V_SHIFT 0 1324*e65e175bSOded Gabbay #define TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO_V_MASK 0xFFFFFFFF 1325*e65e175bSOded Gabbay 1326*e65e175bSOded Gabbay /* TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI */ 1327*e65e175bSOded Gabbay #define TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI_V_SHIFT 0 1328*e65e175bSOded Gabbay #define TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI_V_MASK 0xFFFFFFFF 1329*e65e175bSOded Gabbay 1330*e65e175bSOded Gabbay /* TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO */ 1331*e65e175bSOded Gabbay #define TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO_V_SHIFT 0 1332*e65e175bSOded Gabbay #define TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO_V_MASK 0xFFFFFFFF 1333*e65e175bSOded Gabbay 1334*e65e175bSOded Gabbay /* TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI */ 1335*e65e175bSOded Gabbay #define TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI_V_SHIFT 0 1336*e65e175bSOded Gabbay #define TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI_V_MASK 0xFFFFFFFF 1337*e65e175bSOded Gabbay 1338*e65e175bSOded Gabbay /* TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO */ 1339*e65e175bSOded Gabbay #define TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO_V_SHIFT 0 1340*e65e175bSOded Gabbay #define TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO_V_MASK 0xFFFFFFFF 1341*e65e175bSOded Gabbay 1342*e65e175bSOded Gabbay /* TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI */ 1343*e65e175bSOded Gabbay #define TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI_V_SHIFT 0 1344*e65e175bSOded Gabbay #define TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI_V_MASK 0xFFFFFFFF 1345*e65e175bSOded Gabbay 1346*e65e175bSOded Gabbay /* TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO */ 1347*e65e175bSOded Gabbay #define TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO_V_SHIFT 0 1348*e65e175bSOded Gabbay #define TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO_V_MASK 0xFFFFFFFF 1349*e65e175bSOded Gabbay 1350*e65e175bSOded Gabbay /* TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI */ 1351*e65e175bSOded Gabbay #define TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI_V_SHIFT 0 1352*e65e175bSOded Gabbay #define TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI_V_MASK 0xFFFFFFFF 1353*e65e175bSOded Gabbay 1354*e65e175bSOded Gabbay /* TPC0_CFG_TSB_CFG_MAX_SIZE */ 1355*e65e175bSOded Gabbay #define TPC0_CFG_TSB_CFG_MAX_SIZE_DATA_SHIFT 0 1356*e65e175bSOded Gabbay #define TPC0_CFG_TSB_CFG_MAX_SIZE_DATA_MASK 0xFFFF 1357*e65e175bSOded Gabbay #define TPC0_CFG_TSB_CFG_MAX_SIZE_MD_SHIFT 16 1358*e65e175bSOded Gabbay #define TPC0_CFG_TSB_CFG_MAX_SIZE_MD_MASK 0xFFFF0000 1359*e65e175bSOded Gabbay 1360*e65e175bSOded Gabbay /* TPC0_CFG_TSB_CFG */ 1361*e65e175bSOded Gabbay #define TPC0_CFG_TSB_CFG_FORCE_MISS_SHIFT 0 1362*e65e175bSOded Gabbay #define TPC0_CFG_TSB_CFG_FORCE_MISS_MASK 0x1 1363*e65e175bSOded Gabbay #define TPC0_CFG_TSB_CFG_MAX_OS_SHIFT 1 1364*e65e175bSOded Gabbay #define TPC0_CFG_TSB_CFG_MAX_OS_MASK 0x1FFFE 1365*e65e175bSOded Gabbay 1366*e65e175bSOded Gabbay /* TPC0_CFG_DBGMEM_ADD */ 1367*e65e175bSOded Gabbay #define TPC0_CFG_DBGMEM_ADD_V_SHIFT 0 1368*e65e175bSOded Gabbay #define TPC0_CFG_DBGMEM_ADD_V_MASK 0xFFFFFFFF 1369*e65e175bSOded Gabbay 1370*e65e175bSOded Gabbay /* TPC0_CFG_DBGMEM_DATA_WR */ 1371*e65e175bSOded Gabbay #define TPC0_CFG_DBGMEM_DATA_WR_V_SHIFT 0 1372*e65e175bSOded Gabbay #define TPC0_CFG_DBGMEM_DATA_WR_V_MASK 0xFFFFFFFF 1373*e65e175bSOded Gabbay 1374*e65e175bSOded Gabbay /* TPC0_CFG_DBGMEM_DATA_RD */ 1375*e65e175bSOded Gabbay #define TPC0_CFG_DBGMEM_DATA_RD_V_SHIFT 0 1376*e65e175bSOded Gabbay #define TPC0_CFG_DBGMEM_DATA_RD_V_MASK 0xFFFFFFFF 1377*e65e175bSOded Gabbay 1378*e65e175bSOded Gabbay /* TPC0_CFG_DBGMEM_CTRL */ 1379*e65e175bSOded Gabbay #define TPC0_CFG_DBGMEM_CTRL_WR_NRD_SHIFT 0 1380*e65e175bSOded Gabbay #define TPC0_CFG_DBGMEM_CTRL_WR_NRD_MASK 0x1 1381*e65e175bSOded Gabbay 1382*e65e175bSOded Gabbay /* TPC0_CFG_DBGMEM_RC */ 1383*e65e175bSOded Gabbay #define TPC0_CFG_DBGMEM_RC_VALID_SHIFT 0 1384*e65e175bSOded Gabbay #define TPC0_CFG_DBGMEM_RC_VALID_MASK 0x1 1385*e65e175bSOded Gabbay 1386*e65e175bSOded Gabbay /* TPC0_CFG_TSB_INFLIGHT_CNTR */ 1387*e65e175bSOded Gabbay #define TPC0_CFG_TSB_INFLIGHT_CNTR_V_SHIFT 0 1388*e65e175bSOded Gabbay #define TPC0_CFG_TSB_INFLIGHT_CNTR_V_MASK 0xFFFFFFFF 1389*e65e175bSOded Gabbay 1390*e65e175bSOded Gabbay /* TPC0_CFG_WQ_INFLIGHT_CNTR */ 1391*e65e175bSOded Gabbay #define TPC0_CFG_WQ_INFLIGHT_CNTR_HBW_SHIFT 0 1392*e65e175bSOded Gabbay #define TPC0_CFG_WQ_INFLIGHT_CNTR_HBW_MASK 0xFFFF 1393*e65e175bSOded Gabbay #define TPC0_CFG_WQ_INFLIGHT_CNTR_LBW_SHIFT 16 1394*e65e175bSOded Gabbay #define TPC0_CFG_WQ_INFLIGHT_CNTR_LBW_MASK 0xF0000 1395*e65e175bSOded Gabbay 1396*e65e175bSOded Gabbay /* TPC0_CFG_WQ_LBW_TOTAL_CNTR */ 1397*e65e175bSOded Gabbay #define TPC0_CFG_WQ_LBW_TOTAL_CNTR_V_SHIFT 0 1398*e65e175bSOded Gabbay #define TPC0_CFG_WQ_LBW_TOTAL_CNTR_V_MASK 0xFFFFFFFF 1399*e65e175bSOded Gabbay 1400*e65e175bSOded Gabbay /* TPC0_CFG_WQ_HBW_TOTAL_CNTR */ 1401*e65e175bSOded Gabbay #define TPC0_CFG_WQ_HBW_TOTAL_CNTR_V_SHIFT 0 1402*e65e175bSOded Gabbay #define TPC0_CFG_WQ_HBW_TOTAL_CNTR_V_MASK 0xFFFFFFFF 1403*e65e175bSOded Gabbay 1404*e65e175bSOded Gabbay /* TPC0_CFG_IRQ_OCCOUPY_CNTR */ 1405*e65e175bSOded Gabbay #define TPC0_CFG_IRQ_OCCOUPY_CNTR_V_SHIFT 0 1406*e65e175bSOded Gabbay #define TPC0_CFG_IRQ_OCCOUPY_CNTR_V_MASK 0xFFFFFFFF 1407*e65e175bSOded Gabbay 1408*e65e175bSOded Gabbay /* TPC0_CFG_FUNC_MBIST_CNTRL */ 1409*e65e175bSOded Gabbay #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_SHIFT 0 1410*e65e175bSOded Gabbay #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_START_MASK 0x1 1411*e65e175bSOded Gabbay #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_SHIFT 1 1412*e65e175bSOded Gabbay #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_DONE_MASK 0x2 1413*e65e175bSOded Gabbay #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_SHIFT 2 1414*e65e175bSOded Gabbay #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_ACTIVE_MASK 0x4 1415*e65e175bSOded Gabbay #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_FAILED_SHIFT 16 1416*e65e175bSOded Gabbay #define TPC0_CFG_FUNC_MBIST_CNTRL_MBIST_FAILED_MASK 0x3FF0000 1417*e65e175bSOded Gabbay 1418*e65e175bSOded Gabbay /* TPC0_CFG_FUNC_MBIST_PAT */ 1419*e65e175bSOded Gabbay #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_EVEN_SHIFT 0 1420*e65e175bSOded Gabbay #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_EVEN_MASK 0x3 1421*e65e175bSOded Gabbay #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_ODD_SHIFT 2 1422*e65e175bSOded Gabbay #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN0_ODD_MASK 0xC 1423*e65e175bSOded Gabbay #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_EVEN_SHIFT 4 1424*e65e175bSOded Gabbay #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_EVEN_MASK 0x30 1425*e65e175bSOded Gabbay #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_ODD_SHIFT 6 1426*e65e175bSOded Gabbay #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN1_ODD_MASK 0xC0 1427*e65e175bSOded Gabbay #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_EVEN_SHIFT 8 1428*e65e175bSOded Gabbay #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_EVEN_MASK 0x300 1429*e65e175bSOded Gabbay #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_ODD_SHIFT 10 1430*e65e175bSOded Gabbay #define TPC0_CFG_FUNC_MBIST_PAT_MBIST_PATTERN2_ODD_MASK 0xC00 1431*e65e175bSOded Gabbay 1432*e65e175bSOded Gabbay /* TPC0_CFG_FUNC_MBIST_MEM */ 1433*e65e175bSOded Gabbay #define TPC0_CFG_FUNC_MBIST_MEM_MAX_ADDR_SHIFT 0 1434*e65e175bSOded Gabbay #define TPC0_CFG_FUNC_MBIST_MEM_MAX_ADDR_MASK 0x7FF 1435*e65e175bSOded Gabbay #define TPC0_CFG_FUNC_MBIST_MEM_PATTERN_EN_SHIFT 12 1436*e65e175bSOded Gabbay #define TPC0_CFG_FUNC_MBIST_MEM_PATTERN_EN_MASK 0x7000 1437*e65e175bSOded Gabbay #define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_ADDR_SHIFT 16 1438*e65e175bSOded Gabbay #define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_ADDR_MASK 0x7FF0000 1439*e65e175bSOded Gabbay #define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_PATTERN_SHIFT 28 1440*e65e175bSOded Gabbay #define TPC0_CFG_FUNC_MBIST_MEM_LAST_FAILED_PATTERN_MASK 0x70000000 1441*e65e175bSOded Gabbay 1442*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW */ 1443*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW_V_SHIFT 0 1444*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 1445*e65e175bSOded Gabbay 1446*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH */ 1447*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH_V_SHIFT 0 1448*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 1449*e65e175bSOded Gabbay 1450*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_0_PADDING_VALUE */ 1451*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_PADDING_VALUE_V_SHIFT 0 1452*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_PADDING_VALUE_V_MASK 0xFFFFFFFF 1453*e65e175bSOded Gabbay 1454*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG */ 1455*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 1456*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 1457*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 1458*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 1459*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_SHIFT 16 1460*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 1461*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_SET_SHIFT 19 1462*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_SET_MASK 0x80000 1463*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 1464*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 1465*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_OP_SHIFT 21 1466*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG_RMW_OP_MASK 0x600000 1467*e65e175bSOded Gabbay 1468*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE */ 1469*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_V_SHIFT 0 1470*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_V_MASK 0xFFFFFFFF 1471*e65e175bSOded Gabbay 1472*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE */ 1473*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE_V_SHIFT 0 1474*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 1475*e65e175bSOded Gabbay 1476*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE */ 1477*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_V_SHIFT 0 1478*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_V_MASK 0xFFFFFFFF 1479*e65e175bSOded Gabbay 1480*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE */ 1481*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE_V_SHIFT 0 1482*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 1483*e65e175bSOded Gabbay 1484*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE */ 1485*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_V_SHIFT 0 1486*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_V_MASK 0xFFFFFFFF 1487*e65e175bSOded Gabbay 1488*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE */ 1489*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE_V_SHIFT 0 1490*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 1491*e65e175bSOded Gabbay 1492*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE */ 1493*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_V_SHIFT 0 1494*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_V_MASK 0xFFFFFFFF 1495*e65e175bSOded Gabbay 1496*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE */ 1497*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE_V_SHIFT 0 1498*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 1499*e65e175bSOded Gabbay 1500*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE */ 1501*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_V_SHIFT 0 1502*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_V_MASK 0xFFFFFFFF 1503*e65e175bSOded Gabbay 1504*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE */ 1505*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE_V_SHIFT 0 1506*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 1507*e65e175bSOded Gabbay 1508*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW */ 1509*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW_V_SHIFT 0 1510*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 1511*e65e175bSOded Gabbay 1512*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH */ 1513*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH_V_SHIFT 0 1514*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 1515*e65e175bSOded Gabbay 1516*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_1_PADDING_VALUE */ 1517*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_PADDING_VALUE_V_SHIFT 0 1518*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_PADDING_VALUE_V_MASK 0xFFFFFFFF 1519*e65e175bSOded Gabbay 1520*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG */ 1521*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 1522*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 1523*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 1524*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 1525*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_SHIFT 16 1526*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 1527*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_SET_SHIFT 19 1528*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_SET_MASK 0x80000 1529*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 1530*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 1531*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_OP_SHIFT 21 1532*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_TENSOR_CONFIG_RMW_OP_MASK 0x600000 1533*e65e175bSOded Gabbay 1534*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE */ 1535*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE_V_SHIFT 0 1536*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_DIM_0_SIZE_V_MASK 0xFFFFFFFF 1537*e65e175bSOded Gabbay 1538*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE */ 1539*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE_V_SHIFT 0 1540*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 1541*e65e175bSOded Gabbay 1542*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE */ 1543*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE_V_SHIFT 0 1544*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_DIM_1_SIZE_V_MASK 0xFFFFFFFF 1545*e65e175bSOded Gabbay 1546*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE */ 1547*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE_V_SHIFT 0 1548*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 1549*e65e175bSOded Gabbay 1550*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE */ 1551*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE_V_SHIFT 0 1552*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_DIM_2_SIZE_V_MASK 0xFFFFFFFF 1553*e65e175bSOded Gabbay 1554*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE */ 1555*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE_V_SHIFT 0 1556*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 1557*e65e175bSOded Gabbay 1558*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE */ 1559*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE_V_SHIFT 0 1560*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_DIM_3_SIZE_V_MASK 0xFFFFFFFF 1561*e65e175bSOded Gabbay 1562*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE */ 1563*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE_V_SHIFT 0 1564*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 1565*e65e175bSOded Gabbay 1566*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE */ 1567*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE_V_SHIFT 0 1568*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_DIM_4_SIZE_V_MASK 0xFFFFFFFF 1569*e65e175bSOded Gabbay 1570*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE */ 1571*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE_V_SHIFT 0 1572*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_1_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 1573*e65e175bSOded Gabbay 1574*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW */ 1575*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW_V_SHIFT 0 1576*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 1577*e65e175bSOded Gabbay 1578*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH */ 1579*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH_V_SHIFT 0 1580*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 1581*e65e175bSOded Gabbay 1582*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_2_PADDING_VALUE */ 1583*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_PADDING_VALUE_V_SHIFT 0 1584*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_PADDING_VALUE_V_MASK 0xFFFFFFFF 1585*e65e175bSOded Gabbay 1586*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG */ 1587*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 1588*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 1589*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 1590*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 1591*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_SHIFT 16 1592*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 1593*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_SET_SHIFT 19 1594*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_SET_MASK 0x80000 1595*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 1596*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 1597*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_OP_SHIFT 21 1598*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_TENSOR_CONFIG_RMW_OP_MASK 0x600000 1599*e65e175bSOded Gabbay 1600*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE */ 1601*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE_V_SHIFT 0 1602*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_DIM_0_SIZE_V_MASK 0xFFFFFFFF 1603*e65e175bSOded Gabbay 1604*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE */ 1605*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE_V_SHIFT 0 1606*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 1607*e65e175bSOded Gabbay 1608*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE */ 1609*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE_V_SHIFT 0 1610*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_DIM_1_SIZE_V_MASK 0xFFFFFFFF 1611*e65e175bSOded Gabbay 1612*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE */ 1613*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE_V_SHIFT 0 1614*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 1615*e65e175bSOded Gabbay 1616*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE */ 1617*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE_V_SHIFT 0 1618*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_DIM_2_SIZE_V_MASK 0xFFFFFFFF 1619*e65e175bSOded Gabbay 1620*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE */ 1621*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE_V_SHIFT 0 1622*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 1623*e65e175bSOded Gabbay 1624*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE */ 1625*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE_V_SHIFT 0 1626*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_DIM_3_SIZE_V_MASK 0xFFFFFFFF 1627*e65e175bSOded Gabbay 1628*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE */ 1629*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE_V_SHIFT 0 1630*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 1631*e65e175bSOded Gabbay 1632*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE */ 1633*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE_V_SHIFT 0 1634*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_DIM_4_SIZE_V_MASK 0xFFFFFFFF 1635*e65e175bSOded Gabbay 1636*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE */ 1637*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE_V_SHIFT 0 1638*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_2_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 1639*e65e175bSOded Gabbay 1640*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW */ 1641*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW_V_SHIFT 0 1642*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 1643*e65e175bSOded Gabbay 1644*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH */ 1645*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH_V_SHIFT 0 1646*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 1647*e65e175bSOded Gabbay 1648*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_3_PADDING_VALUE */ 1649*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_PADDING_VALUE_V_SHIFT 0 1650*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_PADDING_VALUE_V_MASK 0xFFFFFFFF 1651*e65e175bSOded Gabbay 1652*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG */ 1653*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 1654*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 1655*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 1656*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 1657*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_SHIFT 16 1658*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 1659*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_SET_SHIFT 19 1660*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_SET_MASK 0x80000 1661*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 1662*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 1663*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_OP_SHIFT 21 1664*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_TENSOR_CONFIG_RMW_OP_MASK 0x600000 1665*e65e175bSOded Gabbay 1666*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE */ 1667*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE_V_SHIFT 0 1668*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_DIM_0_SIZE_V_MASK 0xFFFFFFFF 1669*e65e175bSOded Gabbay 1670*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE */ 1671*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE_V_SHIFT 0 1672*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 1673*e65e175bSOded Gabbay 1674*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE */ 1675*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE_V_SHIFT 0 1676*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_DIM_1_SIZE_V_MASK 0xFFFFFFFF 1677*e65e175bSOded Gabbay 1678*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE */ 1679*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE_V_SHIFT 0 1680*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 1681*e65e175bSOded Gabbay 1682*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE */ 1683*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE_V_SHIFT 0 1684*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_DIM_2_SIZE_V_MASK 0xFFFFFFFF 1685*e65e175bSOded Gabbay 1686*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE */ 1687*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE_V_SHIFT 0 1688*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 1689*e65e175bSOded Gabbay 1690*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE */ 1691*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE_V_SHIFT 0 1692*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_DIM_3_SIZE_V_MASK 0xFFFFFFFF 1693*e65e175bSOded Gabbay 1694*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE */ 1695*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE_V_SHIFT 0 1696*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 1697*e65e175bSOded Gabbay 1698*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE */ 1699*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE_V_SHIFT 0 1700*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_DIM_4_SIZE_V_MASK 0xFFFFFFFF 1701*e65e175bSOded Gabbay 1702*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE */ 1703*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE_V_SHIFT 0 1704*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_3_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 1705*e65e175bSOded Gabbay 1706*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW */ 1707*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW_V_SHIFT 0 1708*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 1709*e65e175bSOded Gabbay 1710*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH */ 1711*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH_V_SHIFT 0 1712*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 1713*e65e175bSOded Gabbay 1714*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_4_PADDING_VALUE */ 1715*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_PADDING_VALUE_V_SHIFT 0 1716*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_PADDING_VALUE_V_MASK 0xFFFFFFFF 1717*e65e175bSOded Gabbay 1718*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG */ 1719*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 1720*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 1721*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 1722*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 1723*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_SHIFT 16 1724*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 1725*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_SET_SHIFT 19 1726*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_SET_MASK 0x80000 1727*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 1728*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 1729*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_OP_SHIFT 21 1730*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_TENSOR_CONFIG_RMW_OP_MASK 0x600000 1731*e65e175bSOded Gabbay 1732*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE */ 1733*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE_V_SHIFT 0 1734*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_DIM_0_SIZE_V_MASK 0xFFFFFFFF 1735*e65e175bSOded Gabbay 1736*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE */ 1737*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE_V_SHIFT 0 1738*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 1739*e65e175bSOded Gabbay 1740*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE */ 1741*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE_V_SHIFT 0 1742*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_DIM_1_SIZE_V_MASK 0xFFFFFFFF 1743*e65e175bSOded Gabbay 1744*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE */ 1745*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE_V_SHIFT 0 1746*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 1747*e65e175bSOded Gabbay 1748*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE */ 1749*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE_V_SHIFT 0 1750*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_DIM_2_SIZE_V_MASK 0xFFFFFFFF 1751*e65e175bSOded Gabbay 1752*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE */ 1753*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE_V_SHIFT 0 1754*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 1755*e65e175bSOded Gabbay 1756*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE */ 1757*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE_V_SHIFT 0 1758*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_DIM_3_SIZE_V_MASK 0xFFFFFFFF 1759*e65e175bSOded Gabbay 1760*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE */ 1761*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE_V_SHIFT 0 1762*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 1763*e65e175bSOded Gabbay 1764*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE */ 1765*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE_V_SHIFT 0 1766*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_DIM_4_SIZE_V_MASK 0xFFFFFFFF 1767*e65e175bSOded Gabbay 1768*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE */ 1769*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE_V_SHIFT 0 1770*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_4_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 1771*e65e175bSOded Gabbay 1772*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW */ 1773*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW_V_SHIFT 0 1774*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 1775*e65e175bSOded Gabbay 1776*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH */ 1777*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH_V_SHIFT 0 1778*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 1779*e65e175bSOded Gabbay 1780*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_5_PADDING_VALUE */ 1781*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_PADDING_VALUE_V_SHIFT 0 1782*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_PADDING_VALUE_V_MASK 0xFFFFFFFF 1783*e65e175bSOded Gabbay 1784*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG */ 1785*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 1786*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 1787*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 1788*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 1789*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_SHIFT 16 1790*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 1791*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_SET_SHIFT 19 1792*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_SET_MASK 0x80000 1793*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 1794*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 1795*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_OP_SHIFT 21 1796*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_TENSOR_CONFIG_RMW_OP_MASK 0x600000 1797*e65e175bSOded Gabbay 1798*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE */ 1799*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE_V_SHIFT 0 1800*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_DIM_0_SIZE_V_MASK 0xFFFFFFFF 1801*e65e175bSOded Gabbay 1802*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE */ 1803*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE_V_SHIFT 0 1804*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 1805*e65e175bSOded Gabbay 1806*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE */ 1807*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE_V_SHIFT 0 1808*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_DIM_1_SIZE_V_MASK 0xFFFFFFFF 1809*e65e175bSOded Gabbay 1810*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE */ 1811*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE_V_SHIFT 0 1812*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 1813*e65e175bSOded Gabbay 1814*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE */ 1815*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE_V_SHIFT 0 1816*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_DIM_2_SIZE_V_MASK 0xFFFFFFFF 1817*e65e175bSOded Gabbay 1818*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE */ 1819*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE_V_SHIFT 0 1820*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 1821*e65e175bSOded Gabbay 1822*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE */ 1823*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE_V_SHIFT 0 1824*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_DIM_3_SIZE_V_MASK 0xFFFFFFFF 1825*e65e175bSOded Gabbay 1826*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE */ 1827*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE_V_SHIFT 0 1828*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 1829*e65e175bSOded Gabbay 1830*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE */ 1831*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE_V_SHIFT 0 1832*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_DIM_4_SIZE_V_MASK 0xFFFFFFFF 1833*e65e175bSOded Gabbay 1834*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE */ 1835*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE_V_SHIFT 0 1836*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_5_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 1837*e65e175bSOded Gabbay 1838*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW */ 1839*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW_V_SHIFT 0 1840*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 1841*e65e175bSOded Gabbay 1842*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH */ 1843*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH_V_SHIFT 0 1844*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 1845*e65e175bSOded Gabbay 1846*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_6_PADDING_VALUE */ 1847*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_PADDING_VALUE_V_SHIFT 0 1848*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_PADDING_VALUE_V_MASK 0xFFFFFFFF 1849*e65e175bSOded Gabbay 1850*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG */ 1851*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 1852*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 1853*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 1854*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 1855*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_SHIFT 16 1856*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 1857*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_SET_SHIFT 19 1858*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_SET_MASK 0x80000 1859*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 1860*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 1861*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_OP_SHIFT 21 1862*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_TENSOR_CONFIG_RMW_OP_MASK 0x600000 1863*e65e175bSOded Gabbay 1864*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE */ 1865*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE_V_SHIFT 0 1866*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_DIM_0_SIZE_V_MASK 0xFFFFFFFF 1867*e65e175bSOded Gabbay 1868*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE */ 1869*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE_V_SHIFT 0 1870*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 1871*e65e175bSOded Gabbay 1872*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE */ 1873*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE_V_SHIFT 0 1874*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_DIM_1_SIZE_V_MASK 0xFFFFFFFF 1875*e65e175bSOded Gabbay 1876*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE */ 1877*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE_V_SHIFT 0 1878*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 1879*e65e175bSOded Gabbay 1880*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE */ 1881*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE_V_SHIFT 0 1882*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_DIM_2_SIZE_V_MASK 0xFFFFFFFF 1883*e65e175bSOded Gabbay 1884*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE */ 1885*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE_V_SHIFT 0 1886*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 1887*e65e175bSOded Gabbay 1888*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE */ 1889*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE_V_SHIFT 0 1890*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_DIM_3_SIZE_V_MASK 0xFFFFFFFF 1891*e65e175bSOded Gabbay 1892*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE */ 1893*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE_V_SHIFT 0 1894*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 1895*e65e175bSOded Gabbay 1896*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE */ 1897*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE_V_SHIFT 0 1898*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_DIM_4_SIZE_V_MASK 0xFFFFFFFF 1899*e65e175bSOded Gabbay 1900*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE */ 1901*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE_V_SHIFT 0 1902*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_6_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 1903*e65e175bSOded Gabbay 1904*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW */ 1905*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW_V_SHIFT 0 1906*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 1907*e65e175bSOded Gabbay 1908*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH */ 1909*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH_V_SHIFT 0 1910*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 1911*e65e175bSOded Gabbay 1912*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_7_PADDING_VALUE */ 1913*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_PADDING_VALUE_V_SHIFT 0 1914*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_PADDING_VALUE_V_MASK 0xFFFFFFFF 1915*e65e175bSOded Gabbay 1916*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG */ 1917*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 1918*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 1919*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 1920*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 1921*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_SHIFT 16 1922*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 1923*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_SET_SHIFT 19 1924*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_SET_MASK 0x80000 1925*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 1926*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 1927*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_OP_SHIFT 21 1928*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_TENSOR_CONFIG_RMW_OP_MASK 0x600000 1929*e65e175bSOded Gabbay 1930*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE */ 1931*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE_V_SHIFT 0 1932*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_DIM_0_SIZE_V_MASK 0xFFFFFFFF 1933*e65e175bSOded Gabbay 1934*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE */ 1935*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE_V_SHIFT 0 1936*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 1937*e65e175bSOded Gabbay 1938*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE */ 1939*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE_V_SHIFT 0 1940*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_DIM_1_SIZE_V_MASK 0xFFFFFFFF 1941*e65e175bSOded Gabbay 1942*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE */ 1943*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE_V_SHIFT 0 1944*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 1945*e65e175bSOded Gabbay 1946*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE */ 1947*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE_V_SHIFT 0 1948*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_DIM_2_SIZE_V_MASK 0xFFFFFFFF 1949*e65e175bSOded Gabbay 1950*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE */ 1951*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE_V_SHIFT 0 1952*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 1953*e65e175bSOded Gabbay 1954*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE */ 1955*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE_V_SHIFT 0 1956*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_DIM_3_SIZE_V_MASK 0xFFFFFFFF 1957*e65e175bSOded Gabbay 1958*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE */ 1959*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE_V_SHIFT 0 1960*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 1961*e65e175bSOded Gabbay 1962*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE */ 1963*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE_V_SHIFT 0 1964*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_DIM_4_SIZE_V_MASK 0xFFFFFFFF 1965*e65e175bSOded Gabbay 1966*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE */ 1967*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE_V_SHIFT 0 1968*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_7_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 1969*e65e175bSOded Gabbay 1970*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW */ 1971*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW_V_SHIFT 0 1972*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 1973*e65e175bSOded Gabbay 1974*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH */ 1975*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH_V_SHIFT 0 1976*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 1977*e65e175bSOded Gabbay 1978*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_8_PADDING_VALUE */ 1979*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_PADDING_VALUE_V_SHIFT 0 1980*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_PADDING_VALUE_V_MASK 0xFFFFFFFF 1981*e65e175bSOded Gabbay 1982*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG */ 1983*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 1984*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 1985*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 1986*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 1987*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_LAST_DIM_SHIFT 16 1988*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 1989*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_SET_SHIFT 19 1990*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_SET_MASK 0x80000 1991*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 1992*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 1993*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_OP_SHIFT 21 1994*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_TENSOR_CONFIG_RMW_OP_MASK 0x600000 1995*e65e175bSOded Gabbay 1996*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_8_DIM_0_SIZE */ 1997*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_DIM_0_SIZE_V_SHIFT 0 1998*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_DIM_0_SIZE_V_MASK 0xFFFFFFFF 1999*e65e175bSOded Gabbay 2000*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE */ 2001*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE_V_SHIFT 0 2002*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 2003*e65e175bSOded Gabbay 2004*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_8_DIM_1_SIZE */ 2005*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_DIM_1_SIZE_V_SHIFT 0 2006*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_DIM_1_SIZE_V_MASK 0xFFFFFFFF 2007*e65e175bSOded Gabbay 2008*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE */ 2009*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE_V_SHIFT 0 2010*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 2011*e65e175bSOded Gabbay 2012*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_8_DIM_2_SIZE */ 2013*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_DIM_2_SIZE_V_SHIFT 0 2014*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_DIM_2_SIZE_V_MASK 0xFFFFFFFF 2015*e65e175bSOded Gabbay 2016*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE */ 2017*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE_V_SHIFT 0 2018*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 2019*e65e175bSOded Gabbay 2020*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_8_DIM_3_SIZE */ 2021*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_DIM_3_SIZE_V_SHIFT 0 2022*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_DIM_3_SIZE_V_MASK 0xFFFFFFFF 2023*e65e175bSOded Gabbay 2024*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE */ 2025*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE_V_SHIFT 0 2026*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 2027*e65e175bSOded Gabbay 2028*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_8_DIM_4_SIZE */ 2029*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_DIM_4_SIZE_V_SHIFT 0 2030*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_DIM_4_SIZE_V_MASK 0xFFFFFFFF 2031*e65e175bSOded Gabbay 2032*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE */ 2033*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE_V_SHIFT 0 2034*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_8_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 2035*e65e175bSOded Gabbay 2036*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW */ 2037*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW_V_SHIFT 0 2038*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 2039*e65e175bSOded Gabbay 2040*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH */ 2041*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH_V_SHIFT 0 2042*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 2043*e65e175bSOded Gabbay 2044*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_9_PADDING_VALUE */ 2045*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_PADDING_VALUE_V_SHIFT 0 2046*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_PADDING_VALUE_V_MASK 0xFFFFFFFF 2047*e65e175bSOded Gabbay 2048*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG */ 2049*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 2050*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 2051*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 2052*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 2053*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_LAST_DIM_SHIFT 16 2054*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 2055*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_SET_SHIFT 19 2056*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_SET_MASK 0x80000 2057*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 2058*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 2059*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_OP_SHIFT 21 2060*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_TENSOR_CONFIG_RMW_OP_MASK 0x600000 2061*e65e175bSOded Gabbay 2062*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_9_DIM_0_SIZE */ 2063*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_DIM_0_SIZE_V_SHIFT 0 2064*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_DIM_0_SIZE_V_MASK 0xFFFFFFFF 2065*e65e175bSOded Gabbay 2066*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE */ 2067*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE_V_SHIFT 0 2068*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 2069*e65e175bSOded Gabbay 2070*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_9_DIM_1_SIZE */ 2071*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_DIM_1_SIZE_V_SHIFT 0 2072*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_DIM_1_SIZE_V_MASK 0xFFFFFFFF 2073*e65e175bSOded Gabbay 2074*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE */ 2075*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE_V_SHIFT 0 2076*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 2077*e65e175bSOded Gabbay 2078*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_9_DIM_2_SIZE */ 2079*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_DIM_2_SIZE_V_SHIFT 0 2080*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_DIM_2_SIZE_V_MASK 0xFFFFFFFF 2081*e65e175bSOded Gabbay 2082*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE */ 2083*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE_V_SHIFT 0 2084*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 2085*e65e175bSOded Gabbay 2086*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_9_DIM_3_SIZE */ 2087*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_DIM_3_SIZE_V_SHIFT 0 2088*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_DIM_3_SIZE_V_MASK 0xFFFFFFFF 2089*e65e175bSOded Gabbay 2090*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE */ 2091*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE_V_SHIFT 0 2092*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 2093*e65e175bSOded Gabbay 2094*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_9_DIM_4_SIZE */ 2095*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_DIM_4_SIZE_V_SHIFT 0 2096*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_DIM_4_SIZE_V_MASK 0xFFFFFFFF 2097*e65e175bSOded Gabbay 2098*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE */ 2099*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE_V_SHIFT 0 2100*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_9_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 2101*e65e175bSOded Gabbay 2102*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW */ 2103*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW_V_SHIFT 0 2104*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 2105*e65e175bSOded Gabbay 2106*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH */ 2107*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH_V_SHIFT 0 2108*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 2109*e65e175bSOded Gabbay 2110*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_10_PADDING_VALUE */ 2111*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_PADDING_VALUE_V_SHIFT 0 2112*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_PADDING_VALUE_V_MASK 0xFFFFFFFF 2113*e65e175bSOded Gabbay 2114*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG */ 2115*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 2116*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 2117*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 2118*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 2119*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_LAST_DIM_SHIFT 16 2120*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 2121*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_SET_SHIFT 19 2122*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_SET_MASK 0x80000 2123*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 2124*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 2125*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_OP_SHIFT 21 2126*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_TENSOR_CONFIG_RMW_OP_MASK 0x600000 2127*e65e175bSOded Gabbay 2128*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_10_DIM_0_SIZE */ 2129*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_DIM_0_SIZE_V_SHIFT 0 2130*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_DIM_0_SIZE_V_MASK 0xFFFFFFFF 2131*e65e175bSOded Gabbay 2132*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE */ 2133*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE_V_SHIFT 0 2134*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 2135*e65e175bSOded Gabbay 2136*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_10_DIM_1_SIZE */ 2137*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_DIM_1_SIZE_V_SHIFT 0 2138*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_DIM_1_SIZE_V_MASK 0xFFFFFFFF 2139*e65e175bSOded Gabbay 2140*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE */ 2141*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE_V_SHIFT 0 2142*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 2143*e65e175bSOded Gabbay 2144*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_10_DIM_2_SIZE */ 2145*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_DIM_2_SIZE_V_SHIFT 0 2146*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_DIM_2_SIZE_V_MASK 0xFFFFFFFF 2147*e65e175bSOded Gabbay 2148*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE */ 2149*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE_V_SHIFT 0 2150*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 2151*e65e175bSOded Gabbay 2152*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_10_DIM_3_SIZE */ 2153*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_DIM_3_SIZE_V_SHIFT 0 2154*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_DIM_3_SIZE_V_MASK 0xFFFFFFFF 2155*e65e175bSOded Gabbay 2156*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE */ 2157*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE_V_SHIFT 0 2158*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 2159*e65e175bSOded Gabbay 2160*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_10_DIM_4_SIZE */ 2161*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_DIM_4_SIZE_V_SHIFT 0 2162*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_DIM_4_SIZE_V_MASK 0xFFFFFFFF 2163*e65e175bSOded Gabbay 2164*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE */ 2165*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE_V_SHIFT 0 2166*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_10_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 2167*e65e175bSOded Gabbay 2168*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW */ 2169*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW_V_SHIFT 0 2170*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 2171*e65e175bSOded Gabbay 2172*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH */ 2173*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH_V_SHIFT 0 2174*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 2175*e65e175bSOded Gabbay 2176*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_11_PADDING_VALUE */ 2177*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_PADDING_VALUE_V_SHIFT 0 2178*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_PADDING_VALUE_V_MASK 0xFFFFFFFF 2179*e65e175bSOded Gabbay 2180*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG */ 2181*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 2182*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 2183*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 2184*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 2185*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_LAST_DIM_SHIFT 16 2186*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 2187*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_SET_SHIFT 19 2188*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_SET_MASK 0x80000 2189*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 2190*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 2191*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_OP_SHIFT 21 2192*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_TENSOR_CONFIG_RMW_OP_MASK 0x600000 2193*e65e175bSOded Gabbay 2194*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_11_DIM_0_SIZE */ 2195*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_DIM_0_SIZE_V_SHIFT 0 2196*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_DIM_0_SIZE_V_MASK 0xFFFFFFFF 2197*e65e175bSOded Gabbay 2198*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE */ 2199*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE_V_SHIFT 0 2200*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 2201*e65e175bSOded Gabbay 2202*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_11_DIM_1_SIZE */ 2203*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_DIM_1_SIZE_V_SHIFT 0 2204*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_DIM_1_SIZE_V_MASK 0xFFFFFFFF 2205*e65e175bSOded Gabbay 2206*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE */ 2207*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE_V_SHIFT 0 2208*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 2209*e65e175bSOded Gabbay 2210*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_11_DIM_2_SIZE */ 2211*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_DIM_2_SIZE_V_SHIFT 0 2212*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_DIM_2_SIZE_V_MASK 0xFFFFFFFF 2213*e65e175bSOded Gabbay 2214*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE */ 2215*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE_V_SHIFT 0 2216*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 2217*e65e175bSOded Gabbay 2218*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_11_DIM_3_SIZE */ 2219*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_DIM_3_SIZE_V_SHIFT 0 2220*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_DIM_3_SIZE_V_MASK 0xFFFFFFFF 2221*e65e175bSOded Gabbay 2222*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE */ 2223*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE_V_SHIFT 0 2224*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 2225*e65e175bSOded Gabbay 2226*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_11_DIM_4_SIZE */ 2227*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_DIM_4_SIZE_V_SHIFT 0 2228*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_DIM_4_SIZE_V_MASK 0xFFFFFFFF 2229*e65e175bSOded Gabbay 2230*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE */ 2231*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE_V_SHIFT 0 2232*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_11_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 2233*e65e175bSOded Gabbay 2234*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW */ 2235*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW_V_SHIFT 0 2236*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 2237*e65e175bSOded Gabbay 2238*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH */ 2239*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH_V_SHIFT 0 2240*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 2241*e65e175bSOded Gabbay 2242*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_12_PADDING_VALUE */ 2243*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_PADDING_VALUE_V_SHIFT 0 2244*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_PADDING_VALUE_V_MASK 0xFFFFFFFF 2245*e65e175bSOded Gabbay 2246*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG */ 2247*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 2248*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 2249*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 2250*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 2251*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_LAST_DIM_SHIFT 16 2252*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 2253*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_SET_SHIFT 19 2254*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_SET_MASK 0x80000 2255*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 2256*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 2257*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_OP_SHIFT 21 2258*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_TENSOR_CONFIG_RMW_OP_MASK 0x600000 2259*e65e175bSOded Gabbay 2260*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_12_DIM_0_SIZE */ 2261*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_DIM_0_SIZE_V_SHIFT 0 2262*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_DIM_0_SIZE_V_MASK 0xFFFFFFFF 2263*e65e175bSOded Gabbay 2264*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE */ 2265*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE_V_SHIFT 0 2266*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 2267*e65e175bSOded Gabbay 2268*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_12_DIM_1_SIZE */ 2269*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_DIM_1_SIZE_V_SHIFT 0 2270*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_DIM_1_SIZE_V_MASK 0xFFFFFFFF 2271*e65e175bSOded Gabbay 2272*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE */ 2273*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE_V_SHIFT 0 2274*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 2275*e65e175bSOded Gabbay 2276*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_12_DIM_2_SIZE */ 2277*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_DIM_2_SIZE_V_SHIFT 0 2278*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_DIM_2_SIZE_V_MASK 0xFFFFFFFF 2279*e65e175bSOded Gabbay 2280*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE */ 2281*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE_V_SHIFT 0 2282*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 2283*e65e175bSOded Gabbay 2284*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_12_DIM_3_SIZE */ 2285*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_DIM_3_SIZE_V_SHIFT 0 2286*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_DIM_3_SIZE_V_MASK 0xFFFFFFFF 2287*e65e175bSOded Gabbay 2288*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE */ 2289*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE_V_SHIFT 0 2290*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 2291*e65e175bSOded Gabbay 2292*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_12_DIM_4_SIZE */ 2293*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_DIM_4_SIZE_V_SHIFT 0 2294*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_DIM_4_SIZE_V_MASK 0xFFFFFFFF 2295*e65e175bSOded Gabbay 2296*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE */ 2297*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE_V_SHIFT 0 2298*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_12_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 2299*e65e175bSOded Gabbay 2300*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW */ 2301*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW_V_SHIFT 0 2302*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 2303*e65e175bSOded Gabbay 2304*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH */ 2305*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH_V_SHIFT 0 2306*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 2307*e65e175bSOded Gabbay 2308*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_13_PADDING_VALUE */ 2309*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_PADDING_VALUE_V_SHIFT 0 2310*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_PADDING_VALUE_V_MASK 0xFFFFFFFF 2311*e65e175bSOded Gabbay 2312*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG */ 2313*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 2314*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 2315*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 2316*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 2317*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_LAST_DIM_SHIFT 16 2318*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 2319*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_SET_SHIFT 19 2320*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_SET_MASK 0x80000 2321*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 2322*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 2323*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_OP_SHIFT 21 2324*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_TENSOR_CONFIG_RMW_OP_MASK 0x600000 2325*e65e175bSOded Gabbay 2326*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_13_DIM_0_SIZE */ 2327*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_DIM_0_SIZE_V_SHIFT 0 2328*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_DIM_0_SIZE_V_MASK 0xFFFFFFFF 2329*e65e175bSOded Gabbay 2330*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE */ 2331*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE_V_SHIFT 0 2332*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 2333*e65e175bSOded Gabbay 2334*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_13_DIM_1_SIZE */ 2335*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_DIM_1_SIZE_V_SHIFT 0 2336*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_DIM_1_SIZE_V_MASK 0xFFFFFFFF 2337*e65e175bSOded Gabbay 2338*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE */ 2339*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE_V_SHIFT 0 2340*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 2341*e65e175bSOded Gabbay 2342*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_13_DIM_2_SIZE */ 2343*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_DIM_2_SIZE_V_SHIFT 0 2344*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_DIM_2_SIZE_V_MASK 0xFFFFFFFF 2345*e65e175bSOded Gabbay 2346*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE */ 2347*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE_V_SHIFT 0 2348*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 2349*e65e175bSOded Gabbay 2350*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_13_DIM_3_SIZE */ 2351*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_DIM_3_SIZE_V_SHIFT 0 2352*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_DIM_3_SIZE_V_MASK 0xFFFFFFFF 2353*e65e175bSOded Gabbay 2354*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE */ 2355*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE_V_SHIFT 0 2356*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 2357*e65e175bSOded Gabbay 2358*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_13_DIM_4_SIZE */ 2359*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_DIM_4_SIZE_V_SHIFT 0 2360*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_DIM_4_SIZE_V_MASK 0xFFFFFFFF 2361*e65e175bSOded Gabbay 2362*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE */ 2363*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE_V_SHIFT 0 2364*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_13_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 2365*e65e175bSOded Gabbay 2366*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW */ 2367*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW_V_SHIFT 0 2368*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 2369*e65e175bSOded Gabbay 2370*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH */ 2371*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH_V_SHIFT 0 2372*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 2373*e65e175bSOded Gabbay 2374*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_14_PADDING_VALUE */ 2375*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_PADDING_VALUE_V_SHIFT 0 2376*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_PADDING_VALUE_V_MASK 0xFFFFFFFF 2377*e65e175bSOded Gabbay 2378*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG */ 2379*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 2380*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 2381*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 2382*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 2383*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_LAST_DIM_SHIFT 16 2384*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 2385*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_SET_SHIFT 19 2386*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_SET_MASK 0x80000 2387*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 2388*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 2389*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_OP_SHIFT 21 2390*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_TENSOR_CONFIG_RMW_OP_MASK 0x600000 2391*e65e175bSOded Gabbay 2392*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_14_DIM_0_SIZE */ 2393*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_DIM_0_SIZE_V_SHIFT 0 2394*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_DIM_0_SIZE_V_MASK 0xFFFFFFFF 2395*e65e175bSOded Gabbay 2396*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE */ 2397*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE_V_SHIFT 0 2398*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 2399*e65e175bSOded Gabbay 2400*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_14_DIM_1_SIZE */ 2401*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_DIM_1_SIZE_V_SHIFT 0 2402*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_DIM_1_SIZE_V_MASK 0xFFFFFFFF 2403*e65e175bSOded Gabbay 2404*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE */ 2405*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE_V_SHIFT 0 2406*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 2407*e65e175bSOded Gabbay 2408*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_14_DIM_2_SIZE */ 2409*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_DIM_2_SIZE_V_SHIFT 0 2410*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_DIM_2_SIZE_V_MASK 0xFFFFFFFF 2411*e65e175bSOded Gabbay 2412*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE */ 2413*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE_V_SHIFT 0 2414*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 2415*e65e175bSOded Gabbay 2416*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_14_DIM_3_SIZE */ 2417*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_DIM_3_SIZE_V_SHIFT 0 2418*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_DIM_3_SIZE_V_MASK 0xFFFFFFFF 2419*e65e175bSOded Gabbay 2420*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE */ 2421*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE_V_SHIFT 0 2422*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 2423*e65e175bSOded Gabbay 2424*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_14_DIM_4_SIZE */ 2425*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_DIM_4_SIZE_V_SHIFT 0 2426*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_DIM_4_SIZE_V_MASK 0xFFFFFFFF 2427*e65e175bSOded Gabbay 2428*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE */ 2429*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE_V_SHIFT 0 2430*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_14_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 2431*e65e175bSOded Gabbay 2432*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW */ 2433*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW_V_SHIFT 0 2434*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_LOW_V_MASK 0xFFFFFFFF 2435*e65e175bSOded Gabbay 2436*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH */ 2437*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH_V_SHIFT 0 2438*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_BASE_ADDR_HIGH_V_MASK 0xFFFFFFFF 2439*e65e175bSOded Gabbay 2440*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_15_PADDING_VALUE */ 2441*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_PADDING_VALUE_V_SHIFT 0 2442*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_PADDING_VALUE_V_MASK 0xFFFFFFFF 2443*e65e175bSOded Gabbay 2444*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG */ 2445*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_SHIFT 0 2446*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_DATA_TYPE_MASK 0x7 2447*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_SHIFT 8 2448*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_VALID_DIM_MASK_MASK 0x1F00 2449*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_LAST_DIM_SHIFT 16 2450*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_LAST_DIM_MASK 0x70000 2451*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_SET_SHIFT 19 2452*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_SET_MASK 0x80000 2453*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_SHIFT 20 2454*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_RESERV_MASK 0x100000 2455*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_OP_SHIFT 21 2456*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_TENSOR_CONFIG_RMW_OP_MASK 0x600000 2457*e65e175bSOded Gabbay 2458*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_15_DIM_0_SIZE */ 2459*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_DIM_0_SIZE_V_SHIFT 0 2460*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_DIM_0_SIZE_V_MASK 0xFFFFFFFF 2461*e65e175bSOded Gabbay 2462*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE */ 2463*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE_V_SHIFT 0 2464*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_DIM_0_STRIDE_V_MASK 0xFFFFFFFF 2465*e65e175bSOded Gabbay 2466*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_15_DIM_1_SIZE */ 2467*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_DIM_1_SIZE_V_SHIFT 0 2468*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_DIM_1_SIZE_V_MASK 0xFFFFFFFF 2469*e65e175bSOded Gabbay 2470*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE */ 2471*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE_V_SHIFT 0 2472*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_DIM_1_STRIDE_V_MASK 0xFFFFFFFF 2473*e65e175bSOded Gabbay 2474*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_15_DIM_2_SIZE */ 2475*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_DIM_2_SIZE_V_SHIFT 0 2476*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_DIM_2_SIZE_V_MASK 0xFFFFFFFF 2477*e65e175bSOded Gabbay 2478*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE */ 2479*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE_V_SHIFT 0 2480*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_DIM_2_STRIDE_V_MASK 0xFFFFFFFF 2481*e65e175bSOded Gabbay 2482*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_15_DIM_3_SIZE */ 2483*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_DIM_3_SIZE_V_SHIFT 0 2484*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_DIM_3_SIZE_V_MASK 0xFFFFFFFF 2485*e65e175bSOded Gabbay 2486*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE */ 2487*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE_V_SHIFT 0 2488*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_DIM_3_STRIDE_V_MASK 0xFFFFFFFF 2489*e65e175bSOded Gabbay 2490*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_15_DIM_4_SIZE */ 2491*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_DIM_4_SIZE_V_SHIFT 0 2492*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_DIM_4_SIZE_V_MASK 0xFFFFFFFF 2493*e65e175bSOded Gabbay 2494*e65e175bSOded Gabbay /* TPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE */ 2495*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE_V_SHIFT 0 2496*e65e175bSOded Gabbay #define TPC0_CFG_QM_TENSOR_15_DIM_4_STRIDE_V_MASK 0xFFFFFFFF 2497*e65e175bSOded Gabbay 2498*e65e175bSOded Gabbay /* TPC0_CFG_QM_SYNC_OBJECT_MESSAGE */ 2499*e65e175bSOded Gabbay #define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_SHIFT 0 2500*e65e175bSOded Gabbay #define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_WRITE_VALUE_MASK 0xFFFF 2501*e65e175bSOded Gabbay #define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_RSV_SHIFT 16 2502*e65e175bSOded Gabbay #define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_RSV_MASK 0x1FFF0000 2503*e65e175bSOded Gabbay #define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_SHIFT 29 2504*e65e175bSOded Gabbay #define TPC0_CFG_QM_SYNC_OBJECT_MESSAGE_SO_OPERATION_MASK 0xE0000000 2505*e65e175bSOded Gabbay 2506*e65e175bSOded Gabbay /* TPC0_CFG_QM_SYNC_OBJECT_ADDR */ 2507*e65e175bSOded Gabbay #define TPC0_CFG_QM_SYNC_OBJECT_ADDR_V_SHIFT 0 2508*e65e175bSOded Gabbay #define TPC0_CFG_QM_SYNC_OBJECT_ADDR_V_MASK 0xFFFFFFFF 2509*e65e175bSOded Gabbay 2510*e65e175bSOded Gabbay /* TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW */ 2511*e65e175bSOded Gabbay #define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW_V_SHIFT 0 2512*e65e175bSOded Gabbay #define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW_V_MASK 0xFFFFFFFF 2513*e65e175bSOded Gabbay 2514*e65e175bSOded Gabbay /* TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH */ 2515*e65e175bSOded Gabbay #define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH_V_SHIFT 0 2516*e65e175bSOded Gabbay #define TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH_V_MASK 0xFFFFFFFF 2517*e65e175bSOded Gabbay 2518*e65e175bSOded Gabbay /* TPC0_CFG_QM_TID_BASE_DIM_0 */ 2519*e65e175bSOded Gabbay #define TPC0_CFG_QM_TID_BASE_DIM_0_V_SHIFT 0 2520*e65e175bSOded Gabbay #define TPC0_CFG_QM_TID_BASE_DIM_0_V_MASK 0xFFFFFFFF 2521*e65e175bSOded Gabbay 2522*e65e175bSOded Gabbay /* TPC0_CFG_QM_TID_SIZE_DIM_0 */ 2523*e65e175bSOded Gabbay #define TPC0_CFG_QM_TID_SIZE_DIM_0_V_SHIFT 0 2524*e65e175bSOded Gabbay #define TPC0_CFG_QM_TID_SIZE_DIM_0_V_MASK 0xFFFFFFFF 2525*e65e175bSOded Gabbay 2526*e65e175bSOded Gabbay /* TPC0_CFG_QM_TID_BASE_DIM_1 */ 2527*e65e175bSOded Gabbay #define TPC0_CFG_QM_TID_BASE_DIM_1_V_SHIFT 0 2528*e65e175bSOded Gabbay #define TPC0_CFG_QM_TID_BASE_DIM_1_V_MASK 0xFFFFFFFF 2529*e65e175bSOded Gabbay 2530*e65e175bSOded Gabbay /* TPC0_CFG_QM_TID_SIZE_DIM_1 */ 2531*e65e175bSOded Gabbay #define TPC0_CFG_QM_TID_SIZE_DIM_1_V_SHIFT 0 2532*e65e175bSOded Gabbay #define TPC0_CFG_QM_TID_SIZE_DIM_1_V_MASK 0xFFFFFFFF 2533*e65e175bSOded Gabbay 2534*e65e175bSOded Gabbay /* TPC0_CFG_QM_TID_BASE_DIM_2 */ 2535*e65e175bSOded Gabbay #define TPC0_CFG_QM_TID_BASE_DIM_2_V_SHIFT 0 2536*e65e175bSOded Gabbay #define TPC0_CFG_QM_TID_BASE_DIM_2_V_MASK 0xFFFFFFFF 2537*e65e175bSOded Gabbay 2538*e65e175bSOded Gabbay /* TPC0_CFG_QM_TID_SIZE_DIM_2 */ 2539*e65e175bSOded Gabbay #define TPC0_CFG_QM_TID_SIZE_DIM_2_V_SHIFT 0 2540*e65e175bSOded Gabbay #define TPC0_CFG_QM_TID_SIZE_DIM_2_V_MASK 0xFFFFFFFF 2541*e65e175bSOded Gabbay 2542*e65e175bSOded Gabbay /* TPC0_CFG_QM_TID_BASE_DIM_3 */ 2543*e65e175bSOded Gabbay #define TPC0_CFG_QM_TID_BASE_DIM_3_V_SHIFT 0 2544*e65e175bSOded Gabbay #define TPC0_CFG_QM_TID_BASE_DIM_3_V_MASK 0xFFFFFFFF 2545*e65e175bSOded Gabbay 2546*e65e175bSOded Gabbay /* TPC0_CFG_QM_TID_SIZE_DIM_3 */ 2547*e65e175bSOded Gabbay #define TPC0_CFG_QM_TID_SIZE_DIM_3_V_SHIFT 0 2548*e65e175bSOded Gabbay #define TPC0_CFG_QM_TID_SIZE_DIM_3_V_MASK 0xFFFFFFFF 2549*e65e175bSOded Gabbay 2550*e65e175bSOded Gabbay /* TPC0_CFG_QM_TID_BASE_DIM_4 */ 2551*e65e175bSOded Gabbay #define TPC0_CFG_QM_TID_BASE_DIM_4_V_SHIFT 0 2552*e65e175bSOded Gabbay #define TPC0_CFG_QM_TID_BASE_DIM_4_V_MASK 0xFFFFFFFF 2553*e65e175bSOded Gabbay 2554*e65e175bSOded Gabbay /* TPC0_CFG_QM_TID_SIZE_DIM_4 */ 2555*e65e175bSOded Gabbay #define TPC0_CFG_QM_TID_SIZE_DIM_4_V_SHIFT 0 2556*e65e175bSOded Gabbay #define TPC0_CFG_QM_TID_SIZE_DIM_4_V_MASK 0xFFFFFFFF 2557*e65e175bSOded Gabbay 2558*e65e175bSOded Gabbay /* TPC0_CFG_QM_KERNEL_CONFIG */ 2559*e65e175bSOded Gabbay #define TPC0_CFG_QM_KERNEL_CONFIG_SMALL_VLM_SHIFT 0 2560*e65e175bSOded Gabbay #define TPC0_CFG_QM_KERNEL_CONFIG_SMALL_VLM_MASK 0x1 2561*e65e175bSOded Gabbay #define TPC0_CFG_QM_KERNEL_CONFIG_ASO_EVICT_L0_SHIFT 1 2562*e65e175bSOded Gabbay #define TPC0_CFG_QM_KERNEL_CONFIG_ASO_EVICT_L0_MASK 0x2 2563*e65e175bSOded Gabbay #define TPC0_CFG_QM_KERNEL_CONFIG_NUM_VALID_SRFS_SHIFT 2 2564*e65e175bSOded Gabbay #define TPC0_CFG_QM_KERNEL_CONFIG_NUM_VALID_SRFS_MASK 0xFC 2565*e65e175bSOded Gabbay #define TPC0_CFG_QM_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_SHIFT 8 2566*e65e175bSOded Gabbay #define TPC0_CFG_QM_KERNEL_CONFIG_RD_RATE_LIMIT_RST_TOKEN_MASK 0xFF00 2567*e65e175bSOded Gabbay #define TPC0_CFG_QM_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_SHIFT 16 2568*e65e175bSOded Gabbay #define TPC0_CFG_QM_KERNEL_CONFIG_WR_RATE_LIMIT_RST_TOKEN_MASK 0xFF0000 2569*e65e175bSOded Gabbay 2570*e65e175bSOded Gabbay /* TPC0_CFG_QM_KERNEL_ID */ 2571*e65e175bSOded Gabbay #define TPC0_CFG_QM_KERNEL_ID_V_SHIFT 0 2572*e65e175bSOded Gabbay #define TPC0_CFG_QM_KERNEL_ID_V_MASK 0xFFFF 2573*e65e175bSOded Gabbay 2574*e65e175bSOded Gabbay /* TPC0_CFG_QM_SRF */ 2575*e65e175bSOded Gabbay #define TPC0_CFG_QM_SRF_V_SHIFT 0 2576*e65e175bSOded Gabbay #define TPC0_CFG_QM_SRF_V_MASK 0xFFFFFFFF 2577*e65e175bSOded Gabbay 2578*e65e175bSOded Gabbay #endif /* ASIC_REG_TPC0_CFG_MASKS_H_ */ 2579