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/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dgpio.h18 #define PIN_BASE 0
24 #define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0)
25 #define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1)
26 #define AT91_PIN_PA2 (PIN_BASE + 0x00 + 2)
27 #define AT91_PIN_PA3 (PIN_BASE + 0x00 + 3)
28 #define AT91_PIN_PA4 (PIN_BASE + 0x00 + 4)
29 #define AT91_PIN_PA5 (PIN_BASE + 0x00 + 5)
30 #define AT91_PIN_PA6 (PIN_BASE + 0x00 + 6)
31 #define AT91_PIN_PA7 (PIN_BASE + 0x00 + 7)
32 #define AT91_PIN_PA8 (PIN_BASE + 0x00 + 8)
[all …]
H A Dat91_mc.h9 #define AT91_ASM_MC_EBI_CSA (ATMEL_BASE_MC + 0x60)
10 #define AT91_ASM_MC_EBI_CFG (ATMEL_BASE_MC + 0x64)
11 #define AT91_ASM_MC_SMC_CSR0 (ATMEL_BASE_MC + 0x70)
12 #define AT91_ASM_MC_SDRAMC_MR (ATMEL_BASE_MC + 0x90)
13 #define AT91_ASM_MC_SDRAMC_TR (ATMEL_BASE_MC + 0x94)
14 #define AT91_ASM_MC_SDRAMC_CR (ATMEL_BASE_MC + 0x98)
19 u32 csa; /* 0x00 Chip Select Assignment Register */
20 u32 cfgr; /* 0x04 Configuration Register */
24 #define AT91_EBI_CSA_CS0A 0x0001
25 #define AT91_EBI_CSA_CS1A 0x0002
[all …]
/openbmc/u-boot/board/intel/bayleybay/acpi/
H A Dmainboard.asl21 IO(Decode16, 0x60, 0x60, 0x00, 0x01)
22 IO(Decode16, 0x64, 0x64, 0x00, 0x01)
26 Method(_STA, 0, Serialized)
38 IO(Decode16, 0x60, 0x60, 0x00, 0x01)
39 IO(Decode16, 0x64, 0x64, 0x00, 0x01)
43 Method(_STA, 0, Serialized)
/openbmc/openbmc/meta-facebook/meta-catalina/recipes-phosphor/configuration/entity-manager/clemente/
H A Dblacklist.json4 "bus": 0,
5 "addresses": ["0x1f", "0x20", "0x21", "0x40", "0x41", "0x43", "0x50", string
6 "0x52", "0x56", "0x71", "0x72", "0x73", "0x74", "0x75",
7 "0x76", "0x77"]
11 "addresses": ["0x0c", "0x12", "0x14", "0x18", "0x1e", "0x20", "0x21", string
12 "0x22", "0x23", "0x25", "0x27", "0x28", "0x2c", "0x2f",
13 "0x34", "0x35", "0x37", "0x41", "0x42", "0x43", "0x44",
14 "0x4a", "0x4b", "0x4c", "0x4e", "0x4f", "0x51", "0x54",
15 "0x60", "0x61", "0x62", "0x70"]
22 "addresses": ["0x30", "0x31", "0x33", "0x40", "0x41", "0x42", "0x44", string
[all …]
/openbmc/qemu/tests/qtest/
H A Dboot-serial-test.c21 0x88, 0xe0, /* ldi r24, 0x08 */
22 0x80, 0x93, 0xc1, 0x00, /* sts 0x00C1, r24 ; Enable tx */
23 0x86, 0xe0, /* ldi r24, 0x06 */
24 0x80, 0x93, 0xc2, 0x00, /* sts 0x00C2, r24 ; Set the data bits to 8 */
25 0x84, 0xe5, /* ldi r24, 0x54 */
26 0x80, 0x93, 0xc6, 0x00, /* sts 0x00C6, r24 ; Output 'T' */
30 0x0c, 0xc0, 0x3f, 0x14, /* lu12i.w $t0, 0x1fe00 */
31 0x8c, 0x81, 0x87, 0x03, /* ori $t0, $t0, 0x1e0 */
32 0x0d, 0x50, 0x81, 0x03, /* li.w $t1, 'T' */
33 0x8d, 0x01, 0x00, 0x29, /* st.b $t1, $t0, 0 */
[all …]
H A Dtmp105-test.c19 #define TMP105_TEST_ADDR 0x49
51 g_assert_cmpuint(value, ==, 0); in send_and_receive()
54 g_assert_cmphex(value, ==, 0); in send_and_receive()
61 g_assert_cmphex(value, ==, 0x1400); in send_and_receive()
69 i2c_set8(i2cdev, TMP105_REG_CONFIG, 0x60); in send_and_receive()
71 g_assert_cmphex(value, ==, 0x60); in send_and_receive()
74 g_assert_cmphex(value, ==, 0x14f0); in send_and_receive()
77 i2c_set8(i2cdev, TMP105_REG_CONFIG, 0x00); in send_and_receive()
78 g_assert_cmphex(i2c_get8(i2cdev, TMP105_REG_CONFIG), ==, 0x00); in send_and_receive()
80 g_assert_cmphex(value, ==, 0x1480); in send_and_receive()
[all …]
H A Dpca9552-test.c18 #define PCA9552_TEST_ADDR 0x60
22 /* Switch on LEDs 0 and 12 */ in pca9552_init()
23 i2c_set8(i2cdev, PCA9552_LS0, 0x54); in pca9552_init()
24 i2c_set8(i2cdev, PCA9552_LS3, 0x54); in pca9552_init()
39 g_assert_cmphex(resp, ==, 0x54); in receive_autoinc()
43 g_assert_cmphex(resp, ==, 0x55); in receive_autoinc()
47 g_assert_cmphex(resp, ==, 0x55); in receive_autoinc()
51 g_assert_cmphex(resp, ==, 0x54); in receive_autoinc()
60 g_assert_cmphex(value, ==, 0x55); in send_and_receive()
63 g_assert_cmphex(value, ==, 0xFF); in send_and_receive()
[all …]
/openbmc/openbmc/meta-facebook/meta-catalina/recipes-phosphor/configuration/entity-manager/catalina/
H A Dblacklist.json4 "bus": 0,
6 "0x10", string
7 "0x1f",
8 "0x20",
9 "0x21",
10 "0x32",
11 "0x50",
12 "0x71",
13 "0x72",
14 "0x73",
[all …]
/openbmc/openbmc/meta-ibm/meta-system1/recipes-phosphor/configurations/entity-manager/
H A Dblacklist.json4 "bus": 0,
6 "0x60",
7 "0x61",
8 "0x62",
9 "0x63",
10 "0x64",
11 "0x65",
12 "0x66",
13 "0x67"
25 "0x1a", string
[all …]
/openbmc/openbmc/meta-facebook/meta-yosemite5/recipes-phosphor/configuration/entity-manager/
H A Dblacklist.json3 0, number
10 "0x10", string
11 "0x1f",
12 "0x32",
13 "0x61"
22 "0x0f", string
23 "0x14",
24 "0x1d",
25 "0x1e",
26 "0x1f",
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dgpio.h12 u32 reserved0[(0x30 - 0x08) / 4];
22 u32 reserved1[(0x60 - 0x54) / 4];
25 check_member(rockchip_gpio_regs, ls_sync, 0x60);
28 GPIO_PULL_NORMAL = 0,
40 GPIO_OFFSET_MASK = 0x1f,
46 BANK_A = 0,
53 GPIO_INPUT = 0,
/openbmc/u-boot/arch/x86/cpu/broadwell/
H A Dsata.c27 * 0 = port 0 DEVSLP on DEVSLP0/GPIO33
34 * 0: DEVSLP is enabled
55 dm_pci_read_config16(dev, 0x92, &reg16); in broadwell_sata_init()
56 reg16 &= ~0xf; in broadwell_sata_init()
57 reg16 |= 0x8000 | plat->port_map; in broadwell_sata_init()
58 dm_pci_write_config16(dev, 0x92, reg16); in broadwell_sata_init()
62 dm_pci_read_config32(dev, 0x98, &reg32); in broadwell_sata_init()
66 dm_pci_write_config32(dev, 0x98, reg32); in broadwell_sata_init()
69 reg16 = 0; /* Disable alternate ID */ in broadwell_sata_init()
71 dm_pci_write_config16(dev, 0x9c, reg16); in broadwell_sata_init()
[all …]
/openbmc/openbmc/meta-facebook/meta-harma/recipes-phosphor/configuration/entity-manager/
H A Dblacklist.json3 0, number
7 "0x08", string
8 "0x09",
9 "0x0A",
10 "0x0B",
11 "0x0C",
12 "0x0D",
13 "0x0E",
14 "0x0F",
15 "0x10",
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-imx/
H A Dcpu.h6 #define MXC_CPU_MX23 0x23
7 #define MXC_CPU_MX25 0x25
8 #define MXC_CPU_MX27 0x27
9 #define MXC_CPU_MX28 0x28
10 #define MXC_CPU_MX31 0x31
11 #define MXC_CPU_MX35 0x35
12 #define MXC_CPU_MX51 0x51
13 #define MXC_CPU_MX53 0x53
14 #define MXC_CPU_MX6SL 0x60
15 #define MXC_CPU_MX6DL 0x61
[all …]
/openbmc/u-boot/drivers/video/tegra124/
H A Ddisplayport.h18 #define DPAUX_INTR_EN_AUX 0x1
19 #define DPAUX_INTR_AUX 0x5
20 #define DPAUX_DP_AUXDATA_WRITE_W(i) (0x9 + 4 * (i))
21 #define DPAUX_DP_AUXDATA_READ_W(i) (0x19 + 4 * (i))
22 #define DPAUX_DP_AUXADDR 0x29
23 #define DPAUX_DP_AUXCTL 0x2d
24 #define DPAUX_DP_AUXCTL_CMDLEN_SHIFT 0
25 #define DPAUX_DP_AUXCTL_CMDLEN_FIELD 0xff
27 #define DPAUX_DP_AUXCTL_CMD_MASK (0xf << 12)
28 #define DPAUX_DP_AUXCTL_CMD_I2CWR (0 << 12)
[all …]
/openbmc/openbmc/meta-ibm/recipes-phosphor/chassis/power-workarounds/witherspoon/
H A Dpower-workarounds.sh5 i2cset -y 4 0x70 0x00 0x01 b
6 i2cset -y 4 0x70 0x02 0x16 b #respond to ENABLE pin
7 i2cset -y 4 0x70 0x00 0x00 b
9 i2cset -y 5 0x70 0x00 0x01 b
10 i2cset -y 5 0x70 0x02 0x16 b #respond to ENABLE pin
11 i2cset -y 5 0x70 0x00 0x00 b
14 i2cset -y 4 0x12 0xFF 0x00 b # VDD/VCS 0
15 i2cset -y 4 0x12 0x2E 0x03 b # VDD/VCS 0
16 i2cset -y 4 0x13 0xFF 0x00 b # VDN 0
17 i2cset -y 4 0x13 0x2E 0x03 b # VDN 0
[all …]
/openbmc/u-boot/arch/x86/include/asm/arch-broadwell/
H A Dpch.h12 #define PMBASE 0x40
13 #define ACPI_CNTL 0x44
16 #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
17 #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
20 #define PCIEXBAR 0x60
22 #define PCH_DEV_LPC PCI_BDF(0, 0x1f, 0)
25 #define OIC 0x31fe /* 16bit */
26 #define HPTC 0x3404 /* 32bit */
27 #define FD 0x3418 /* 32bit */
29 /* Function Disable 1 RCBA 0x3418 */
[all …]
/openbmc/qemu/tests/tcg/hexagon/
H A Dhvx_histogram_input.h18 { 0x26, 0x32, 0x2e, 0x2e, 0x2d, 0x2c, 0x2d, 0x2d,
19 0x2c, 0x2e, 0x31, 0x33, 0x36, 0x39, 0x3b, 0x3f,
20 0x42, 0x46, 0x4a, 0x4c, 0x51, 0x53, 0x53, 0x54,
21 0x56, 0x57, 0x58, 0x57, 0x56, 0x52, 0x51, 0x4f,
22 0x4c, 0x49, 0x47, 0x42, 0x3e, 0x3b, 0x38, 0x35,
23 0x33, 0x30, 0x2e, 0x2c, 0x2b, 0x2a, 0x2a, 0x28,
24 0x28, 0x27, 0x27, 0x28, 0x29, 0x2a, 0x2c, 0x2e,
25 0x2f, 0x33, 0x36, 0x38, 0x3c, 0x3d, 0x40, 0x42,
26 0x43, 0x42, 0x43, 0x44, 0x43, 0x41, 0x40, 0x3b,
27 0x3b, 0x3a, 0x38, 0x35, 0x32, 0x2f, 0x2c, 0x29,
[all …]
/openbmc/u-boot/cmd/aspeed/nettest/
H A Dmem_io.h4 #define MAC1_BASE 0x1e660000
5 #define MAC2_BASE 0x1e680000
6 #define MDIO0_BASE (MAC1_BASE + 0x60)
7 #define MDIO1_BASE (MAC2_BASE + 0x60)
8 #define SCU_BASE 0x1e6e2000
12 #define MAC3_BASE 0x1e670000
13 #define MAC4_BASE 0x1e690000
15 #define PMI_BASE 0x1e650000
18 #define MDIO0_BASE (PMI_BASE + 0x00)
19 #define MDIO1_BASE (PMI_BASE + 0x08)
[all …]
/openbmc/qemu/ui/
H A Dvgafont.h3 /* 0 0x00 '^@' */
4 0x00, /* 00000000 */
5 0x00, /* 00000000 */
6 0x00, /* 00000000 */
7 0x00, /* 00000000 */
8 0x00, /* 00000000 */
9 0x00, /* 00000000 */
10 0x00, /* 00000000 */
11 0x00, /* 00000000 */
12 0x00, /* 00000000 */
[all …]
/openbmc/u-boot/include/
H A Dvideo_font_data.h19 /* 0 0x00 '^@' */
20 0x00, /* 00000000 */
21 0x00, /* 00000000 */
22 0x00, /* 00000000 */
23 0x00, /* 00000000 */
24 0x00, /* 00000000 */
25 0x00, /* 00000000 */
26 0x00, /* 00000000 */
27 0x00, /* 00000000 */
28 0x00, /* 00000000 */
[all …]
H A Di8042.h14 #define I8042_DATA_REG 0x60 /* keyboard i/o buffer */
15 #define I8042_STS_REG 0x64 /* keyboard status read */
16 #define I8042_CMD_REG 0x64 /* keyboard ctrl write */
19 #define STATUS_OBF (1 << 0)
23 #define CONFIG_KIRQ_EN (1 << 0)
31 #define CMD_RD_CONFIG 0x20 /* read configuration byte */
32 #define CMD_WR_CONFIG 0x60 /* write configuration byte */
33 #define CMD_SELF_TEST 0xaa /* controller self-test */
34 #define CMD_KBD_DIS 0xad /* keyboard disable */
35 #define CMD_KBD_EN 0xae /* keyboard enable */
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dsocfpga.dtsi23 #size-cells = <0>;
26 cpu0: cpu@0 {
29 reg = <0>;
43 interrupts = <0 176 4>, <0 177 4>;
45 reg = <0xff111000 0x1000>,
46 <0xff113000 0x1000>;
53 reg = <0xfffed000 0x1000>,
54 <0xfffec100 0x100>;
73 reg = <0xffe01000 0x1000>;
74 interrupts = <0 104 4>,
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dfirewall_s10.h11 u32 nand; /* 0x00 */
15 u32 usb1; /* 0x10 */
19 u32 spim1; /* 0x20 */
23 u32 emac1; /* 0x30 */
27 u32 sdmmc; /* 0x40 */
31 u32 i2c0; /* 0x50 */
35 u32 i2c4; /* 0x60 */
39 u32 uart1; /* 0x70 */
43 u32 _pad_0x00; /* 0x00 */
47 u32 emac0tx_ecc; /* 0x10 */
[all …]
/openbmc/qemu/tests/qtest/migration/ppc64/
H A Da-b-kernel.h7 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
8 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
9 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
11 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
12 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
13 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
14 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
15 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
16 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
[all …]

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