1*5c8f9400Sryan_chen //#include "io.h" 2*5c8f9400Sryan_chen #include <asm/io.h> 3*5c8f9400Sryan_chen 4*5c8f9400Sryan_chen #define MAC1_BASE 0x1e660000 5*5c8f9400Sryan_chen #define MAC2_BASE 0x1e680000 6*5c8f9400Sryan_chen #define MDIO0_BASE (MAC1_BASE + 0x60) 7*5c8f9400Sryan_chen #define MDIO1_BASE (MAC2_BASE + 0x60) 8*5c8f9400Sryan_chen #define SCU_BASE 0x1e6e2000 9*5c8f9400Sryan_chen 10*5c8f9400Sryan_chen 11*5c8f9400Sryan_chen #ifdef CONFIG_ASPEED_AST2600 12*5c8f9400Sryan_chen #define MAC3_BASE 0x1e670000 13*5c8f9400Sryan_chen #define MAC4_BASE 0x1e690000 14*5c8f9400Sryan_chen 15*5c8f9400Sryan_chen #define PMI_BASE 0x1e650000 16*5c8f9400Sryan_chen #undef MDIO0_BASE 17*5c8f9400Sryan_chen #undef MDIO1_BASE 18*5c8f9400Sryan_chen #define MDIO0_BASE (PMI_BASE + 0x00) 19*5c8f9400Sryan_chen #define MDIO1_BASE (PMI_BASE + 0x08) 20*5c8f9400Sryan_chen #define MDIO2_BASE (PMI_BASE + 0x10) 21*5c8f9400Sryan_chen #define MDIO3_BASE (PMI_BASE + 0x18) 22*5c8f9400Sryan_chen #endif 23*5c8f9400Sryan_chen 24*5c8f9400Sryan_chen #define GPIO_BASE 0x1e780000 25*5c8f9400Sryan_chen 26*5c8f9400Sryan_chen /* macros for register access */ 27*5c8f9400Sryan_chen #define SCU_RD(offset) readl(SCU_BASE + offset) 28*5c8f9400Sryan_chen #define SCU_WR(value, offset) writel(value, SCU_BASE + offset) 29*5c8f9400Sryan_chen 30*5c8f9400Sryan_chen #define MAC1_RD(offset) readl(MAC1_BASE + offset) 31*5c8f9400Sryan_chen #define MAC1_WR(value, offset) writel(value, MAC1_BASE + offset) 32*5c8f9400Sryan_chen #define MAC2_RD(offset) readl(MAC2_BASE + offset) 33*5c8f9400Sryan_chen #define MAC2_WR(value, offset) writel(value, MAC2_BASE + offset) 34*5c8f9400Sryan_chen #ifdef CONFIG_ASPEED_AST2600 35*5c8f9400Sryan_chen #define MAC3_RD(offset) readl(MAC3_BASE + offset) 36*5c8f9400Sryan_chen #define MAC3_WR(value, offset) writel(value, MAC3_BASE + offset) 37*5c8f9400Sryan_chen #define MAC4_RD(offset) readl(MAC4_BASE + offset) 38*5c8f9400Sryan_chen #define MAC4_WR(value, offset) writel(value, MAC4_BASE + offset) 39*5c8f9400Sryan_chen #endif 40*5c8f9400Sryan_chen 41*5c8f9400Sryan_chen #define GPIO_RD(offset) readl(GPIO_BASE + offset) 42*5c8f9400Sryan_chen #define GPIO_WR(value, offset) writel(value, GPIO_BASE + offset) 43*5c8f9400Sryan_chen /* typedef for register access */ 44*5c8f9400Sryan_chen typedef union { 45*5c8f9400Sryan_chen uint32_t w; 46*5c8f9400Sryan_chen struct { 47*5c8f9400Sryan_chen uint32_t reserved_0 : 6; /* bit[5:0] */ 48*5c8f9400Sryan_chen uint32_t mac1_interface : 1; /* bit[6] */ 49*5c8f9400Sryan_chen uint32_t mac2_interface : 1; /* bit[7] */ 50*5c8f9400Sryan_chen uint32_t reserved_1 : 24; /* bit[31:8] */ 51*5c8f9400Sryan_chen }b; 52*5c8f9400Sryan_chen } hw_strap1_t; 53*5c8f9400Sryan_chen 54*5c8f9400Sryan_chen typedef union { 55*5c8f9400Sryan_chen uint32_t w; 56*5c8f9400Sryan_chen struct { 57*5c8f9400Sryan_chen uint32_t mac3_interface : 1; /* bit[0] */ 58*5c8f9400Sryan_chen uint32_t mac4_interface : 1; /* bit[1] */ 59*5c8f9400Sryan_chen uint32_t reserved_0 : 30; /* bit[31:2] */ 60*5c8f9400Sryan_chen }b; 61*5c8f9400Sryan_chen } hw_strap2_t; 62*5c8f9400Sryan_chen 63*5c8f9400Sryan_chen uint32_t SRAM_RD(uint32_t addr);