Lines Matching +full:0 +full:x60

27 	 * 0 = port 0 DEVSLP on DEVSLP0/GPIO33
34 * 0: DEVSLP is enabled
55 dm_pci_read_config16(dev, 0x92, &reg16); in broadwell_sata_init()
56 reg16 &= ~0xf; in broadwell_sata_init()
57 reg16 |= 0x8000 | plat->port_map; in broadwell_sata_init()
58 dm_pci_write_config16(dev, 0x92, reg16); in broadwell_sata_init()
62 dm_pci_read_config32(dev, 0x98, &reg32); in broadwell_sata_init()
66 dm_pci_write_config32(dev, 0x98, reg32); in broadwell_sata_init()
69 reg16 = 0; /* Disable alternate ID */ in broadwell_sata_init()
71 dm_pci_write_config16(dev, 0x9c, reg16); in broadwell_sata_init()
74 reg32 = 0x183; in broadwell_sata_init()
75 reg32 |= (plat->port_map ^ 0xf) << 24; in broadwell_sata_init()
77 dm_pci_write_config32(dev, 0x94, reg32); in broadwell_sata_init()
85 clrsetbits_le32(abar + 0x00, 0x00020060 /* SXS+EMS+PMS */, in broadwell_sata_init()
86 0x0c006000 /* PSC+SSC+SALP+SSS */ | in broadwell_sata_init()
90 writel(plat->port_map, abar + 0x0c); in broadwell_sata_init()
91 (void) readl(abar + 0x0c); /* Read back 1 */ in broadwell_sata_init()
92 (void) readl(abar + 0x0c); /* Read back 2 */ in broadwell_sata_init()
96 clrbits_le32(abar + 0x24, 1 << 3); in broadwell_sata_init()
99 setbits_le32(abar + 0x24, 1 << 5 | 1 << 4 | 1 << 3 | 1 << 2); in broadwell_sata_init()
101 for (port = 0; port < 4; port++) { in broadwell_sata_init()
105 setbits_le32(abar + 0x144 + (0x80 * port), 1 << 1); in broadwell_sata_init()
110 reg32 = readl(RCB_REG(0x3a84)); in broadwell_sata_init()
112 if ((plat->port_map & ((1 << 3)|(1 << 2))) == 0) in broadwell_sata_init()
114 /* Port 1 and 0 disabled */ in broadwell_sata_init()
115 if ((plat->port_map & ((1 << 1)|(1 << 0))) == 0) in broadwell_sata_init()
117 writel(reg32, RCB_REG(0x3a84)); in broadwell_sata_init()
166 pch_common_sir_write(dev, 0x64, 0x883c9003); in broadwell_sata_init()
168 /* Step 2: SIR 68h[15:0] = 880Ah */ in broadwell_sata_init()
169 reg32 = pch_common_sir_read(dev, 0x68); in broadwell_sata_init()
170 reg32 &= 0xffff0000; in broadwell_sata_init()
171 reg32 |= 0x880a; in broadwell_sata_init()
172 pch_common_sir_write(dev, 0x68, reg32); in broadwell_sata_init()
175 reg32 = pch_common_sir_read(dev, 0x60); in broadwell_sata_init()
177 pch_common_sir_write(dev, 0x60, reg32); in broadwell_sata_init()
179 /* Step 4: SIR 60h[0] = 1 */ in broadwell_sata_init()
180 reg32 = pch_common_sir_read(dev, 0x60); in broadwell_sata_init()
181 reg32 |= (1 << 0); in broadwell_sata_init()
182 pch_common_sir_write(dev, 0x60, reg32); in broadwell_sata_init()
185 reg32 = pch_common_sir_read(dev, 0x60); in broadwell_sata_init()
187 pch_common_sir_write(dev, 0x60, reg32); in broadwell_sata_init()
190 pch_common_sir_write(dev, 0x70, 0x3f00bf1f); in broadwell_sata_init()
191 pch_common_sir_write(dev, 0x54, 0xcf000f0f); in broadwell_sata_init()
192 pch_common_sir_write(dev, 0x58, 0x00190000); in broadwell_sata_init()
193 clrsetbits_le32(RCB_REG(0x333c), 0x00300000, 0x00c00000); in broadwell_sata_init()
195 dm_pci_read_config32(dev, 0x300, &reg32); in broadwell_sata_init()
198 dm_pci_write_config32(dev, 0x300, reg32); in broadwell_sata_init()
200 dm_pci_read_config32(dev, 0x98, &reg32); in broadwell_sata_init()
202 dm_pci_write_config32(dev, 0x98, reg32); in broadwell_sata_init()
205 dm_pci_read_config32(dev, 0x9c, &reg32); in broadwell_sata_init()
207 dm_pci_write_config32(dev, 0x9c, reg32); in broadwell_sata_init()
221 map = 0x0060; in broadwell_sata_enable()
223 map |= (plat->port_map ^ 0x3f) << 8; in broadwell_sata_enable()
224 dm_pci_write_config16(dev, 0x90, map); in broadwell_sata_enable()
226 ret = gpio_request_by_name(dev, "reset-gpio", 0, &desc, GPIOD_IS_OUT); in broadwell_sata_enable()
230 return 0; in broadwell_sata_enable()
239 plat->port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0); in broadwell_sata_ofdata_to_platdata()
241 "intel,sata-port0-gen3-tx", 0); in broadwell_sata_ofdata_to_platdata()
243 return 0; in broadwell_sata_ofdata_to_platdata()
253 return 0; in broadwell_sata_probe()