Lines Matching +full:0 +full:x60
11 u32 nand; /* 0x00 */
15 u32 usb1; /* 0x10 */
19 u32 spim1; /* 0x20 */
23 u32 emac1; /* 0x30 */
27 u32 sdmmc; /* 0x40 */
31 u32 i2c0; /* 0x50 */
35 u32 i2c4; /* 0x60 */
39 u32 uart1; /* 0x70 */
43 u32 _pad_0x00; /* 0x00 */
47 u32 emac0tx_ecc; /* 0x10 */
51 u32 emac2tx_ecc; /* 0x20 */
55 u32 nand_read_ecc; /* 0x30 */
59 u32 sdmmc_ecc; /* 0x40 */
63 u32 _pad_0x50; /* 0x50 */
67 u32 osc0_timer; /* 0x60 */
71 u32 watchdog2; /* 0x70 */
75 #define FIREWALL_L4_DISABLE_ALL (BIT(0) | BIT(24) | BIT(16))
76 #define FIREWALL_BRIDGE_DISABLE_ALL (~0)
79 #define CCU_CPU0_MPRT_ADBASE_DDRREG 0x4400
80 #define CCU_CPU0_MPRT_ADBASE_MEMSPACE0 0x45c0
81 #define CCU_CPU0_MPRT_ADBASE_MEMSPACE1A 0x45e0
82 #define CCU_CPU0_MPRT_ADBASE_MEMSPACE1B 0x4600
83 #define CCU_CPU0_MPRT_ADBASE_MEMSPACE1C 0x4620
84 #define CCU_CPU0_MPRT_ADBASE_MEMSPACE1D 0x4640
85 #define CCU_CPU0_MPRT_ADBASE_MEMSPACE1E 0x4660
87 #define CCU_CPU0_MPRT_ADMASK_MEM_RAM0 0x4688
89 #define CCU_IOM_MPRT_ADBASE_MEMSPACE0 0x18560
90 #define CCU_IOM_MPRT_ADBASE_MEMSPACE1A 0x18580
91 #define CCU_IOM_MPRT_ADBASE_MEMSPACE1B 0x185a0
92 #define CCU_IOM_MPRT_ADBASE_MEMSPACE1C 0x185c0
93 #define CCU_IOM_MPRT_ADBASE_MEMSPACE1D 0x185e0
94 #define CCU_IOM_MPRT_ADBASE_MEMSPACE1E 0x18600
96 #define CCU_IOM_MPRT_ADMASK_MEM_RAM0 0x18628
98 #define CCU_ADMASK_P_MASK BIT(0)
107 #define FW_MPU_DDR_SCR_EN 0x00
108 #define FW_MPU_DDR_SCR_EN_SET 0x04
109 #define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT 0x18
110 #define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT 0x1c
111 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98
112 #define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0x9c
114 #define MPUREGION0_ENABLE BIT(0)