Lines Matching +full:0 +full:x60
12 #define PMBASE 0x40
13 #define ACPI_CNTL 0x44
16 #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */
17 #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */
20 #define PCIEXBAR 0x60
22 #define PCH_DEV_LPC PCI_BDF(0, 0x1f, 0)
25 #define OIC 0x31fe /* 16bit */
26 #define HPTC 0x3404 /* 32bit */
27 #define FD 0x3418 /* 32bit */
29 /* Function Disable 1 RCBA 0x3418 */
30 #define PCH_DISABLE_ALWAYS (1 << 0)
33 #define TCO1_CNT 0x60
37 /* Device 0:0.0 PCI configuration space */
39 #define EPBAR 0x40
40 #define MCHBAR 0x48
41 #define PCIEXBAR 0x60
42 #define DMIBAR 0x68
43 #define GGC 0x50 /* GMCH Graphics Control */
44 #define DEVEN 0x54 /* Device Enable */
52 #define DEVEN_D0EN (1 << 0)
53 #define DPR 0x5c
56 #define DPR_SIZE_MASK 0xff0
58 #define MCHBAR_PEI_VERSION 0x5034
59 #define BIOS_RESET_CPL 0x5da8
60 #define EDRAMBAR 0x5408
61 #define MCH_PAIR 0x5418
62 #define GDXCBAR 0x5420
64 #define PAM0 0x80
65 #define PAM1 0x81
66 #define PAM2 0x82
67 #define PAM3 0x83
68 #define PAM4 0x84
69 #define PAM5 0x85
70 #define PAM6 0x86
73 #define BIOS_MAILBOX_INTERFACE 0x5da4
77 #define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509
78 #define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909
79 #define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa
80 #define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb
81 #define MAILBOX_BIOS_CMD_READ_C9C10_VOLTAGE 0x26
82 #define MAILBOX_BIOS_CMD_WRITE_C9C10_VOLTAGE 0x27
83 /* Errors are returned back in bits 7:0. */
84 #define MAILBOX_BIOS_ERROR_NONE 0
92 /* Data is passed through bits 31:0 of the data register. */
93 #define BIOS_MAILBOX_DATA 0x5da0
96 #define SATA_IOBP_SP0_SECRT88 0xea002688
97 #define SATA_IOBP_SP1_SECRT88 0xea002488
99 #define SATA_SECRT88_VADJ_MASK 0xff
102 #define SATA_IOBP_SP0DTLE_DATA 0xea002550
103 #define SATA_IOBP_SP0DTLE_EDGE 0xea002554
104 #define SATA_IOBP_SP1DTLE_DATA 0xea002750
105 #define SATA_IOBP_SP1DTLE_EDGE 0xea002754
107 #define SATA_DTLE_MASK 0xF
112 #define PCH_PCS 0x84
115 #define GEN_PMCON_1 0xa0
117 #define GEN_PMCON_2 0xa2
121 #define PWROK_FLR (1 << 0)
122 #define GEN_PMCON_3 0xa4
127 #define SLEEP_AFTER_POWER_FAIL (1 << 0)
128 #define GEN_PMCON_LOCK 0xa6
131 #define PMIR 0xac
136 #define PCH_WPT_HSW_U_SAMPLE 0x9cc1
137 #define PCH_WPT_BDW_U_SAMPLE 0x9cc2
138 #define PCH_WPT_BDW_U_PREMIUM 0x9cc3
139 #define PCH_WPT_BDW_U_BASE 0x9cc5
140 #define PCH_WPT_BDW_Y_SAMPLE 0x9cc6
141 #define PCH_WPT_BDW_Y_PREMIUM 0x9cc7
142 #define PCH_WPT_BDW_Y_BASE 0x9cc9
143 #define PCH_WPT_BDW_H 0x9ccb
145 #define SA_IGD_OPROM_VENDEV 0x80860406