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/openbmc/u-boot/board/freescale/mpc8313erdb/
H A Dmpc8313erdb.c35 return 0; in board_early_init_f()
44 return 0; in board_early_init_r()
50 return 0; in checkboard()
83 clk->occr |= 0xe0000000; in pci_init_board()
88 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; in pci_init_board()
89 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; in pci_init_board()
104 int rc = 0; in misc_init_r()
125 return 0; in ft_board_setup()
132 NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), in board_init_f()
152 NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r'); in putc()
[all …]
/openbmc/u-boot/board/freescale/mpc8315erdb/
H A Dmpc8315erdb.c30 return 0; in board_early_init_f()
38 i2c_set_bus_num(0); in read_board_info()
40 if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0) in read_board_info()
43 return 0; in read_board_info()
59 i = (!info) ? 4: info & 0x03; in checkboard()
63 return 0; in checkboard()
128 clk->occr |= 0xe0000000; in pci_init_board()
133 pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR; in pci_init_board()
134 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB; in pci_init_board()
146 out_be32(&sysconf->pecr1, 0xE0008000); in pci_init_board()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dqcom,spmi-rradc.yaml29 enum: [0, 1, 4, 12, 20, 40, 60, 80]
44 #size-cells = <0>;
48 reg = <0x4500>;
/openbmc/openbmc/meta-arm/meta-arm-bsp/recipes-security/trusted-services/corstone1000/
H A D0018-Make-RSS-and-MHU-sizes-compile-time-definitions-user.patch26 +set(PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE 0x43C0 CACHE STRING "Size of the RSS_COMMS_PAYLOAD buffer")
27 +set(COMMS_MHU_MSG_SIZE 0x4500 CACHE STRING "Max message size that can be transfered via MHU")
30 SMM_VARIABLE_INDEX_STORAGE_UID=0x787
31 - PLAT_RSS_COMMS_PAYLOAD_MAX_SIZE=0x2080
32 - COMMS_MHU_MSG_SIZE=0x3500
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dpq3-duart-0.dtsi2 * PQ3 DUART device tree stub [ controller @ offset 0x4000 ]
36 cell-index = <0>;
39 reg = <0x4500 0x100>;
40 clock-frequency = <0>;
41 interrupts = <42 2 0 0>;
48 reg = <0x4600 0x100>;
49 clock-frequency = <0>;
50 interrupts = <42 2 0 0>;
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dpmi8998.dtsi8 reg = <0x2 SPMI_USID>;
10 #size-cells = <0>;
14 reg = <0x1000>;
16 interrupts = <0x2 0x13 0x4 IRQ_TYPE_EDGE_BOTH>,
17 <0x2 0x12 0x2 IRQ_TYPE_EDGE_BOTH>,
18 <0x2 0x16 0x1 IRQ_TYPE_EDGE_RISING>,
19 <0x2 0x13 0x6 IRQ_TYPE_EDGE_RISING>;
34 reg = <0xc000>;
36 gpio-ranges = <&pmi8998_gpios 0 0 14>;
44 reg = <0x4500>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Domap-spi.yaml109 reg = <0x2100000 0x400>;
114 #size-cells = <0>;
115 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
/openbmc/u-boot/include/configs/
H A Dqemu-ppce500.h27 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
28 #define CONFIG_SYS_MEMTEST_END 0x00400000
33 #define CONFIG_SYS_CCSRBAR 0xe0000000
40 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
45 #define CONFIG_SYS_PCI_MAP_START 0x80000000
46 #define CONFIG_SYS_PCI_MAP_END 0xe8000000
49 #define CONFIG_SYS_TMPVIRT 0xe8000000
55 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
58 #define CONFIG_CHIP_SELECTS_PER_CTRL 0
62 #define CONFIG_SYS_BOOT_BLOCK 0x00000000 /* boot TLB */
[all …]
H A Dcontrolcenterd.h57 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
63 #define CONFIG_SYS_INIT_L2_ADDR 0xf8fc0000
65 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8fc0000ull
74 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
85 * 0x0000_0000 0x3fff_ffff DDR 1G Cacheable
86 * 0xc000_0000 0xdfff_ffff PCI Express Mem 512M non-cacheable
87 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
90 * 0xe000_0000 0xe00f_ffff eLBC 1M non-cacheable
91 * 0xf8fc0000 0xf8ff_ffff L2 SRAM 256k Cacheable
92 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
[all …]
H A DBSC9131RDB.h18 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
27 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000
29 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
30 #define CONFIG_SPL_RELOC_STACK 0x00100000
31 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
32 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
33 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
34 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
62 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
63 #define CONFIG_SYS_MEMTEST_END 0x01ffffff
[all …]
H A DP1023RDB.h17 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
46 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
47 #define CONFIG_SYS_MEMTEST_END 0x02000000
50 #define CONFIG_SYS_LBC_LBCR 0x00000000
55 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
63 #define CONFIG_SYS_SPD_BUS_NUM 0
64 #define SPD_EEPROM_ADDRESS 0x50
70 * 0x0000_0000 0x1fff_ffff DDR 512M cacheable
71 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
72 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
[all …]
/openbmc/linux/drivers/regulator/
H A Dqcom_spmi-regulator.c25 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_NONE 0x00
26 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN0 0x01
27 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN1 0x02
28 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN2 0x04
29 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_EN3 0x08
30 #define SPMI_REGULATOR_PIN_CTRL_ENABLE_HW_DEFAULT 0x10
33 #define SPMI_REGULATOR_PIN_CTRL_HPM_NONE 0x00
34 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN0 0x01
35 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN1 0x02
36 #define SPMI_REGULATOR_PIN_CTRL_HPM_EN2 0x04
[all …]
/openbmc/linux/drivers/dma/ti/
H A Dk3-psil-am654.c54 PSIL_SA2UL(0x4000, 0),
55 PSIL_SA2UL(0x4001, 0),
56 PSIL_SA2UL(0x4002, 0),
57 PSIL_SA2UL(0x4003, 0),
59 PSIL_ETHERNET(0x4100),
60 PSIL_ETHERNET(0x4101),
61 PSIL_ETHERNET(0x4102),
62 PSIL_ETHERNET(0x4103),
64 PSIL_ETHERNET(0x4200),
65 PSIL_ETHERNET(0x4201),
[all …]
H A Dk3-psil-am62.c73 PSIL_SAUL(0x7504, 20, 35, 8, 35, 0),
74 PSIL_SAUL(0x7505, 21, 35, 8, 36, 0),
75 PSIL_SAUL(0x7506, 22, 43, 8, 43, 0),
76 PSIL_SAUL(0x7507, 23, 43, 8, 44, 0),
78 PSIL_PDMA_XY_PKT(0x4300),
79 PSIL_PDMA_XY_PKT(0x4301),
80 PSIL_PDMA_XY_PKT(0x4302),
81 PSIL_PDMA_XY_PKT(0x4303),
82 PSIL_PDMA_XY_PKT(0x4304),
83 PSIL_PDMA_XY_PKT(0x4305),
[all …]
H A Dk3-psil-am62a.c83 PSIL_SAUL(0x7504, 20, 35, 8, 35, 0),
84 PSIL_SAUL(0x7505, 21, 35, 8, 36, 0),
85 PSIL_SAUL(0x7506, 22, 43, 8, 43, 0),
86 PSIL_SAUL(0x7507, 23, 43, 8, 44, 0),
88 PSIL_PDMA_XY_PKT(0x4300),
89 PSIL_PDMA_XY_PKT(0x4301),
90 PSIL_PDMA_XY_PKT(0x4302),
91 PSIL_PDMA_XY_PKT(0x4303),
92 PSIL_PDMA_XY_PKT(0x4304),
93 PSIL_PDMA_XY_PKT(0x4305),
[all …]
H A Dk3-psil-am64.c66 PSIL_SAUL(0x4000, 17, 32, 8, 32, 0),
67 PSIL_SAUL(0x4001, 18, 32, 8, 33, 0),
68 PSIL_SAUL(0x4002, 19, 40, 8, 40, 0),
69 PSIL_SAUL(0x4003, 20, 40, 8, 41, 0),
71 PSIL_ETHERNET(0x4100, 21, 48, 16),
72 PSIL_ETHERNET(0x4101, 22, 64, 16),
73 PSIL_ETHERNET(0x4102, 23, 80, 16),
74 PSIL_ETHERNET(0x4103, 24, 96, 16),
76 PSIL_ETHERNET(0x4200, 25, 112, 16),
77 PSIL_ETHERNET(0x4201, 26, 128, 16),
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dstorcenter.dts30 #size-cells = <0>;
32 PowerPC,8241@0 {
34 reg = <0>;
37 bus-frequency = <0>; /* from bootwrapper */
47 reg = <0x00000000 0x04000000>; /* 64MB @ 0x0 */
55 store-gathering = <0>; /* 0 == off, !0 == on */
56 ranges = <0x0 0xfc000000 0x100000>;
57 reg = <0xfc000000 0x100000>; /* EUMB */
58 bus-frequency = <0>; /* fixed by loader */
62 #size-cells = <0>;
[all …]
H A Dmpc8349emitxgp.dts25 #size-cells = <0>;
27 PowerPC,8349@0 {
29 reg = <0x0>;
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
42 reg = <0x00000000 0x10000000>;
50 ranges = <0x0 0xe0000000 0x00100000>;
51 reg = <0xe0000000 0x00000200>;
52 bus-frequency = <0>; // from bootloader
[all …]
H A Dmpc8308rdb.dts26 #size-cells = <0>;
28 PowerPC,8308@0 {
30 reg = <0x0>;
35 timebase-frequency = <0>; // from bootloader
36 bus-frequency = <0>; // from bootloader
37 clock-frequency = <0>; // from bootloader
43 reg = <0x00000000 0x08000000>; // 128MB at 0
50 reg = <0xe0005000 0x1000>;
51 interrupts = <77 0x8>;
57 ranges = <0x0 0x0 0xfe000000 0x00800000
[all …]
H A Dmpc8308_p1m.dts25 #size-cells = <0>;
27 PowerPC,8308@0 {
29 reg = <0x0>;
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
42 reg = <0x00000000 0x08000000>; // 128MB at 0
49 reg = <0xe0005000 0x1000>;
50 interrupts = <77 0x8>;
53 ranges = <0x0 0x0 0xfc000000 0x04000000
[all …]
H A Dasp834x-redboot.dts25 #size-cells = <0>;
27 PowerPC,8347@0 {
29 reg = <0x0>;
34 timebase-frequency = <0>; // from bootloader
35 bus-frequency = <0>; // from bootloader
36 clock-frequency = <0>; // from bootloader
42 reg = <0x00000000 0x8000000>; // 128MB at 0
51 reg = <0xff005000 0x1000>;
52 interrupts = <77 0x8>;
56 0 0 0xf0000000 0x02000000
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/therm/
H A Dgk104.c38 for (i = 0; order[i].type != NVKM_SUBDEV_NR; i++) { in gk104_clkgate_enable()
42 nvkm_mask(dev, 0x20200 + order[i].offset, 0xff00, 0x4500); in gk104_clkgate_enable()
46 nvkm_wr32(dev, 0x020288, therm->idle_filter->fecs); in gk104_clkgate_enable()
47 nvkm_wr32(dev, 0x02028c, therm->idle_filter->hubmmu); in gk104_clkgate_enable()
50 for (i = 0; order[i].type != NVKM_SUBDEV_NR; i++) { in gk104_clkgate_enable()
54 nvkm_mask(dev, 0x20200 + order[i].offset, 0x00ff, 0x0045); in gk104_clkgate_enable()
67 for (i = 0; order[i].type != NVKM_SUBDEV_NR; i++) { in gk104_clkgate_fini()
71 nvkm_mask(dev, 0x20200 + order[i].offset, 0xff, 0x54); in gk104_clkgate_fini()
76 { NVKM_ENGINE_GR, 0, 0x00 },
77 { NVKM_ENGINE_MSPDEC, 0, 0x04 },
[all …]
/openbmc/u-boot/include/configs/km/
H A Dkm83xx-common.h24 #define CONFIG_SYS_IMMR 0xE0000000
31 #define CONFIG_SYS_ACR_APARK 0 /* park bus to master (below) */
37 #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
39 #define CONFIG_SYS_SDRAM_BASE2 (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
57 #define CONFIG_SYS_FLASH_BASE 0xF0000000
70 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
71 #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */
80 * 0 Local GPCM 16 bit 256MB FLASH
127 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
129 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
[all …]
/openbmc/linux/drivers/media/i2c/
H A Dov8858.c36 #define OV8858_REG_ADDR_MASK 0xffff
41 #define OV8858_REG_SC_CTRL0100 OV8858_REG_8BIT(0x0100)
42 #define OV8858_MODE_SW_STANDBY 0x0
43 #define OV8858_MODE_STREAMING 0x1
45 #define OV8858_REG_CHIP_ID OV8858_REG_24BIT(0x300a)
46 #define OV8858_CHIP_ID 0x008858
48 #define OV8858_REG_SUB_ID OV8858_REG_8BIT(0x302a)
49 #define OV8858_R1A 0xb0
50 #define OV8858_R2A 0xb2
52 #define OV8858_REG_LONG_EXPO OV8858_REG_24BIT(0x3500)
[all …]
/openbmc/linux/drivers/scsi/esas2r/
H A Datioctl.h58 #define IOCTL_SUCCESS 0
76 * NOTE - if channel == 0xFF, the request is
83 #define FUNC_FW_DOWNLOAD 0x09
84 #define FUNC_FW_UPLOAD 0x12
87 #define FW_IMG_FW 0x01
88 #define FW_IMG_BIOS 0x02
89 #define FW_IMG_NVR 0x03
90 #define FW_IMG_RAW 0x04
91 #define FW_IMG_FM_API 0x05
92 #define FW_IMG_FS_API 0x06
[all …]

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