Lines Matching +full:0 +full:x4500

57 #define CONFIG_RESET_VECTOR_ADDRESS	0xf8fffffc
63 #define CONFIG_SYS_INIT_L2_ADDR		0xf8fc0000
65 #define CONFIG_SYS_INIT_L2_ADDR_PHYS	0xff8fc0000ull
74 #define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
85  * 0x0000_0000	0x3fff_ffff	DDR			1G Cacheable
86  * 0xc000_0000	0xdfff_ffff	PCI Express Mem		512M non-cacheable
87  * 0xffc0_0000	0xffc2_ffff	PCI IO range		192K non-cacheable
90  * 0xe000_0000	0xe00f_ffff	eLBC			1M non-cacheable
91  * 0xf8fc0000	0xf8ff_ffff	L2 SRAM			256k Cacheable
92  * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
93  * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
97 #define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* Initial L1 address */
98 #define CONFIG_SYS_INIT_RAM_SIZE	0x00004000 /* used area in RAM */
107 #define CONFIG_SYS_CCSRBAR		0xffe00000
110 #define CONFIG_SYS_MPC85xx_GPIO3_ADDR	(CONFIG_SYS_CCSRBAR+0xf200)
116 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
124 #define CONFIG_SYS_MEMTEST_START	0x00000000
125 #define CONFIG_SYS_MEMTEST_END		0x3fffffff
129 #define SPD_EEPROM_ADDRESS 0x52
137 #define CONFIG_SYS_ELBC_BASE		0xe0000000
139 #define CONFIG_SYS_ELBC_BASE_PHYS	0xfe0000000ull
146 #define CONFIG_UART_OR_PRELIM	(OR_AM_32KB | 0xff7)
148 #define CONFIG_SYS_BR0_PRELIM	0 /* CS0 was originally intended for FPGA */
149 #define CONFIG_SYS_OR0_PRELIM	0 /* debugging, was never used */
159 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
164 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
165 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
173 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
174 #define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
176 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
177 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
181 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
195 #define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x10000)
199  * Memory space is mapped 1-1, but I/O space must start from 0.
209 #define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
211 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
212 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc40000000ull
214 #define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
215 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
217 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
218 #define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
219 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
221 #define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc20000ull
223 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
225 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
251 #define TSEC1_PHY_ADDR		0
257 #define TSEC1_PHYIDX		0
258 #define TSEC2_PHYIDX		0
276 #define CONFIG_ENV_SIZE		0x2000		/* 8KB */
278 #define CONFIG_ENV_SIZE		0x2000		/* 8KB */
279 #define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
280 #define CONFIG_ENV_SECT_SIZE	0x10000
283 #define CONFIG_ENV_SIZE		0x2000
284 #define CONFIG_SYS_MMC_ENV_DEV	0
291 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
320 	"mp_holdoff=1\0"
332 	"netdev=eth0\0"						\
333 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
334 	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
340 		"cmp.b $loadaddr $ubootaddr $filesize\0"	\
341 	"consoledev=ttyS1\0"					\
342 	"ramdiskaddr=2000000\0"					\
343 	"ramdiskfile=rootfs.ext2.gz.uboot\0"			\
344 	"fdtaddr=1e00000\0"					\
345 	"fdtfile=controlcenterd.dtb\0"				\
346 	"bdev=sda3\0"