Lines Matching +full:0 +full:x4500
18 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
27 #define CONFIG_SPL_TEXT_BASE 0xFFFFE000
29 #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
30 #define CONFIG_SPL_RELOC_STACK 0x00100000
31 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
32 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
33 #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
34 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0
62 #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */
63 #define CONFIG_SYS_MEMTEST_END 0x01ffffff
68 #define CONFIG_SYS_SPD_BUS_NUM 0
69 #define SPD_EEPROM_ADDRESS 0x52 /* I2C access */
71 #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
77 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
83 #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
84 #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
85 #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
87 #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
88 #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
89 #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
90 #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
92 #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
93 #define CONFIG_SYS_DDR_SR_CNTR 0x00000000
94 #define CONFIG_SYS_DDR_RCW_1 0x00000000
95 #define CONFIG_SYS_DDR_RCW_2 0x00000000
96 #define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
97 #define CONFIG_SYS_DDR_CONTROL_2 0x24401000
98 #define CONFIG_SYS_DDR_TIMING_4 0x00000001
99 #define CONFIG_SYS_DDR_TIMING_5 0x02401400
101 #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
102 #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
103 #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
104 #define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf
105 #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
106 #define CONFIG_SYS_DDR_MODE_1_800 0x00441420
107 #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
108 #define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
109 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
128 * 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable
129 * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M
130 * 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M
131 * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
132 * 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K
133 * 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K
134 * 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
135 * 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
136 * 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
137 * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M
146 #define CONFIG_SYS_NAND_BASE 0xff800000
164 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
165 | FTIM0_NAND_TWP(0x05) \
166 | FTIM0_NAND_TWCHT(0x02) \
167 | FTIM0_NAND_TWH(0x04))
168 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \
169 | FTIM1_NAND_TWBE(0x1E) \
170 | FTIM1_NAND_TRR(0x07) \
171 | FTIM1_NAND_TRP(0x05))
172 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
173 | FTIM2_NAND_TREH(0x04) \
174 | FTIM2_NAND_TWHRE(0x11))
175 #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
193 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
194 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* End of used area in RAM */
207 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
215 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
220 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
221 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
238 #define TSEC1_PHY_ADDR 0
244 #define TSEC1_PHYIDX 0
246 #define TSEC2_PHYIDX 0
256 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
257 #define CONFIG_ENV_SECT_SIZE 0x10000
258 #define CONFIG_ENV_SIZE 0x2000
264 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
265 #define CONFIG_ENV_SIZE 0x2000
274 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
319 "netdev=eth0\0" \
320 "uboot=" CONFIG_UBOOTPATH "\0" \
321 "loadaddr=1000000\0" \
322 "bootfile=uImage\0" \
323 "consoledev=ttyS0\0" \
324 "ramdiskaddr=2000000\0" \
325 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
326 "fdtaddr=1e00000\0" \
327 "fdtfile=bsc9131rdb.dtb\0" \
328 "bdev=sda1\0" \
329 "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
330 "bootm_size=0x37000000\0" \
332 "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \
336 "ext2load usb 0:4 $loadaddr $bootfile;" \
337 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
338 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
339 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \