| /openbmc/linux/arch/arm64/boot/dts/ti/ |
| H A D | k3-am62.dtsi | 54 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
55 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
56 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
57 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
58 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
59 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
60 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
61 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
62 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
63 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
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| H A D | k3-am62a.dtsi | 54 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
55 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
56 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
57 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
58 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
59 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
60 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
61 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
62 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
63 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
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| H A D | k3-am62p.dtsi | 53 ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
54 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
55 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
56 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
57 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
58 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
59 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
60 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
61 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
62 <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */
[all …]
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| H A D | k3-am62a-main.dtsi | 11 reg = <0x00 0x70000000 0x00 0x10000>;
14 ranges = <0x0 0x00 0x70000000 0x10000>;
19 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
20 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
21 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
22 <0x01 0x00000000 0x00 0x2000>, /* GICC */
23 <0x01 0x00010000 0x00 0x1000>, /* GICH */
24 <0x01 0x00020000 0x00 0x2000>; /* GICV */
38 reg = <0x00 0x01820000 0x00 0x10000>;
39 socionext,synquacer-pre-its = <0x1000000 0x400000>;
[all …]
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| H A D | k3-am62-main.dtsi | 11 reg = <0x00 0x70000000 0x00 0x10000>;
14 ranges = <0x0 0x00 0x70000000 0x10000>;
24 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
25 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
26 <0x00 0x01880000 0x00 0xc0000>, /* GICR */
27 <0x01 0x00000000 0x00 0x2000>, /* GICC */
28 <0x01 0x00010000 0x00 0x1000>, /* GICH */
29 <0x01 0x00020000 0x00 0x2000>; /* GICV */
38 reg = <0x00 0x01820000 0x00 0x10000>;
39 socionext,synquacer-pre-its = <0x1000000 0x400000>;
[all …]
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| /openbmc/u-boot/include/configs/ |
| H A D | peach-pit.h | 12 "bootm_size=0x10000000\0" \
13 "kernel_addr_r=0x22000000\0" \
14 "fdt_addr_r=0x23000000\0" \
15 "ramdisk_addr_r=0x23300000\0" \
16 "scriptaddr=0x30000000\0" \
17 "pxefile_addr_r=0x31000000\0"
23 #define CONFIG_SYS_SDRAM_BASE 0x20000000
24 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800)
27 #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
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| H A D | peach-pi.h | 12 "bootm_size=0x10000000\0" \
13 "kernel_addr_r=0x22000000\0" \
14 "fdt_addr_r=0x23000000\0" \
15 "ramdisk_addr_r=0x23300000\0" \
16 "scriptaddr=0x30000000\0" \
17 "pxefile_addr_r=0x31000000\0"
23 #define CONFIG_SYS_SDRAM_BASE 0x20000000
24 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800)
27 #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
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| /openbmc/linux/Documentation/devicetree/bindings/gpio/ |
| H A D | fujitsu,mb86s70-gpio.yaml | 45 reg = <0x31000000 0x10000>;
48 clocks = <&clk 0 2 1>;
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| /openbmc/linux/arch/arm/mach-lpc32xx/ |
| H A D | phy3250.c | 47 .slave_channels = &pl08x_slave_channels[0],
64 OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
65 OF_DEV_AUXDATA("nxp,lpc3220-slc", 0x20020000, "20020000.flash",
67 OF_DEV_AUXDATA("nxp,lpc3220-mlc", 0x200a8000, "200a8000.flash",
88 .atag_offset = 0x100,
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| H A D | lpc32xx.h | 17 * AHB 0 physical base addresses
19 #define LPC32XX_SLC_BASE 0x20020000
20 #define LPC32XX_SSP0_BASE 0x20084000
21 #define LPC32XX_SPI1_BASE 0x20088000
22 #define LPC32XX_SSP1_BASE 0x2008C000
23 #define LPC32XX_SPI2_BASE 0x20090000
24 #define LPC32XX_I2S0_BASE 0x20094000
25 #define LPC32XX_SD_BASE 0x20098000
26 #define LPC32XX_I2S1_BASE 0x2009C000
27 #define LPC32XX_MLC_BASE 0x200A8000
[all …]
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| /openbmc/u-boot/arch/arm/include/asm/arch-lpc32xx/ |
| H A D | cpu.h | 12 #define SLC_NAND_BASE 0x20020000 /* SLC NAND Flash registers base */
13 #define SSP0_BASE 0x20084000 /* SSP0 registers base */
14 #define SD_CARD_BASE 0x20098000 /* SD card interface registers base */
15 #define MLC_NAND_BASE 0x200A8000 /* MLC NAND Flash registers base */
16 #define DMA_BASE 0x31000000 /* DMA controller registers base */
17 #define USB_BASE 0x31020000 /* USB registers base */
18 #define LCD_BASE 0x31040000 /* LCD registers base */
19 #define ETHERNET_BASE 0x31060000 /* Ethernet registers base */
20 #define EMC_BASE 0x31080000 /* EMC configuration registers base */
23 #define CLK_PM_BASE 0x40004000 /* System control registers base */
[all …]
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| /openbmc/linux/drivers/soc/fsl/qe/ |
| H A D | qmc.c | 25 #define SCC_GSMRL 0x00
28 #define SCC_GSMRL_MODE_QMC (0x0A << 0)
31 #define SCC_GSMRH 0x04
38 #define SCC_SCCE 0x10
42 #define SCC_SCCE_GOV (1 << 0)
45 #define SCC_SCCM 0x14
47 #define QMC_GBL_MCBASE 0x00
49 #define QMC_GBL_QMCSTATE 0x04
51 #define QMC_GBL_MRBLR 0x06
53 #define QMC_GBL_TX_S_PTR 0x08
[all …]
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| /openbmc/qemu/include/hw/arm/ |
| H A D | fsl-imx7.h | 100 FSL_IMX7_MMDC_ADDR = 0x80000000,
103 FSL_IMX7_QSPI1_MEM_ADDR = 0x60000000,
106 FSL_IMX7_PCIE1_MEM_ADDR = 0x40000000,
109 FSL_IMX7_QSPI1_RX_BUF_ADDR = 0x34000000,
113 FSL_IMX7_PCIE_REG_ADDR = 0x33800000,
116 FSL_IMX7_DMA_APBH_ADDR = 0x33000000,
117 FSL_IMX7_DMA_APBH_SIZE = 0x8000,
120 FSL_IMX7_GPV6_ADDR = 0x32600000,
121 FSL_IMX7_GPV5_ADDR = 0x32500000,
122 FSL_IMX7_GPV4_ADDR = 0x32400000,
[all …]
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| /openbmc/linux/Documentation/devicetree/bindings/mmc/ |
| H A D | arasan,sdhci.yaml | 137 enum: [0, 1]
158 enum: [0, 1, 2]
159 default: 0
185 reg = <0xe0100000 0x1000>;
189 interrupts = <0 24 4>;
195 reg = <0xe2800000 0x1000>;
199 interrupts = <0 24 4>;
210 reg = <0xfe330000 0x10000>;
220 #clock-cells = <0>;
227 interrupts = <0 48 4>;
[all …]
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| /openbmc/linux/arch/arm/boot/dts/nxp/lpc/ |
| H A D | lpc32xx.dtsi | 20 #size-cells = <0>;
22 cpu@0 {
25 reg = <0x0>;
32 #clock-cells = <0>;
39 #clock-cells = <0>;
49 ranges = <0x00000000 0x00000000 0x10000000>,
50 <0x20000000 0x20000000 0x30000000>,
51 <0xe0000000 0xe0000000 0x04000000>;
55 reg = <0x08000000 0x20000>;
59 ranges = <0x00000000 0x08000000 0x20000>;
[all …]
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| /openbmc/u-boot/arch/arm/include/asm/arch-mx7/ |
| H A D | imx-regs.h | 11 #define ROM_SW_INFO_ADDR 0x000001E8
12 #define ROMCP_ARB_BASE_ADDR 0x00000000
13 #define ROMCP_ARB_END_ADDR 0x00017FFF
15 #define CAAM_ARB_BASE_ADDR 0x00100000
16 #define CAAM_ARB_END_ADDR 0x00107FFF
17 #define GIC400_ARB_BASE_ADDR 0x31000000
18 #define GIC400_ARB_END_ADDR 0x31007FFF
19 #define APBH_DMA_ARB_BASE_ADDR 0x33000000
20 #define APBH_DMA_ARB_END_ADDR 0x33007FFF
21 #define M4_BOOTROM_BASE_ADDR 0x00180000
[all …]
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| /openbmc/linux/arch/arm64/include/asm/ |
| H A D | insn.h | 18 AARCH64_INSN_HINT_NOP = 0x0 << 5,
19 AARCH64_INSN_HINT_YIELD = 0x1 << 5,
20 AARCH64_INSN_HINT_WFE = 0x2 << 5,
21 AARCH64_INSN_HINT_WFI = 0x3 << 5,
22 AARCH64_INSN_HINT_SEV = 0x4 << 5,
23 AARCH64_INSN_HINT_SEVL = 0x5 << 5,
25 AARCH64_INSN_HINT_XPACLRI = 0x07 << 5,
26 AARCH64_INSN_HINT_PACIA_1716 = 0x08 << 5,
27 AARCH64_INSN_HINT_PACIB_1716 = 0x0A << 5,
28 AARCH64_INSN_HINT_AUTIA_1716 = 0x0C << 5,
[all …]
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| /openbmc/linux/arch/hexagon/kernel/ |
| H A D | vm_init_segtable.S | 16 * Start with mapping PA=0 to both VA=0x0 and VA=0xc000000 as 16MB large pages.
46 /* VA 0x00000000 */
59 /* VA 0x40000000 */
68 /* VA 0x80000000 */
74 /*0xa8*/.word X,X,X,X
77 /*0xa9*/.word BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000),BKPG_IO(0xa9000000)
79 /*0xa9*/.word X,X,X,X
81 /*0xaa*/.word X,X,X,X
82 /*0xab*/.word X,X,X,X
83 /*0xac*/.word X,X,X,X
[all …]
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| /openbmc/u-boot/drivers/misc/ |
| H A D | dp_mcu_firmware.h | 6 0xa0000080, 0xa0000080, 0xa0000080, 0xa00029a8,
7 0xa0002a08, 0xa0002a68, 0xa0000080, 0xa0000080,
8 0xa0000080, 0xa0000080, 0xa0000080, 0xa0000080,
9 0xa0000080, 0xa0000080, 0xa0000080, 0xa0000080,
10 0xa0000080, 0xa0000080, 0xa0000080, 0xa0000080,
11 0xa0000080, 0xa0000080, 0xa0000080, 0xa0000080,
12 0xa0000080, 0xa0000080, 0xa0000080, 0xa0000080,
13 0xa0000080, 0xa0000080, 0xa0000080, 0xa0000080,
14 0x2a801e6e, 0x5694b000, 0x29201800, 0x55290000,
15 0x54c00104, 0x54e00000, 0x05093800, 0xdc080000,
[all …]
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| /openbmc/linux/crypto/ |
| H A D | aes_generic.c | 67 0xa56363c6, 0x847c7cf8, 0x997777ee, 0x8d7b7bf6,
68 0x0df2f2ff, 0xbd6b6bd6, 0xb16f6fde, 0x54c5c591,
69 0x50303060, 0x03010102, 0xa96767ce, 0x7d2b2b56,
70 0x19fefee7, 0x62d7d7b5, 0xe6abab4d, 0x9a7676ec,
71 0x45caca8f, 0x9d82821f, 0x40c9c989, 0x877d7dfa,
72 0x15fafaef, 0xeb5959b2, 0xc947478e, 0x0bf0f0fb,
73 0xecadad41, 0x67d4d4b3, 0xfda2a25f, 0xeaafaf45,
74 0xbf9c9c23, 0xf7a4a453, 0x967272e4, 0x5bc0c09b,
75 0xc2b7b775, 0x1cfdfde1, 0xae93933d, 0x6a26264c,
76 0x5a36366c, 0x413f3f7e, 0x02f7f7f5, 0x4fcccc83,
[all …]
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| /openbmc/linux/drivers/media/i2c/s5c73m3/ |
| H A D | s5c73m3-core.c | 125 u8 buf[4] = { addr >> 8, addr & 0xff, data >> 8, data & 0xff }; in s5c73m3_i2c_write()
129 v4l_dbg(4, s5c73m3_dbg, client, "%s: addr 0x%04x, data 0x%04x\n", in s5c73m3_i2c_write()
133 return 0; in s5c73m3_i2c_write()
135 return ret < 0 ? ret : -EREMOTEIO; in s5c73m3_i2c_write()
141 u8 rbuf[2], wbuf[2] = { addr >> 8, addr & 0xff }; in s5c73m3_i2c_read()
145 .flags = 0, in s5c73m3_i2c_read()
163 "%s: addr: 0x%04x, data: 0x%04x\n", in s5c73m3_i2c_read()
165 return 0; in s5c73m3_i2c_read()
170 return ret >= 0 ? -EREMOTEIO : ret; in s5c73m3_i2c_read()
178 if ((addr ^ state->i2c_write_address) & 0xffff0000) { in s5c73m3_write()
[all …]
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| /openbmc/u-boot/cmd/aspeed/ |
| H A D | dptest.c | 18 #define MAINVER 0
33 #define DBG_ERR 0x00000001 /* DBG_ERROR */
34 #define DBG_NOR 0x00000002 /* DBG_NORMAL */
35 #define DBG_A_NOR 0x00000004 /* DBG_AUTO_NORMAL */
36 #define DBG_A_TEST 0x00000008 /* DBG_AUTO_TEST */
37 #define DBG_A_SUB 0x00000010 /* DBG_AUTO_SUBFUNS */
38 #define DBG_A_EDID 0x00000020 /* DBG_AUTO_EDID */
39 #define DBG_INF 0x00000040 /* DBG_INFORMATION */
40 #define DBG_STAGE 0x00000040 /* DBG_STAGE */
41 #define DBG_AUX_R 0x00001000 /* DBG_AUX_R_VALUE */
[all …]
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| /openbmc/linux/arch/arm64/boot/dts/freescale/ |
| H A D | imx8mq.dtsi | 47 #clock-cells = <0>;
54 #clock-cells = <0>;
61 #clock-cells = <0>;
68 #clock-cells = <0>;
75 #clock-cells = <0>;
82 #clock-cells = <0>;
89 #clock-cells = <0>;
96 #clock-cells = <0>;
103 #size-cells = <0>;
105 A53_0: cpu@0 {
[all …]
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| /openbmc/qemu/tcg/aarch64/ |
| H A D | tcg-target.c.inc | 20 QEMU_BUILD_BUG_ON(TCG_TYPE_I32 != 0 || TCG_TYPE_I64 != 1);
71 tcg_debug_assert(slot >= 0 && slot <= 1);
87 if (offset == sextract64(offset, 0, 26)) {
90 *src_rw = deposit32(*src_rw, 0, 26, offset);
101 if (offset == sextract64(offset, 0, 19)) {
113 if (offset == sextract64(offset, 0, 14)) {
123 tcg_debug_assert(addend == 0);
137 #define TCG_CT_CONST_AIMM 0x100
138 #define TCG_CT_CONST_LIMM 0x200
139 #define TCG_CT_CONST_ZERO 0x400
[all …]
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| /openbmc/linux/drivers/net/ethernet/broadcom/bnx2x/ |
| H A D | bnx2x_hsi.h | 17 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
23 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
24 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
25 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
31 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
32 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0
33 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
42 #define PIN_CFG_NA 0x00000000
43 #define PIN_CFG_GPIO0_P0 0x00000001
44 #define PIN_CFG_GPIO1_P0 0x00000002
[all …]
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