1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 2b1d902a9SAdrian Alonso /* 3b1d902a9SAdrian Alonso * Copyright (C) 2015 Freescale Semiconductor, Inc. All Rights Reserved. 4b1d902a9SAdrian Alonso */ 5b1d902a9SAdrian Alonso 6b1d902a9SAdrian Alonso #ifndef __ASM_ARCH_MX7_IMX_REGS_H__ 7b1d902a9SAdrian Alonso #define __ASM_ARCH_MX7_IMX_REGS_H__ 8b1d902a9SAdrian Alonso 9b1d902a9SAdrian Alonso #define ARCH_MXC 10b1d902a9SAdrian Alonso 11b1d902a9SAdrian Alonso #define ROM_SW_INFO_ADDR 0x000001E8 12b1d902a9SAdrian Alonso #define ROMCP_ARB_BASE_ADDR 0x00000000 13b1d902a9SAdrian Alonso #define ROMCP_ARB_END_ADDR 0x00017FFF 14b1d902a9SAdrian Alonso #define BOOT_ROM_BASE_ADDR ROMCP_ARB_BASE_ADDR 15b1d902a9SAdrian Alonso #define CAAM_ARB_BASE_ADDR 0x00100000 16b1d902a9SAdrian Alonso #define CAAM_ARB_END_ADDR 0x00107FFF 17b1d902a9SAdrian Alonso #define GIC400_ARB_BASE_ADDR 0x31000000 18b1d902a9SAdrian Alonso #define GIC400_ARB_END_ADDR 0x31007FFF 19b1d902a9SAdrian Alonso #define APBH_DMA_ARB_BASE_ADDR 0x33000000 20b1d902a9SAdrian Alonso #define APBH_DMA_ARB_END_ADDR 0x33007FFF 21b1d902a9SAdrian Alonso #define M4_BOOTROM_BASE_ADDR 0x00180000 22b1d902a9SAdrian Alonso 23b1d902a9SAdrian Alonso #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR 24b1d902a9SAdrian Alonso #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000) 25b1d902a9SAdrian Alonso #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000) 26b1d902a9SAdrian Alonso 27b1d902a9SAdrian Alonso /* GPV - PL301 configuration ports */ 28b1d902a9SAdrian Alonso #define GPV0_BASE_ADDR 0x32000000 29b1d902a9SAdrian Alonso #define GPV1_BASE_ADDR 0x32100000 30b1d902a9SAdrian Alonso #define GPV2_BASE_ADDR 0x32200000 31b1d902a9SAdrian Alonso #define GPV3_BASE_ADDR 0x32300000 32b1d902a9SAdrian Alonso #define GPV4_BASE_ADDR 0x32400000 33b1d902a9SAdrian Alonso #define GPV5_BASE_ADDR 0x32500000 34b1d902a9SAdrian Alonso #define GPV6_BASE_ADDR 0x32600000 35b1d902a9SAdrian Alonso #define GPV7_BASE_ADDR 0x32700000 36b1d902a9SAdrian Alonso 37b1d902a9SAdrian Alonso #define OCRAM_ARB_BASE_ADDR 0x00900000 38b1d902a9SAdrian Alonso #define OCRAM_ARB_END_ADDR 0x0091FFFF 39b1d902a9SAdrian Alonso #define OCRAM_EPDC_BASE_ADDR 0x00920000 40b1d902a9SAdrian Alonso #define OCRAM_EPDC_END_ADDR 0x0093FFFF 41b1d902a9SAdrian Alonso #define OCRAM_PXP_BASE_ADDR 0x00940000 42b1d902a9SAdrian Alonso #define OCRAM_PXP_END_ADDR 0x00947FFF 43b1d902a9SAdrian Alonso #define IRAM_BASE_ADDR OCRAM_ARB_BASE_ADDR 44b1d902a9SAdrian Alonso #define IRAM_SIZE 0x00020000 45b1d902a9SAdrian Alonso 46b1d902a9SAdrian Alonso #define AIPS1_ARB_BASE_ADDR 0x30000000 47b1d902a9SAdrian Alonso #define AIPS1_ARB_END_ADDR 0x303FFFFF 48b1d902a9SAdrian Alonso #define AIPS2_ARB_BASE_ADDR 0x30400000 49b1d902a9SAdrian Alonso #define AIPS2_ARB_END_ADDR 0x307FFFFF 50b1d902a9SAdrian Alonso #define AIPS3_ARB_BASE_ADDR 0x30800000 51b1d902a9SAdrian Alonso #define AIPS3_ARB_END_ADDR 0x30BFFFFF 52b1d902a9SAdrian Alonso 53b1d902a9SAdrian Alonso #define WEIM_ARB_BASE_ADDR 0x28000000 54b1d902a9SAdrian Alonso #define WEIM_ARB_END_ADDR 0x2FFFFFFF 55b1d902a9SAdrian Alonso 56b1d902a9SAdrian Alonso #define QSPI0_ARB_BASE_ADDR 0x60000000 57b1d902a9SAdrian Alonso #define QSPI0_ARB_END_ADDR 0x6FFFFFFF 58b1d902a9SAdrian Alonso #define PCIE_ARB_BASE_ADDR 0x40000000 59b1d902a9SAdrian Alonso #define PCIE_ARB_END_ADDR 0x4FFFFFFF 60b1d902a9SAdrian Alonso #define PCIE_REG_BASE_ADDR 0x33800000 61b1d902a9SAdrian Alonso #define PCIE_REG_END_ADDR 0x33803FFF 62b1d902a9SAdrian Alonso 63b1d902a9SAdrian Alonso #define MMDC0_ARB_BASE_ADDR 0x80000000 64b1d902a9SAdrian Alonso #define MMDC0_ARB_END_ADDR 0xBFFFFFFF 65b1d902a9SAdrian Alonso #define MMDC1_ARB_BASE_ADDR 0xC0000000 66b1d902a9SAdrian Alonso #define MMDC1_ARB_END_ADDR 0xFFFFFFFF 67b1d902a9SAdrian Alonso 68b1d902a9SAdrian Alonso /* Cortex-A9 MPCore private memory region */ 69b1d902a9SAdrian Alonso #define ARM_PERIPHBASE 0x31000000 70b1d902a9SAdrian Alonso #define SCU_BASE_ADDR ARM_PERIPHBASE 71b1d902a9SAdrian Alonso #define GLOBAL_TIMER_BASE_ADDR (ARM_PERIPHBASE + 0x0200) 72b1d902a9SAdrian Alonso #define PRIVATE_TIMERS_WD_BASE_ADDR (ARM_PERIPHBASE + 0x0600) 73b1d902a9SAdrian Alonso 74b1d902a9SAdrian Alonso 75b1d902a9SAdrian Alonso /* Defines for Blocks connected via AIPS (SkyBlue) */ 76b1d902a9SAdrian Alonso #define AIPS_TZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR 77b1d902a9SAdrian Alonso #define AIPS_TZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR 78b1d902a9SAdrian Alonso #define AIPS_TZ3_BASE_ADDR AIPS3_ARB_BASE_ADDR 79b1d902a9SAdrian Alonso 80b1d902a9SAdrian Alonso /* DAP base-address */ 81b1d902a9SAdrian Alonso #define ARM_IPS_BASE_ADDR AIPS1_ARB_BASE_ADDR 82b1d902a9SAdrian Alonso 83b1d902a9SAdrian Alonso /* AIPS_TZ#1- On Platform */ 84b1d902a9SAdrian Alonso #define AIPS1_ON_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x1F0000) 85b1d902a9SAdrian Alonso /* AIPS_TZ#1- Off Platform */ 86b1d902a9SAdrian Alonso #define AIPS1_OFF_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x200000) 87b1d902a9SAdrian Alonso 88b1d902a9SAdrian Alonso #define GPIO1_BASE_ADDR AIPS1_OFF_BASE_ADDR 89b1d902a9SAdrian Alonso #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x10000) 90b1d902a9SAdrian Alonso #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x20000) 91b1d902a9SAdrian Alonso #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x30000) 92b1d902a9SAdrian Alonso #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x40000) 93b1d902a9SAdrian Alonso #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x50000) 94b1d902a9SAdrian Alonso #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x60000) 95b1d902a9SAdrian Alonso #define IOMUXC_LPSR_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x70000) 96b1d902a9SAdrian Alonso #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x80000) 97b1d902a9SAdrian Alonso #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x90000) 98b1d902a9SAdrian Alonso #define WDOG3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xA0000) 99b1d902a9SAdrian Alonso #define WDOG4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xB0000) 100b1d902a9SAdrian Alonso #define IOMUXC_LPSR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xC0000) 101b1d902a9SAdrian Alonso #define GPT_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xD0000) 102b1d902a9SAdrian Alonso #define GPT1_BASE_ADDR GPT_IPS_BASE_ADDR 103b1d902a9SAdrian Alonso #define GPT2_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xE0000) 104b1d902a9SAdrian Alonso #define GPT3_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xF0000) 105b1d902a9SAdrian Alonso #define GPT4_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x100000) 106b1d902a9SAdrian Alonso #define ROMCP_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x110000) 107b1d902a9SAdrian Alonso #define KPP_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x120000) 108b1d902a9SAdrian Alonso #define IOMUXC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x130000) 109b1d902a9SAdrian Alonso #define IOMUXC_BASE_ADDR IOMUXC_IPS_BASE_ADDR 110b1d902a9SAdrian Alonso #define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x140000) 111b1d902a9SAdrian Alonso #define OCOTP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x150000) 112b1d902a9SAdrian Alonso #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x160000) 113b1d902a9SAdrian Alonso #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x170000) 114b1d902a9SAdrian Alonso #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x180000) 115b1d902a9SAdrian Alonso #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x190000) 116b1d902a9SAdrian Alonso #define GPC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1A0000) 117b1d902a9SAdrian Alonso #define SEMA41_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1B0000) 118b1d902a9SAdrian Alonso #define SEMA42_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1C0000) 119b1d902a9SAdrian Alonso #define RDC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1D0000) 120b1d902a9SAdrian Alonso #define CSU_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1E0000) 121b1d902a9SAdrian Alonso 122b1d902a9SAdrian Alonso /* AIPS_TZ#2- On Platform */ 123b1d902a9SAdrian Alonso #define AIPS2_ON_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x1F0000) 124b1d902a9SAdrian Alonso /* AIPS_TZ#2- Off Platform */ 125b1d902a9SAdrian Alonso #define AIPS2_OFF_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x200000) 126b1d902a9SAdrian Alonso #define ADC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x10000) 127b1d902a9SAdrian Alonso #define ADC2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x20000) 128b1d902a9SAdrian Alonso #define ECSPI4_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x30000) 129b1d902a9SAdrian Alonso #define FTM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x40000) 130b1d902a9SAdrian Alonso #define FTM2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x50000) 131b1d902a9SAdrian Alonso #define PWM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x60000) 132b1d902a9SAdrian Alonso #define PWM2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x70000) 133b1d902a9SAdrian Alonso #define PWM3_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x80000) 134b1d902a9SAdrian Alonso #define PWM4_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x90000) 135b1d902a9SAdrian Alonso #define SYSCNT_RD_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xA0000) 136b1d902a9SAdrian Alonso #define SYSCNT_CMP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xB0000) 137b1d902a9SAdrian Alonso #define SYSCNT_CTRL_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xC0000) 138b1d902a9SAdrian Alonso #define PCIE_PHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xD0000) 139b1d902a9SAdrian Alonso #define EPDC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xF0000) 140b1d902a9SAdrian Alonso #define EPDC_BASE_ADDR EPDC_IPS_BASE_ADDR 141b1d902a9SAdrian Alonso #define EPXP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x100000) 142b1d902a9SAdrian Alonso #define CSI1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x110000) 143b1d902a9SAdrian Alonso #define ELCDIF1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x130000) 144b1d902a9SAdrian Alonso #define MIPI_CSI2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x150000) 145b1d902a9SAdrian Alonso #define MIPI_DSI_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x160000) 146b1d902a9SAdrian Alonso #define IP2APB_TZASC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x180000) 147b1d902a9SAdrian Alonso #define DDRPHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x190000) 148b1d902a9SAdrian Alonso #define DDRC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1A0000) 149b1d902a9SAdrian Alonso #define IP2APB_PERFMON1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1C0000) 150b1d902a9SAdrian Alonso #define IP2APB_PERFMON2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1D0000) 151b1d902a9SAdrian Alonso #define IP2APB_AXIMON_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1E0000) 152b1d902a9SAdrian Alonso #define QOSC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1F0000) 153b1d902a9SAdrian Alonso 154b1d902a9SAdrian Alonso /* AIPS_TZ#3 - Global enable (0) */ 155b1d902a9SAdrian Alonso #define ECSPI1_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x20000) 156b1d902a9SAdrian Alonso #define ECSPI2_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x30000) 157b1d902a9SAdrian Alonso #define ECSPI3_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x40000) 158b1d902a9SAdrian Alonso #define UART1_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x60000) 159b1d902a9SAdrian Alonso #define UART3_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x80000) 160b1d902a9SAdrian Alonso #define UART2_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x90000) 161b1d902a9SAdrian Alonso #define SAI1_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xA0000) 162b1d902a9SAdrian Alonso #define SAI2_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xB0000) 163b1d902a9SAdrian Alonso #define SAI3_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xC0000) 164b1d902a9SAdrian Alonso #define SPBA_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xF0000) 165b1d902a9SAdrian Alonso #define CAAM_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x100000) 166b1d902a9SAdrian Alonso 167b1d902a9SAdrian Alonso /* AIPS_TZ#3- On Platform */ 168b1d902a9SAdrian Alonso #define AIPS3_ON_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x1F0000) 169b1d902a9SAdrian Alonso /* AIPS_TZ#3- Off Platform */ 170b1d902a9SAdrian Alonso #define AIPS3_OFF_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x200000) 171b1d902a9SAdrian Alonso #define CAN1_IPS_BASE_ADDR AIPS3_OFF_BASE_ADDR 172b1d902a9SAdrian Alonso #define CAN2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x10000) 173b1d902a9SAdrian Alonso #define I2C1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x20000) 174b1d902a9SAdrian Alonso #define I2C2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x30000) 175b1d902a9SAdrian Alonso #define I2C3_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x40000) 176b1d902a9SAdrian Alonso #define I2C4_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x50000) 177b1d902a9SAdrian Alonso #define UART4_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x60000) 178b1d902a9SAdrian Alonso #define UART5_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x70000) 179b1d902a9SAdrian Alonso #define UART6_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x80000) 180b1d902a9SAdrian Alonso #define UART7_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x90000) 181b1d902a9SAdrian Alonso #define MUCPU_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xA0000) 182b1d902a9SAdrian Alonso #define MUDSP_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xB0000) 183b1d902a9SAdrian Alonso #define HS_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xC0000) 184b1d902a9SAdrian Alonso #define USBOH2_PL301_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xD0000) 185b1d902a9SAdrian Alonso #define USBOTG1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x110000) 186b1d902a9SAdrian Alonso #define USBOTG2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x120000) 187b1d902a9SAdrian Alonso #define USBHSIC_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x130000) 188b1d902a9SAdrian Alonso #define USDHC1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x140000) 189b1d902a9SAdrian Alonso #define USDHC2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x150000) 190b1d902a9SAdrian Alonso #define USDHC3_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x160000) 191b1d902a9SAdrian Alonso #define EMVSIM1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x190000) 192b1d902a9SAdrian Alonso #define EMVSIM2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1A0000) 193b1d902a9SAdrian Alonso #define SIM1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x190000) 194b1d902a9SAdrian Alonso #define SIM2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1A0000) 195b1d902a9SAdrian Alonso #define QSPI1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1B0000) 196b1d902a9SAdrian Alonso #define WEIM_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1C0000) 197b1d902a9SAdrian Alonso #define SDMA_PORT_IPS_HOST_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1D0000) 198b1d902a9SAdrian Alonso #define ENET_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1E0000) 199b1d902a9SAdrian Alonso #define ENET2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1F0000) 200b1d902a9SAdrian Alonso 201b1d902a9SAdrian Alonso #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR 202b1d902a9SAdrian Alonso #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR 203b1d902a9SAdrian Alonso #define AIPS3_BASE_ADDR AIPS3_ON_BASE_ADDR 204b1d902a9SAdrian Alonso 205b1d902a9SAdrian Alonso #define SDMA_IPS_HOST_BASE_ADDR SDMA_PORT_IPS_HOST_BASE_ADDR 206b1d902a9SAdrian Alonso #define SDMA_IPS_HOST_IPS_BASE_ADDR SDMA_PORT_IPS_HOST_BASE_ADDR 207b1d902a9SAdrian Alonso 208b1d902a9SAdrian Alonso #define SCTR_BASE_ADDR SYSCNT_CTRL_IPS_BASE_ADDR 209b1d902a9SAdrian Alonso #define DEBUG_MONITOR_BASE_ADDR IP2APB_AXIMON_IPS_BASE_ADDR 210b1d902a9SAdrian Alonso 211b1d902a9SAdrian Alonso #define USB_BASE_ADDR USBOTG1_IPS_BASE_ADDR 212af013592SPeng Fan #define SEMAPHORE1_BASE_ADDR SEMA41_IPS_BASE_ADDR 213af013592SPeng Fan #define SEMAPHORE2_BASE_ADDR SEMA42_IPS_BASE_ADDR 214af013592SPeng Fan #define RDC_BASE_ADDR RDC_IPS_BASE_ADDR 215b1d902a9SAdrian Alonso 216b1d902a9SAdrian Alonso #define FEC_QUIRK_ENET_MAC 217b1d902a9SAdrian Alonso #define SNVS_LPGPR 0x68 218e99d7193SAlex Porosanu #define CONFIG_SYS_FSL_SEC_OFFSET 0 219e99d7193SAlex Porosanu #define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ 220e99d7193SAlex Porosanu CONFIG_SYS_FSL_SEC_OFFSET) 221e99d7193SAlex Porosanu #define CONFIG_SYS_FSL_JR0_OFFSET 0x1000 222e99d7193SAlex Porosanu #define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \ 223e99d7193SAlex Porosanu CONFIG_SYS_FSL_JR0_OFFSET) 224e99d7193SAlex Porosanu #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 225b1d902a9SAdrian Alonso #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) 226552a848eSStefano Babic #include <asm/mach-imx/regs-lcdif.h> 227b1d902a9SAdrian Alonso #include <asm/types.h> 228b1d902a9SAdrian Alonso 229b1d902a9SAdrian Alonso extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); 230b1d902a9SAdrian Alonso 231b1d902a9SAdrian Alonso /* System Reset Controller (SRC) */ 232b1d902a9SAdrian Alonso struct src { 233b1d902a9SAdrian Alonso u32 scr; 234b1d902a9SAdrian Alonso u32 a7rcr0; 235b1d902a9SAdrian Alonso u32 a7rcr1; 236b1d902a9SAdrian Alonso u32 m4rcr; 237b1d902a9SAdrian Alonso u32 reserved1; 238b1d902a9SAdrian Alonso u32 ercr; 239b1d902a9SAdrian Alonso u32 reserved2; 240b1d902a9SAdrian Alonso u32 hsicphy_rcr; 241b1d902a9SAdrian Alonso u32 usbophy1_rcr; 242b1d902a9SAdrian Alonso u32 usbophy2_rcr; 243b1d902a9SAdrian Alonso u32 mipiphy_rcr; 244b1d902a9SAdrian Alonso u32 pciephy_rcr; 245b1d902a9SAdrian Alonso u32 reserved3[10]; 246b1d902a9SAdrian Alonso u32 sbmr1; 247b1d902a9SAdrian Alonso u32 srsr; 248b1d902a9SAdrian Alonso u32 reserved4[2]; 249b1d902a9SAdrian Alonso u32 sisr; 250b1d902a9SAdrian Alonso u32 simr; 251b1d902a9SAdrian Alonso u32 sbmr2; 252b1d902a9SAdrian Alonso u32 gpr1; 253b1d902a9SAdrian Alonso u32 gpr2; 254b1d902a9SAdrian Alonso u32 gpr3; 255b1d902a9SAdrian Alonso u32 gpr4; 256b1d902a9SAdrian Alonso u32 gpr5; 257b1d902a9SAdrian Alonso u32 gpr6; 258b1d902a9SAdrian Alonso u32 gpr7; 259b1d902a9SAdrian Alonso u32 gpr8; 260b1d902a9SAdrian Alonso u32 gpr9; 261b1d902a9SAdrian Alonso u32 gpr10; 262b1d902a9SAdrian Alonso u32 reserved5[985]; 263b1d902a9SAdrian Alonso u32 ddrc_rcr; 264b1d902a9SAdrian Alonso }; 265b1d902a9SAdrian Alonso 26603858f8eSEran Matityahu #define src_base ((struct src *)SRC_BASE_ADDR) 26703858f8eSEran Matityahu 2688cf22313SPeng Fan #define SRC_M4_REG_OFFSET 0xC 2698cf22313SPeng Fan #define SRC_M4C_NON_SCLR_RST_OFFSET 0 2708cf22313SPeng Fan #define SRC_M4C_NON_SCLR_RST_MASK BIT(0) 2718cf22313SPeng Fan #define SRC_M4_ENABLE_OFFSET 3 2728cf22313SPeng Fan #define SRC_M4_ENABLE_MASK BIT(3) 2738cf22313SPeng Fan 274258bad41SUri Mashiach #define SRC_DDRC_RCR_DDRC_CORE_RST_OFFSET 1 275258bad41SUri Mashiach #define SRC_DDRC_RCR_DDRC_CORE_RST_MASK (1 << 1) 27683703a1cSPeng Fan 277b1d902a9SAdrian Alonso /* GPR0 Bit Fields */ 278b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK 0x1u 279b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT 0 280b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK 0x2u 281b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT 1 282b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK 0x4u 283b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT 2 284b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK 0x8u 285b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT 3 286b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK 0x10u 287b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT 4 288b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK 0x20u 289b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT 5 290b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK 0x40u 291b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT 6 292d9699de8SPeng Fan #define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK (3 << 7) 293d9699de8SPeng Fan #define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_SHIFT 7 294b1d902a9SAdrian Alonso /* GPR1 Bit Fields */ 295b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_MASK 0x1u 296b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_SHIFT 0 297b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK 0x6u 298b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT 1 299b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK) 300b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_MASK 0x8u 301b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_SHIFT 3 302b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK 0x30u 303b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_SHIFT 4 304b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK) 305b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_MASK 0x40u 306b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_SHIFT 6 307b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK 0x180u 308b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_SHIFT 7 309b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK) 310b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_MASK 0x200u 311b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_SHIFT 9 312b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK 0xC00u 313b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_SHIFT 10 314b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_SHIFT))&IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK) 315b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_IRQ_MASK 0x1000u 316b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_IRQ_SHIFT 12 317b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK 0x2000u 318b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT 13 319b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK 0x4000u 320b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_SHIFT 14 321b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_MASK 0x8000u 322b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_SHIFT 15 323b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_MASK 0x10000u 324b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_SHIFT 16 325b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK 0x20000u 326b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_SHIFT 17 327b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK 0x40000u 328b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_SHIFT 18 329b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_MASK 0x400000u 330b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_SHIFT 22 331b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_MASK 0x800000u 332b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_SHIFT 23 333b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK 0x30000000u 334b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT 28 335b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_DBG_ACK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR1_GPR_DBG_ACK_SHIFT))&IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK) 336b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK 0x40000000u 337b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_SHIFT 30 338b1d902a9SAdrian Alonso /* GPR2 Bit Fields */ 339b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_MASK 0x1u 340b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_SHIFT 0 341b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_MASK 0x2u 342b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_SHIFT 1 343b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_MASK 0x4u 344b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_SHIFT 2 345b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_MASK 0x8u 346b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_SHIFT 3 347b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_MASK 0x10u 348b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_SHIFT 4 349b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_MASK 0x20u 350b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_SHIFT 5 351b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_MASK 0x40u 352b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_SHIFT 6 353b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_MASK 0x80u 354b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_SHIFT 7 355b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_MASK 0x100u 356b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_SHIFT 8 357b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_MASK 0x200u 358b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_SHIFT 9 359b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_MASK 0x400u 360b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_SHIFT 10 361b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_MASK 0x800u 362b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_SHIFT 11 363b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_MASK 0x1000u 364b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_SHIFT 12 365b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_MASK 0x2000u 366b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_SHIFT 13 367b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_MASK 0x4000u 368b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_SHIFT 14 369b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_MASK 0x8000u 370b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_SHIFT 15 371b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK 0xFF0000u 372b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_SHIFT 16 373b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_SHIFT))&IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK) 374b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_MASK 0x1000000u 375b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_SHIFT 24 376b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MQS_EN_MASK 0x2000000u 377b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MQS_EN_SHIFT 25 378b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_MASK 0x4000000u 379b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_SHIFT 26 380b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_MASK 0x8000000u 381b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_SHIFT 27 382b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_MASK 0x10000000u 383b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_SHIFT 28 384b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_MASK 0x20000000u 385b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_SHIFT 29 386b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_MASK 0x40000000u 387b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_SHIFT 30 388b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_MASK 0x80000000u 389b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_SHIFT 31 390b1d902a9SAdrian Alonso /* GPR3 Bit Fields */ 391b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_MASK 0x1u 392b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_SHIFT 0 393b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_MASK 0x2u 394b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_SHIFT 1 395b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_MASK 0x4u 396b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_SHIFT 2 397b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_MASK 0x8u 398b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_SHIFT 3 399b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_MASK 0x10u 400b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_SHIFT 4 401b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_MASK 0x20u 402b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_SHIFT 5 403b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_MASK 0x40u 404b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_SHIFT 6 405b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_MASK 0x80u 406b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_SHIFT 7 407b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_MASK 0x100u 408b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_SHIFT 8 409b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_MASK 0x200u 410b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_SHIFT 9 411b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_MASK 0x400u 412b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_SHIFT 10 413b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_MASK 0x800u 414b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_SHIFT 11 415b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_MASK 0x1000u 416b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_SHIFT 12 417b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_MASK 0x2000u 418b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_SHIFT 13 419b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_MASK 0x4000u 420b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_SHIFT 14 421b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_MASK 0x8000u 422b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_SHIFT 15 423b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_MASK 0x10000u 424b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_SHIFT 16 425b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_MASK 0x20000u 426b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_SHIFT 17 427b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_MASK 0x40000u 428b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_SHIFT 18 429b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_MASK 0x80000u 430b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_SHIFT 19 431b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_MASK 0x100000u 432b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_SHIFT 20 433b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_MASK 0x200000u 434b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_SHIFT 21 435b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_MASK 0x400000u 436b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_SHIFT 22 437b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_MASK 0x800000u 438b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_SHIFT 23 439b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_MASK 0x1000000u 440b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_SHIFT 24 441b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_MASK 0x2000000u 442b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_SHIFT 25 443b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_MASK 0x4000000u 444b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_SHIFT 26 445b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_MASK 0x8000000u 446b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_SHIFT 27 447b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_MASK 0x10000000u 448b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_SHIFT 28 449b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_MASK 0x20000000u 450b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_SHIFT 29 451b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_MASK 0x40000000u 452b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_SHIFT 30 453b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_MASK 0x80000000u 454b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_SHIFT 31 455b1d902a9SAdrian Alonso /* GPR4 Bit Fields */ 456b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_MASK 0x1u 457b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_SHIFT 0 458b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_MASK 0x2u 459b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_SHIFT 1 460b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_MASK 0x4u 461b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_SHIFT 2 462b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_MASK 0x8u 463b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_SHIFT 3 464b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_MASK 0x10u 465b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_SHIFT 4 466b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_MASK 0x20u 467b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_SHIFT 5 468b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_MASK 0x40u 469b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_SHIFT 6 470b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_MASK 0x80u 471b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_SHIFT 7 472b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_MASK 0x10000u 473b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_SHIFT 16 474b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_MASK 0x20000u 475b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_SHIFT 17 476b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_MASK 0x40000u 477b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_SHIFT 18 478b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_MASK 0x80000u 479b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_SHIFT 19 480b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_MASK 0x100000u 481b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_SHIFT 20 482b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_MASK 0x200000u 483b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_SHIFT 21 484b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_MASK 0x400000u 485b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_SHIFT 22 486b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_MASK 0x800000u 487b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_SHIFT 23 488b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK 0x6000000u 489b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_SHIFT 25 490b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_cpu_STANDBYWFI(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_cpu_STANDBYWFI_SHIFT))&IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK) 491b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK 0x18000000u 492b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_SHIFT 27 493b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR4_cpu_STANDBYWFE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR4_cpu_STANDBYWFE_SHIFT))&IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK) 494b1d902a9SAdrian Alonso /* GPR5 Bit Fields */ 495b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_MASK 0x10u 496b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_SHIFT 4 497b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_MASK 0x20u 498b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_SHIFT 5 499b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_MASK 0x40u 500b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_SHIFT 6 501b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_MASK 0x80u 502b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_SHIFT 7 503b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_MASK 0x1000u 504b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_SHIFT 12 505b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_MASK 0x80000u 506b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_SHIFT 19 507b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_MASK 0x100000u 508b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_SHIFT 20 509b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_MASK 0x200000u 510b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_SHIFT 21 511b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_MASK 0x400000u 512b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_SHIFT 22 513b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_MASK 0x1000000u 514b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_SHIFT 24 515b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_MASK 0x2000000u 516b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_SHIFT 25 517b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_MASK 0x4000000u 518b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_SHIFT 26 519b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_MASK 0x8000000u 520b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_SHIFT 27 521b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_MASK 0x10000000u 522b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_SHIFT 28 523b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_MASK 0x20000000u 524b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_SHIFT 29 525b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_MASK 0x40000000u 526b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_SHIFT 30 527b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_MASK 0x80000000u 528b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_SHIFT 31 529b1d902a9SAdrian Alonso /* GPR6 Bit Fields */ 530b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_MASK 0x1u 531b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_SHIFT 0 532b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_MASK 0x2u 533b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_SHIFT 1 534b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_MASK 0x4u 535b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_SHIFT 2 536b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_MASK 0x8u 537b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_SHIFT 3 538b1d902a9SAdrian Alonso /* GPR7 Bit Fields */ 539b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_MASK 0x1u 540b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_SHIFT 0 541b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_MASK 0x2u 542b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_SHIFT 1 543b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_MASK 0x4u 544b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_SHIFT 2 545b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_MASK 0x8u 546b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_SHIFT 3 547b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK 0x30u 548b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_SHIFT 4 549b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_SHIFT))&IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK) 550b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_MASK 0x40u 551b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_SHIFT 6 552b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_MASK 0x80u 553b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_SHIFT 7 554b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_MASK 0x100u 555b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_SHIFT 8 556b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_MASK 0x200u 557b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_SHIFT 9 558b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK 0xC00u 559b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_SHIFT 10 560b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_SHIFT))&IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK) 561b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_MASK 0x1000u 562b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_SHIFT 12 563b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_MASK 0x2000u 564b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_SHIFT 13 565b1d902a9SAdrian Alonso /* GPR8 Bit Fields */ 566b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK 0xF8u 567b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_SHIFT 3 568b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_SHIFT))&IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK) 569b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_MASK 0x100u 570b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_SHIFT 8 571b1d902a9SAdrian Alonso /* GPR9 Bit Fields */ 572b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_MASK 0x1u 573b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_SHIFT 0 574b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK 0x3Eu 575b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_SHIFT 1 576b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_SHIFT))&IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK) 577b1d902a9SAdrian Alonso /* GPR10 Bit Fields */ 578b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR10_GPR0_BF0_MASK 0x1u 579b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR10_GPR0_BF0_SHIFT 0 580b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR10_GPR_DBG_EN_MASK 0x2u 581b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR10_GPR_DBG_EN_SHIFT 1 582b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_MASK 0x4u 583b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_SHIFT 2 584b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_MASK 0x8u 585b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_SHIFT 3 586b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK 0x3F0u 587b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_SHIFT 4 588b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK) 589b1d902a9SAdrian Alonso /* GPR11 Bit Fields */ 590b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_MASK 0x1u 591b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_SHIFT 0 592b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK 0x3Eu 593b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT 1 594b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK) 595b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_MASK 0x40u 596b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_SHIFT 6 597b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK 0x380u 598b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_SHIFT 7 599b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK) 600b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_MASK 0x400u 601b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_SHIFT 10 602b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK 0x3800u 603b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT 11 604b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_SHIFT))&IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK) 605b1d902a9SAdrian Alonso /* GPR12 Bit Fields */ 606b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_MASK 0x1u 607b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_SHIFT 0 608b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_MASK 0x2u 609b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_SHIFT 1 610b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_MASK 0x8u 611b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_SHIFT 3 612b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_MASK 0x10u 613b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_SHIFT 4 614b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_MASK 0x20u 615b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_SHIFT 5 616b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK 0xF000u 617b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_SHIFT 12 618b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK) 619b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK 0x1E0000u 620b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT 17 621b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK) 622b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK 0xE00000u 623b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT 21 624b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_SHIFT))&IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK) 625b1d902a9SAdrian Alonso /* GPR13 Bit Fields */ 626b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_MASK 0x1u 627b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_SHIFT 0 628b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_MASK 0x2u 629b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_SHIFT 1 630b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_MASK 0x4u 631b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_SHIFT 2 632b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_MASK 0x8u 633b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_SHIFT 3 634b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_MASK 0x10u 635b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_SHIFT 4 636b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_MASK 0x20u 637b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_SHIFT 5 638b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_MASK 0x40u 639b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_SHIFT 6 640b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_MASK 0x80u 641b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_SHIFT 7 642b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_MASK 0x100u 643b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_SHIFT 8 644b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_MASK 0x200u 645b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_SHIFT 9 646b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_MASK 0x400u 647b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_SHIFT 10 648b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_MASK 0x800u 649b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_SHIFT 11 650b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_MASK 0x1000u 651b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_SHIFT 12 652b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_MASK 0x2000u 653b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_SHIFT 13 654b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_MASK 0x4000u 655b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_SHIFT 14 656b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_MASK 0x8000u 657b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_SHIFT 15 658b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK 0xFF0000u 659b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT 16 660b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_SHIFT))&IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK) 661b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK 0xF000000u 662b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_SHIFT 24 663b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_SHIFT))&IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK) 664b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_MASK 0x10000000u 665b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_SHIFT 28 666b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_MASK 0x20000000u 667b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_SHIFT 29 668b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_MASK 0x40000000u 669b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_SHIFT 30 670b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_MASK 0x80000000u 671b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_SHIFT 31 672b1d902a9SAdrian Alonso /* GPR14 Bit Fields */ 673b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_MASK 0x1u 674b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_SHIFT 0 675b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_MASK 0x2u 676b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_SHIFT 1 677b1d902a9SAdrian Alonso /* GPR15 Bit Fields */ 678b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_MASK 0x1u 679b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_SHIFT 0 680b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_MASK 0x2u 681b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_SHIFT 1 682b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK 0x3FFCu 683b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_SHIFT 2 684b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_SHIFT))&IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK) 685b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK 0x3F0000u 686b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_SHIFT 16 687b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_SHIFT))&IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK) 688b1d902a9SAdrian Alonso /* GPR16 Bit Fields */ 689b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK 0x3u 690b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT 0 691b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK) 692b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_MASK 0x4u 693b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_SHIFT 2 694b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_MASK 0x8u 695b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_SHIFT 3 696b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_MASK 0x10u 697b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_SHIFT 4 698b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_MASK 0x20u 699b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_SHIFT 5 700b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK 0x3C0u 701b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_SHIFT 6 702b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK) 703b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_MASK 0x400u 704b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_SHIFT 10 705b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_MASK 0x800u 706b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_SHIFT 11 707b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_MASK 0x1000u 708b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_SHIFT 12 709b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK 0xE000u 710b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_SHIFT 13 711b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK) 712b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_MASK 0x10000u 713b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_SHIFT 16 714b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_MASK 0x20000u 715b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_SHIFT 17 716b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK 0x180000u 717b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_SHIFT 19 718b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_SHIFT))&IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK) 719b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_MASK 0x200000u 720b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_SHIFT 21 721b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_MASK 0x400000u 722b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_SHIFT 22 723b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_MASK 0x800000u 724b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_SHIFT 23 725b1d902a9SAdrian Alonso /* GPR17 Bit Fields */ 726b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK 0xFFu 727b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT 0 728b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT))&IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK) 729b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK 0xFF00u 730b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_SHIFT 8 731b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_SHIFT))&IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK) 732b1d902a9SAdrian Alonso /* GPR18 Bit Fields */ 733b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK 0x7u 734b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT 0 735b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK) 736b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK 0x18u 737b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_SHIFT 3 738b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK) 739b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK 0x60u 740b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_SHIFT 5 741b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK) 742b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK 0x3F00u 743b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_SHIFT 8 744b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK) 745b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_MASK 0x4000u 746b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_SHIFT 14 747b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK 0x7F0000u 748b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_SHIFT 16 749b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK) 750b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK 0x3000000u 751b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_SHIFT 24 752b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_SHIFT))&IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK) 753b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_MASK 0x4000000u 754b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_SHIFT 26 755b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_MASK 0x8000000u 756b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_SHIFT 27 757b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_MASK 0x10000000u 758b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_SHIFT 28 759b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_MASK 0x20000000u 760b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_SHIFT 29 761b1d902a9SAdrian Alonso /* GPR19 Bit Fields */ 762b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_MASK 0x1u 763b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_SHIFT 0 764b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK 0xFF00u 765b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_SHIFT 8 766b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_SHIFT))&IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK) 767b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_MASK 0x10000u 768b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_SHIFT 16 769b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_MASK 0x20000u 770b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_SHIFT 17 771b1d902a9SAdrian Alonso /* GPR20 Bit Fields */ 772b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK 0x3Fu 773b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT 0 774b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR20_GPR_LVDS_P(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK) 775b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK 0x3F00u 776b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR20_GPR_LVDS_M_SHIFT 8 777b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR20_GPR_LVDS_M(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_M_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK) 778b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK 0x30000u 779b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR20_GPR_LVDS_S_SHIFT 16 780b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR20_GPR_LVDS_S(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_S_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK) 781b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_MASK 0x1000000u 782b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_SHIFT 24 783b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_MASK 0x2000000u 784b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_SHIFT 25 785b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK 0x38000000u 786b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_SHIFT 27 787b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_SHIFT))&IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK) 788b1d902a9SAdrian Alonso /* GPR21 Bit Fields */ 789b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK 0x7u 790b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT 0 791b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK) 792b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK 0x38u 793b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_SHIFT 3 794b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK) 795b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK 0x1C0u 796b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_SHIFT 6 797b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK) 798b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK 0xE00u 799b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_SHIFT 9 800b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK) 801b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK 0x7000u 802b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_SHIFT 12 803b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK) 804b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK 0x38000u 805b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_SHIFT 15 806b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_SHIFT))&IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK) 807b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_MASK 0x40000u 808b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_SHIFT 18 809b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_MASK 0x80000u 810b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_SHIFT 19 811b1d902a9SAdrian Alonso /* GPR22 Bit Fields */ 812b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK 0xFF0000u 813b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_SHIFT 16 814b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR22_ddrc_mrr_data_out(x) (((uint32_t)(((uint32_t)(x))<<IOMUXC_GPR_GPR22_ddrc_mrr_data_out_SHIFT))&IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK) 815b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_MASK 0x1000000u 816b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_SHIFT 24 817b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_MASK 0x2000000u 818b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_SHIFT 25 819b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_MASK 0x4000000u 820b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_SHIFT 26 821b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_MASK 0x8000000u 822b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_SHIFT 27 823b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_MASK 0x10000000u 824b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_SHIFT 28 825b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_MASK 0x20000000u 826b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_SHIFT 29 827b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_MASK 0x80000000u 828b1d902a9SAdrian Alonso #define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_SHIFT 31 829b1d902a9SAdrian Alonso 830b1d902a9SAdrian Alonso #define IMX7D_GPR5_CSI1_MUX_CTRL_MASK (0x1 << 4) 831b1d902a9SAdrian Alonso #define IMX7D_GPR5_CSI1_MUX_CTRL_PARALLEL_CSI (0x0 << 4) 832b1d902a9SAdrian Alonso #define IMX7D_GPR5_CSI1_MUX_CTRL_MIPI_CSI (0x1 << 4) 833b1d902a9SAdrian Alonso 834b1d902a9SAdrian Alonso struct iomuxc { 835b1d902a9SAdrian Alonso u32 gpr[23]; 836b1d902a9SAdrian Alonso /* mux and pad registers */ 837b1d902a9SAdrian Alonso }; 838b1d902a9SAdrian Alonso 839b1d902a9SAdrian Alonso struct iomuxc_gpr_base_regs { 840b1d902a9SAdrian Alonso u32 gpr[23]; /* 0x000 */ 841b1d902a9SAdrian Alonso }; 842b1d902a9SAdrian Alonso 843b1d902a9SAdrian Alonso /* ECSPI registers */ 844b1d902a9SAdrian Alonso struct cspi_regs { 845b1d902a9SAdrian Alonso u32 rxdata; 846b1d902a9SAdrian Alonso u32 txdata; 847b1d902a9SAdrian Alonso u32 ctrl; 848b1d902a9SAdrian Alonso u32 cfg; 849b1d902a9SAdrian Alonso u32 intr; 850b1d902a9SAdrian Alonso u32 dma; 851b1d902a9SAdrian Alonso u32 stat; 852b1d902a9SAdrian Alonso u32 period; 853b1d902a9SAdrian Alonso }; 854b1d902a9SAdrian Alonso 855b1d902a9SAdrian Alonso /* 856b1d902a9SAdrian Alonso * CSPI register definitions 857b1d902a9SAdrian Alonso */ 858b1d902a9SAdrian Alonso #define MXC_ECSPI 859b1d902a9SAdrian Alonso #define MXC_CSPICTRL_EN (1 << 0) 860b1d902a9SAdrian Alonso #define MXC_CSPICTRL_MODE (1 << 1) 861b1d902a9SAdrian Alonso #define MXC_CSPICTRL_XCH (1 << 2) 862b1d902a9SAdrian Alonso #define MXC_CSPICTRL_MODE_MASK (0xf << 4) 863b1d902a9SAdrian Alonso #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12) 864b1d902a9SAdrian Alonso #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20) 865b1d902a9SAdrian Alonso #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12) 866b1d902a9SAdrian Alonso #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8) 867b1d902a9SAdrian Alonso #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18) 868b1d902a9SAdrian Alonso #define MXC_CSPICTRL_MAXBITS 0xfff 869b1d902a9SAdrian Alonso #define MXC_CSPICTRL_TC (1 << 7) 870b1d902a9SAdrian Alonso #define MXC_CSPICTRL_RXOVF (1 << 6) 871b1d902a9SAdrian Alonso #define MXC_CSPIPERIOD_32KHZ (1 << 15) 872b1d902a9SAdrian Alonso #define MAX_SPI_BYTES 32 873b1d902a9SAdrian Alonso 874b1d902a9SAdrian Alonso /* Bit position inside CTRL register to be associated with SS */ 875b1d902a9SAdrian Alonso #define MXC_CSPICTRL_CHAN 18 876b1d902a9SAdrian Alonso 877b1d902a9SAdrian Alonso /* Bit position inside CON register to be associated with SS */ 878b1d902a9SAdrian Alonso #define MXC_CSPICON_PHA 0 /* SCLK phase control */ 879b1d902a9SAdrian Alonso #define MXC_CSPICON_POL 4 /* SCLK polarity */ 880b1d902a9SAdrian Alonso #define MXC_CSPICON_SSPOL 12 /* SS polarity */ 881b1d902a9SAdrian Alonso #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */ 882b1d902a9SAdrian Alonso 883b1d902a9SAdrian Alonso #define MXC_SPI_BASE_ADDRESSES \ 884b1d902a9SAdrian Alonso ECSPI1_BASE_ADDR, \ 885b1d902a9SAdrian Alonso ECSPI2_BASE_ADDR, \ 886b1d902a9SAdrian Alonso ECSPI3_BASE_ADDR, \ 887b1d902a9SAdrian Alonso ECSPI4_BASE_ADDR 888b1d902a9SAdrian Alonso 8897de47036SPeng Fan #define CSU_INIT_SEC_LEVEL0 0x00FF00FF 8907de47036SPeng Fan #define CSU_NUM_REGS 64 8917de47036SPeng Fan 892b1d902a9SAdrian Alonso struct ocotp_regs { 893b1d902a9SAdrian Alonso u32 ctrl; 894b1d902a9SAdrian Alonso u32 ctrl_set; 895b1d902a9SAdrian Alonso u32 ctrl_clr; 896b1d902a9SAdrian Alonso u32 ctrl_tog; 897b1d902a9SAdrian Alonso u32 timing; 898b1d902a9SAdrian Alonso u32 rsvd0[3]; 899b1d902a9SAdrian Alonso u32 data0; 900b1d902a9SAdrian Alonso u32 rsvd1[3]; 901b1d902a9SAdrian Alonso u32 data1; 902b1d902a9SAdrian Alonso u32 rsvd2[3]; 903b1d902a9SAdrian Alonso u32 data2; 904b1d902a9SAdrian Alonso u32 rsvd3[3]; 905b1d902a9SAdrian Alonso u32 data3; 906b1d902a9SAdrian Alonso u32 rsvd4[3]; 907b1d902a9SAdrian Alonso u32 read_ctrl; 908b1d902a9SAdrian Alonso u32 rsvd5[3]; 909b1d902a9SAdrian Alonso u32 read_fuse_data0; 910b1d902a9SAdrian Alonso u32 rsvd6[3]; 911b1d902a9SAdrian Alonso u32 read_fuse_data1; 912b1d902a9SAdrian Alonso u32 rsvd7[3]; 913b1d902a9SAdrian Alonso u32 read_fuse_data2; 914b1d902a9SAdrian Alonso u32 rsvd8[3]; 915b1d902a9SAdrian Alonso u32 read_fuse_data3; 916b1d902a9SAdrian Alonso u32 rsvd9[3]; 917b1d902a9SAdrian Alonso u32 sw_sticky; 918b1d902a9SAdrian Alonso u32 rsvd10[3]; 919b1d902a9SAdrian Alonso u32 scs; 920b1d902a9SAdrian Alonso u32 scs_set; 921b1d902a9SAdrian Alonso u32 scs_clr; 922b1d902a9SAdrian Alonso u32 scs_tog; 923b1d902a9SAdrian Alonso u32 crc_addr; 924b1d902a9SAdrian Alonso u32 rsvd11[3]; 925b1d902a9SAdrian Alonso u32 crc_value; 926b1d902a9SAdrian Alonso u32 rsvd12[3]; 927b1d902a9SAdrian Alonso u32 version; 928b1d902a9SAdrian Alonso u32 rsvd13[0xc3]; 929b1d902a9SAdrian Alonso 930b1d902a9SAdrian Alonso struct fuse_bank { /* offset 0x400 */ 931b1d902a9SAdrian Alonso u32 fuse_regs[0x10]; 932b1d902a9SAdrian Alonso } bank[16]; 933b1d902a9SAdrian Alonso }; 934b1d902a9SAdrian Alonso 935b1d902a9SAdrian Alonso struct fuse_bank0_regs { 936b1d902a9SAdrian Alonso u32 lock; 937b1d902a9SAdrian Alonso u32 rsvd0[3]; 938b1d902a9SAdrian Alonso u32 tester0; 939b1d902a9SAdrian Alonso u32 rsvd1[3]; 940b1d902a9SAdrian Alonso u32 tester1; 941b1d902a9SAdrian Alonso u32 rsvd2[3]; 942b1d902a9SAdrian Alonso u32 tester2; 943b1d902a9SAdrian Alonso u32 rsvd3[3]; 944b1d902a9SAdrian Alonso }; 945b1d902a9SAdrian Alonso 946b1d902a9SAdrian Alonso struct fuse_bank1_regs { 947b1d902a9SAdrian Alonso u32 tester3; 948b1d902a9SAdrian Alonso u32 rsvd0[3]; 949b1d902a9SAdrian Alonso u32 tester4; 950b1d902a9SAdrian Alonso u32 rsvd1[3]; 951b1d902a9SAdrian Alonso u32 tester5; 952b1d902a9SAdrian Alonso u32 rsvd2[3]; 953b1d902a9SAdrian Alonso u32 cfg0; 954b1d902a9SAdrian Alonso u32 rsvd3[3]; 955b1d902a9SAdrian Alonso }; 956b1d902a9SAdrian Alonso 957b1d902a9SAdrian Alonso struct fuse_bank2_regs { 958b1d902a9SAdrian Alonso u32 cfg1; 959b1d902a9SAdrian Alonso u32 rsvd0[3]; 960b1d902a9SAdrian Alonso u32 cfg2; 961b1d902a9SAdrian Alonso u32 rsvd1[3]; 962b1d902a9SAdrian Alonso u32 cfg3; 963b1d902a9SAdrian Alonso u32 rsvd2[3]; 964b1d902a9SAdrian Alonso u32 cfg4; 965b1d902a9SAdrian Alonso u32 rsvd3[3]; 966b1d902a9SAdrian Alonso }; 967b1d902a9SAdrian Alonso 968b1d902a9SAdrian Alonso struct fuse_bank3_regs { 969b1d902a9SAdrian Alonso u32 mem_trim0; 970b1d902a9SAdrian Alonso u32 rsvd0[3]; 971b1d902a9SAdrian Alonso u32 mem_trim1; 972b1d902a9SAdrian Alonso u32 rsvd1[3]; 973b1d902a9SAdrian Alonso u32 ana0; 974b1d902a9SAdrian Alonso u32 rsvd2[3]; 975b1d902a9SAdrian Alonso u32 ana1; 976b1d902a9SAdrian Alonso u32 rsvd3[3]; 977b1d902a9SAdrian Alonso }; 978b1d902a9SAdrian Alonso 979b1d902a9SAdrian Alonso struct fuse_bank8_regs { 980b1d902a9SAdrian Alonso u32 sjc_resp_low; 981b1d902a9SAdrian Alonso u32 rsvd0[3]; 982b1d902a9SAdrian Alonso u32 sjc_resp_high; 983b1d902a9SAdrian Alonso u32 rsvd1[3]; 984b1d902a9SAdrian Alonso u32 usb_id; 985b1d902a9SAdrian Alonso u32 rsvd2[3]; 986b1d902a9SAdrian Alonso u32 field_return; 987b1d902a9SAdrian Alonso u32 rsvd3[3]; 988b1d902a9SAdrian Alonso }; 989b1d902a9SAdrian Alonso 990b1d902a9SAdrian Alonso struct fuse_bank9_regs { 991b1d902a9SAdrian Alonso u32 mac_addr0; 992b1d902a9SAdrian Alonso u32 rsvd0[3]; 993b1d902a9SAdrian Alonso u32 mac_addr1; 994b1d902a9SAdrian Alonso u32 rsvd1[3]; 995b1d902a9SAdrian Alonso u32 mac_addr2; 996b1d902a9SAdrian Alonso u32 rsvd2[7]; 997b1d902a9SAdrian Alonso }; 998b1d902a9SAdrian Alonso 999b1d902a9SAdrian Alonso struct aipstz_regs { 1000b1d902a9SAdrian Alonso u32 mprot0; 1001b1d902a9SAdrian Alonso u32 mprot1; 1002b1d902a9SAdrian Alonso u32 rsvd[0xe]; 1003b1d902a9SAdrian Alonso u32 opacr0; 1004b1d902a9SAdrian Alonso u32 opacr1; 1005b1d902a9SAdrian Alonso u32 opacr2; 1006b1d902a9SAdrian Alonso u32 opacr3; 1007b1d902a9SAdrian Alonso u32 opacr4; 1008b1d902a9SAdrian Alonso }; 1009b1d902a9SAdrian Alonso 1010b1d902a9SAdrian Alonso struct wdog_regs { 1011b1d902a9SAdrian Alonso u16 wcr; /* Control */ 1012b1d902a9SAdrian Alonso u16 wsr; /* Service */ 1013b1d902a9SAdrian Alonso u16 wrsr; /* Reset Status */ 1014b1d902a9SAdrian Alonso u16 wicr; /* Interrupt Control */ 1015b1d902a9SAdrian Alonso u16 wmcr; /* Miscellaneous Control */ 1016b1d902a9SAdrian Alonso }; 1017b1d902a9SAdrian Alonso 1018b1d902a9SAdrian Alonso struct dbg_monitor_regs { 1019b1d902a9SAdrian Alonso u32 ctrl[4]; /* Control */ 1020b1d902a9SAdrian Alonso u32 master_en[4]; /* Master enable */ 1021b1d902a9SAdrian Alonso u32 irq[4]; /* IRQ */ 1022b1d902a9SAdrian Alonso u32 trap_addr_low[4]; /* Trap address low */ 1023b1d902a9SAdrian Alonso u32 trap_addr_high[4]; /* Trap address high */ 1024b1d902a9SAdrian Alonso u32 trap_id[4]; /* Trap ID */ 1025b1d902a9SAdrian Alonso u32 snvs_addr[4]; /* SNVS address */ 1026b1d902a9SAdrian Alonso u32 snvs_data[4]; /* SNVS data */ 1027b1d902a9SAdrian Alonso u32 snvs_info[4]; /* SNVS info */ 1028b1d902a9SAdrian Alonso u32 version[4]; /* Version */ 1029b1d902a9SAdrian Alonso }; 1030b1d902a9SAdrian Alonso 1031b1d902a9SAdrian Alonso struct rdc_regs { 1032b1d902a9SAdrian Alonso u32 vir; /* Version information */ 1033b1d902a9SAdrian Alonso u32 reserved1[8]; 1034b1d902a9SAdrian Alonso u32 stat; /* Status */ 1035b1d902a9SAdrian Alonso u32 intctrl; /* Interrupt and Control */ 1036b1d902a9SAdrian Alonso u32 intstat; /* Interrupt Status */ 1037b1d902a9SAdrian Alonso u32 reserved2[116]; 1038b1d902a9SAdrian Alonso u32 mda[27]; /* Master Domain Assignment */ 1039b1d902a9SAdrian Alonso u32 reserved3[101]; 1040b1d902a9SAdrian Alonso u32 pdap[118]; /* Peripheral Domain Access Permissions */ 1041b1d902a9SAdrian Alonso u32 reserved4[138]; 1042b1d902a9SAdrian Alonso struct { 1043b1d902a9SAdrian Alonso u32 mrsa; /* Memory Region Start Address */ 1044b1d902a9SAdrian Alonso u32 mrea; /* Memory Region End Address */ 1045b1d902a9SAdrian Alonso u32 mrc; /* Memory Region Control */ 1046b1d902a9SAdrian Alonso u32 mrvs; /* Memory Region Violation Status */ 1047b1d902a9SAdrian Alonso } mem_region[52]; 1048b1d902a9SAdrian Alonso }; 1049b1d902a9SAdrian Alonso 1050b1d902a9SAdrian Alonso struct rdc_sema_regs { 1051b1d902a9SAdrian Alonso u8 gate[64]; /* Gate */ 1052b1d902a9SAdrian Alonso u16 rstgt; /* Reset Gate */ 1053b1d902a9SAdrian Alonso }; 1054b1d902a9SAdrian Alonso 1055b1d902a9SAdrian Alonso #define MXS_LCDIF_BASE ELCDIF1_IPS_BASE_ADDR 1056b1d902a9SAdrian Alonso 1057b1d902a9SAdrian Alonso #define LCDIF_CTRL_SFTRST (1 << 31) 1058b1d902a9SAdrian Alonso #define LCDIF_CTRL_CLKGATE (1 << 30) 1059b1d902a9SAdrian Alonso #define LCDIF_CTRL_YCBCR422_INPUT (1 << 29) 1060b1d902a9SAdrian Alonso #define LCDIF_CTRL_READ_WRITEB (1 << 28) 1061b1d902a9SAdrian Alonso #define LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE (1 << 27) 1062b1d902a9SAdrian Alonso #define LCDIF_CTRL_DATA_SHIFT_DIR (1 << 26) 1063b1d902a9SAdrian Alonso #define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x1f << 21) 1064b1d902a9SAdrian Alonso #define LCDIF_CTRL_SHIFT_NUM_BITS_OFFSET 21 1065b1d902a9SAdrian Alonso #define LCDIF_CTRL_DVI_MODE (1 << 20) 1066b1d902a9SAdrian Alonso #define LCDIF_CTRL_BYPASS_COUNT (1 << 19) 1067b1d902a9SAdrian Alonso #define LCDIF_CTRL_VSYNC_MODE (1 << 18) 1068b1d902a9SAdrian Alonso #define LCDIF_CTRL_DOTCLK_MODE (1 << 17) 1069b1d902a9SAdrian Alonso #define LCDIF_CTRL_DATA_SELECT (1 << 16) 1070b1d902a9SAdrian Alonso #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0x3 << 14) 1071b1d902a9SAdrian Alonso #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_OFFSET 14 1072b1d902a9SAdrian Alonso #define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3 << 12) 1073b1d902a9SAdrian Alonso #define LCDIF_CTRL_CSC_DATA_SWIZZLE_OFFSET 12 1074b1d902a9SAdrian Alonso #define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0x3 << 10) 1075b1d902a9SAdrian Alonso #define LCDIF_CTRL_LCD_DATABUS_WIDTH_OFFSET 10 1076b1d902a9SAdrian Alonso #define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT (0 << 10) 1077b1d902a9SAdrian Alonso #define LCDIF_CTRL_LCD_DATABUS_WIDTH_8BIT (1 << 10) 1078b1d902a9SAdrian Alonso #define LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT (2 << 10) 1079b1d902a9SAdrian Alonso #define LCDIF_CTRL_LCD_DATABUS_WIDTH_24BIT (3 << 10) 1080b1d902a9SAdrian Alonso #define LCDIF_CTRL_WORD_LENGTH_MASK (0x3 << 8) 1081b1d902a9SAdrian Alonso #define LCDIF_CTRL_WORD_LENGTH_OFFSET 8 1082b1d902a9SAdrian Alonso #define LCDIF_CTRL_WORD_LENGTH_16BIT (0 << 8) 1083b1d902a9SAdrian Alonso #define LCDIF_CTRL_WORD_LENGTH_8BIT (1 << 8) 1084b1d902a9SAdrian Alonso #define LCDIF_CTRL_WORD_LENGTH_18BIT (2 << 8) 1085b1d902a9SAdrian Alonso #define LCDIF_CTRL_WORD_LENGTH_24BIT (3 << 8) 1086b1d902a9SAdrian Alonso #define LCDIF_CTRL_RGB_TO_YCBCR422_CSC (1 << 7) 1087b1d902a9SAdrian Alonso #define LCDIF_CTRL_LCDIF_MASTER (1 << 5) 1088b1d902a9SAdrian Alonso #define LCDIF_CTRL_DATA_FORMAT_16_BIT (1 << 3) 1089b1d902a9SAdrian Alonso #define LCDIF_CTRL_DATA_FORMAT_18_BIT (1 << 2) 1090b1d902a9SAdrian Alonso #define LCDIF_CTRL_DATA_FORMAT_24_BIT (1 << 1) 1091b1d902a9SAdrian Alonso #define LCDIF_CTRL_RUN (1 << 0) 1092b1d902a9SAdrian Alonso 1093b1d902a9SAdrian Alonso #define LCDIF_CTRL1_COMBINE_MPU_WR_STRB (1 << 27) 1094b1d902a9SAdrian Alonso #define LCDIF_CTRL1_BM_ERROR_IRQ_EN (1 << 26) 1095b1d902a9SAdrian Alonso #define LCDIF_CTRL1_BM_ERROR_IRQ (1 << 25) 1096b1d902a9SAdrian Alonso #define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW (1 << 24) 1097b1d902a9SAdrian Alonso #define LCDIF_CTRL1_INTERLACE_FIELDS (1 << 23) 1098b1d902a9SAdrian Alonso #define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD (1 << 22) 1099b1d902a9SAdrian Alonso #define LCDIF_CTRL1_FIFO_CLEAR (1 << 21) 1100b1d902a9SAdrian Alonso #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS (1 << 20) 1101b1d902a9SAdrian Alonso #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16) 1102b1d902a9SAdrian Alonso #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET 16 1103b1d902a9SAdrian Alonso #define LCDIF_CTRL1_OVERFLOW_IRQ_EN (1 << 15) 1104b1d902a9SAdrian Alonso #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN (1 << 14) 1105b1d902a9SAdrian Alonso #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13) 1106b1d902a9SAdrian Alonso #define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN (1 << 12) 1107b1d902a9SAdrian Alonso #define LCDIF_CTRL1_OVERFLOW_IRQ (1 << 11) 1108b1d902a9SAdrian Alonso #define LCDIF_CTRL1_UNDERFLOW_IRQ (1 << 10) 1109b1d902a9SAdrian Alonso #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ (1 << 9) 1110b1d902a9SAdrian Alonso #define LCDIF_CTRL1_VSYNC_EDGE_IRQ (1 << 8) 1111b1d902a9SAdrian Alonso #define LCDIF_CTRL1_BUSY_ENABLE (1 << 2) 1112b1d902a9SAdrian Alonso #define LCDIF_CTRL1_MODE86 (1 << 1) 1113b1d902a9SAdrian Alonso #define LCDIF_CTRL1_RESET (1 << 0) 1114b1d902a9SAdrian Alonso 1115b1d902a9SAdrian Alonso #define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0x7 << 21) 1116b1d902a9SAdrian Alonso #define LCDIF_CTRL2_OUTSTANDING_REQS_OFFSET 21 1117b1d902a9SAdrian Alonso #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1 (0x0 << 21) 1118b1d902a9SAdrian Alonso #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2 (0x1 << 21) 1119b1d902a9SAdrian Alonso #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4 (0x2 << 21) 1120b1d902a9SAdrian Alonso #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8 (0x3 << 21) 1121b1d902a9SAdrian Alonso #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16 (0x4 << 21) 1122b1d902a9SAdrian Alonso #define LCDIF_CTRL2_BURST_LEN_8 (1 << 20) 1123b1d902a9SAdrian Alonso #define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x7 << 16) 1124b1d902a9SAdrian Alonso #define LCDIF_CTRL2_ODD_LINE_PATTERN_OFFSET 16 1125b1d902a9SAdrian Alonso #define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB (0x0 << 16) 1126b1d902a9SAdrian Alonso #define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG (0x1 << 16) 1127b1d902a9SAdrian Alonso #define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR (0x2 << 16) 1128b1d902a9SAdrian Alonso #define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB (0x3 << 16) 1129b1d902a9SAdrian Alonso #define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG (0x4 << 16) 1130b1d902a9SAdrian Alonso #define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR (0x5 << 16) 1131b1d902a9SAdrian Alonso #define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7 << 12) 1132b1d902a9SAdrian Alonso #define LCDIF_CTRL2_EVEN_LINE_PATTERN_OFFSET 12 1133b1d902a9SAdrian Alonso #define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB (0x0 << 12) 1134b1d902a9SAdrian Alonso #define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG (0x1 << 12) 1135b1d902a9SAdrian Alonso #define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR (0x2 << 12) 1136b1d902a9SAdrian Alonso #define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB (0x3 << 12) 1137b1d902a9SAdrian Alonso #define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG (0x4 << 12) 1138b1d902a9SAdrian Alonso #define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR (0x5 << 12) 1139b1d902a9SAdrian Alonso #define LCDIF_CTRL2_READ_PACK_DIR (1 << 10) 1140b1d902a9SAdrian Alonso #define LCDIF_CTRL2_READ_MODE_OUTPUT_IN_RGB_FORMAT (1 << 9) 1141b1d902a9SAdrian Alonso #define LCDIF_CTRL2_READ_MODE_6_BIT_INPUT (1 << 8) 1142b1d902a9SAdrian Alonso #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x7 << 4) 1143b1d902a9SAdrian Alonso #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_OFFSET 4 1144b1d902a9SAdrian Alonso #define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0x7 << 1) 1145b1d902a9SAdrian Alonso #define LCDIF_CTRL2_INITIAL_DUMMY_READ_OFFSET 1 1146b1d902a9SAdrian Alonso 1147b1d902a9SAdrian Alonso #define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16) 1148b1d902a9SAdrian Alonso #define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET 16 1149b1d902a9SAdrian Alonso #define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0) 1150b1d902a9SAdrian Alonso #define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0 1151b1d902a9SAdrian Alonso 1152b1d902a9SAdrian Alonso #define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff 1153b1d902a9SAdrian Alonso #define LCDIF_CUR_BUF_ADDR_OFFSET 0 1154b1d902a9SAdrian Alonso 1155b1d902a9SAdrian Alonso #define LCDIF_NEXT_BUF_ADDR_MASK 0xffffffff 1156b1d902a9SAdrian Alonso #define LCDIF_NEXT_BUF_ADDR_OFFSET 0 1157b1d902a9SAdrian Alonso 1158b1d902a9SAdrian Alonso #define LCDIF_TIMING_CMD_HOLD_MASK (0xff << 24) 1159b1d902a9SAdrian Alonso #define LCDIF_TIMING_CMD_HOLD_OFFSET 24 1160b1d902a9SAdrian Alonso #define LCDIF_TIMING_CMD_SETUP_MASK (0xff << 16) 1161b1d902a9SAdrian Alonso #define LCDIF_TIMING_CMD_SETUP_OFFSET 16 1162b1d902a9SAdrian Alonso #define LCDIF_TIMING_DATA_HOLD_MASK (0xff << 8) 1163b1d902a9SAdrian Alonso #define LCDIF_TIMING_DATA_HOLD_OFFSET 8 1164b1d902a9SAdrian Alonso #define LCDIF_TIMING_DATA_SETUP_MASK (0xff << 0) 1165b1d902a9SAdrian Alonso #define LCDIF_TIMING_DATA_SETUP_OFFSET 0 1166b1d902a9SAdrian Alonso 1167b1d902a9SAdrian Alonso #define LCDIF_VDCTRL0_VSYNC_OEB (1 << 29) 1168b1d902a9SAdrian Alonso #define LCDIF_VDCTRL0_ENABLE_PRESENT (1 << 28) 1169b1d902a9SAdrian Alonso #define LCDIF_VDCTRL0_VSYNC_POL (1 << 27) 1170b1d902a9SAdrian Alonso #define LCDIF_VDCTRL0_HSYNC_POL (1 << 26) 1171b1d902a9SAdrian Alonso #define LCDIF_VDCTRL0_DOTCLK_POL (1 << 25) 1172b1d902a9SAdrian Alonso #define LCDIF_VDCTRL0_ENABLE_POL (1 << 24) 1173b1d902a9SAdrian Alonso #define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT (1 << 21) 1174b1d902a9SAdrian Alonso #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT (1 << 20) 1175b1d902a9SAdrian Alonso #define LCDIF_VDCTRL0_HALF_LINE (1 << 19) 1176b1d902a9SAdrian Alonso #define LCDIF_VDCTRL0_HALF_LINE_MODE (1 << 18) 1177b1d902a9SAdrian Alonso #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff 1178b1d902a9SAdrian Alonso #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0 1179b1d902a9SAdrian Alonso 1180b1d902a9SAdrian Alonso #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff 1181b1d902a9SAdrian Alonso #define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0 1182b1d902a9SAdrian Alonso 1183b1d902a9SAdrian Alonso #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18) 1184b1d902a9SAdrian Alonso #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18 1185b1d902a9SAdrian Alonso #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff 1186b1d902a9SAdrian Alonso #define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0 1187b1d902a9SAdrian Alonso 1188b1d902a9SAdrian Alonso #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS (1 << 29) 1189b1d902a9SAdrian Alonso #define LCDIF_VDCTRL3_VSYNC_ONLY (1 << 28) 1190b1d902a9SAdrian Alonso #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16) 1191b1d902a9SAdrian Alonso #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET 16 1192b1d902a9SAdrian Alonso #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0) 1193b1d902a9SAdrian Alonso #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0 1194b1d902a9SAdrian Alonso 1195b1d902a9SAdrian Alonso #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29) 1196b1d902a9SAdrian Alonso #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET 29 1197b1d902a9SAdrian Alonso #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON (1 << 18) 1198b1d902a9SAdrian Alonso #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff 1199b1d902a9SAdrian Alonso #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0 1200b1d902a9SAdrian Alonso 1201b1d902a9SAdrian Alonso 1202b1d902a9SAdrian Alonso extern void check_cpu_temperature(void); 1203b1d902a9SAdrian Alonso 1204b1d902a9SAdrian Alonso extern void pcie_power_up(void); 1205b1d902a9SAdrian Alonso extern void pcie_power_off(void); 1206b1d902a9SAdrian Alonso 1207b1d902a9SAdrian Alonso /* If ROM fail back to USB recover mode, USBPH0_PWD will be clear to use USB 1208b1d902a9SAdrian Alonso * If boot from the other mode, USB0_PWD will keep reset value 1209b1d902a9SAdrian Alonso */ 1210b1d902a9SAdrian Alonso #define is_boot_from_usb(void) (readl(USBOTG1_IPS_BASE_ADDR + 0x158) || \ 1211b1d902a9SAdrian Alonso readl(USBOTG2_IPS_BASE_ADDR + 0x158)) 1212b1d902a9SAdrian Alonso #define disconnect_from_pc(void) writel(0x0, USBOTG1_IPS_BASE_ADDR + 0x140) 1213b1d902a9SAdrian Alonso 1214b1d902a9SAdrian Alonso struct bootrom_sw_info { 1215b1d902a9SAdrian Alonso u8 reserved_1; 1216b1d902a9SAdrian Alonso u8 boot_dev_instance; 1217b1d902a9SAdrian Alonso u8 boot_dev_type; 1218b1d902a9SAdrian Alonso u8 reserved_2; 1219b1d902a9SAdrian Alonso u32 arm_core_freq; 1220b1d902a9SAdrian Alonso u32 axi_freq; 1221b1d902a9SAdrian Alonso u32 ddr_freq; 1222b1d902a9SAdrian Alonso u32 gpt1_freq; 1223b1d902a9SAdrian Alonso u32 reserved_3[3]; 1224b1d902a9SAdrian Alonso }; 1225b1d902a9SAdrian Alonso 1226b1d902a9SAdrian Alonso #endif /* __ASSEMBLER__*/ 1227b1d902a9SAdrian Alonso #endif /* __ASM_ARCH_MX7_IMX_REGS_H__ */ 1228