Lines Matching +full:0 +full:x31000000
11 #define ROM_SW_INFO_ADDR 0x000001E8
12 #define ROMCP_ARB_BASE_ADDR 0x00000000
13 #define ROMCP_ARB_END_ADDR 0x00017FFF
15 #define CAAM_ARB_BASE_ADDR 0x00100000
16 #define CAAM_ARB_END_ADDR 0x00107FFF
17 #define GIC400_ARB_BASE_ADDR 0x31000000
18 #define GIC400_ARB_END_ADDR 0x31007FFF
19 #define APBH_DMA_ARB_BASE_ADDR 0x33000000
20 #define APBH_DMA_ARB_END_ADDR 0x33007FFF
21 #define M4_BOOTROM_BASE_ADDR 0x00180000
24 #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
25 #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
28 #define GPV0_BASE_ADDR 0x32000000
29 #define GPV1_BASE_ADDR 0x32100000
30 #define GPV2_BASE_ADDR 0x32200000
31 #define GPV3_BASE_ADDR 0x32300000
32 #define GPV4_BASE_ADDR 0x32400000
33 #define GPV5_BASE_ADDR 0x32500000
34 #define GPV6_BASE_ADDR 0x32600000
35 #define GPV7_BASE_ADDR 0x32700000
37 #define OCRAM_ARB_BASE_ADDR 0x00900000
38 #define OCRAM_ARB_END_ADDR 0x0091FFFF
39 #define OCRAM_EPDC_BASE_ADDR 0x00920000
40 #define OCRAM_EPDC_END_ADDR 0x0093FFFF
41 #define OCRAM_PXP_BASE_ADDR 0x00940000
42 #define OCRAM_PXP_END_ADDR 0x00947FFF
44 #define IRAM_SIZE 0x00020000
46 #define AIPS1_ARB_BASE_ADDR 0x30000000
47 #define AIPS1_ARB_END_ADDR 0x303FFFFF
48 #define AIPS2_ARB_BASE_ADDR 0x30400000
49 #define AIPS2_ARB_END_ADDR 0x307FFFFF
50 #define AIPS3_ARB_BASE_ADDR 0x30800000
51 #define AIPS3_ARB_END_ADDR 0x30BFFFFF
53 #define WEIM_ARB_BASE_ADDR 0x28000000
54 #define WEIM_ARB_END_ADDR 0x2FFFFFFF
56 #define QSPI0_ARB_BASE_ADDR 0x60000000
57 #define QSPI0_ARB_END_ADDR 0x6FFFFFFF
58 #define PCIE_ARB_BASE_ADDR 0x40000000
59 #define PCIE_ARB_END_ADDR 0x4FFFFFFF
60 #define PCIE_REG_BASE_ADDR 0x33800000
61 #define PCIE_REG_END_ADDR 0x33803FFF
63 #define MMDC0_ARB_BASE_ADDR 0x80000000
64 #define MMDC0_ARB_END_ADDR 0xBFFFFFFF
65 #define MMDC1_ARB_BASE_ADDR 0xC0000000
66 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
69 #define ARM_PERIPHBASE 0x31000000
71 #define GLOBAL_TIMER_BASE_ADDR (ARM_PERIPHBASE + 0x0200)
72 #define PRIVATE_TIMERS_WD_BASE_ADDR (ARM_PERIPHBASE + 0x0600)
84 #define AIPS1_ON_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x1F0000)
86 #define AIPS1_OFF_BASE_ADDR (AIPS_TZ1_BASE_ADDR+0x200000)
89 #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x10000)
90 #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x20000)
91 #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x30000)
92 #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x40000)
93 #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x50000)
94 #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x60000)
95 #define IOMUXC_LPSR_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x70000)
96 #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x80000)
97 #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x90000)
98 #define WDOG3_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xA0000)
99 #define WDOG4_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xB0000)
100 #define IOMUXC_LPSR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xC0000)
101 #define GPT_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xD0000)
103 #define GPT2_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xE0000)
104 #define GPT3_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0xF0000)
105 #define GPT4_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x100000)
106 #define ROMCP_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x110000)
107 #define KPP_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x120000)
108 #define IOMUXC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x130000)
110 #define IOMUXC_GPR_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x140000)
111 #define OCOTP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x150000)
112 #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x160000)
113 #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x170000)
114 #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x180000)
115 #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x190000)
116 #define GPC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1A0000)
117 #define SEMA41_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1B0000)
118 #define SEMA42_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1C0000)
119 #define RDC_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1D0000)
120 #define CSU_IPS_BASE_ADDR (AIPS1_OFF_BASE_ADDR+0x1E0000)
123 #define AIPS2_ON_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x1F0000)
125 #define AIPS2_OFF_BASE_ADDR (AIPS_TZ2_BASE_ADDR+0x200000)
126 #define ADC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x10000)
127 #define ADC2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x20000)
128 #define ECSPI4_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x30000)
129 #define FTM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x40000)
130 #define FTM2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x50000)
131 #define PWM1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x60000)
132 #define PWM2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x70000)
133 #define PWM3_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x80000)
134 #define PWM4_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x90000)
135 #define SYSCNT_RD_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xA0000)
136 #define SYSCNT_CMP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xB0000)
137 #define SYSCNT_CTRL_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xC0000)
138 #define PCIE_PHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xD0000)
139 #define EPDC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0xF0000)
141 #define EPXP_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x100000)
142 #define CSI1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x110000)
143 #define ELCDIF1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x130000)
144 #define MIPI_CSI2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x150000)
145 #define MIPI_DSI_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x160000)
146 #define IP2APB_TZASC1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x180000)
147 #define DDRPHY_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x190000)
148 #define DDRC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1A0000)
149 #define IP2APB_PERFMON1_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1C0000)
150 #define IP2APB_PERFMON2_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1D0000)
151 #define IP2APB_AXIMON_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1E0000)
152 #define QOSC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1F0000)
154 /* AIPS_TZ#3 - Global enable (0) */
155 #define ECSPI1_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x20000)
156 #define ECSPI2_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x30000)
157 #define ECSPI3_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x40000)
158 #define UART1_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x60000)
159 #define UART3_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x80000)
160 #define UART2_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x90000)
161 #define SAI1_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xA0000)
162 #define SAI2_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xB0000)
163 #define SAI3_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xC0000)
164 #define SPBA_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0xF0000)
165 #define CAAM_IPS_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x100000)
168 #define AIPS3_ON_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x1F0000)
170 #define AIPS3_OFF_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x200000)
172 #define CAN2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x10000)
173 #define I2C1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x20000)
174 #define I2C2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x30000)
175 #define I2C3_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x40000)
176 #define I2C4_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x50000)
177 #define UART4_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x60000)
178 #define UART5_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x70000)
179 #define UART6_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x80000)
180 #define UART7_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x90000)
181 #define MUCPU_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xA0000)
182 #define MUDSP_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xB0000)
183 #define HS_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xC0000)
184 #define USBOH2_PL301_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0xD0000)
185 #define USBOTG1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x110000)
186 #define USBOTG2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x120000)
187 #define USBHSIC_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x130000)
188 #define USDHC1_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x140000)
189 #define USDHC2_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x150000)
190 #define USDHC3_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x160000)
191 #define EMVSIM1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x190000)
192 #define EMVSIM2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1A0000)
193 #define SIM1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x190000)
194 #define SIM2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1A0000)
195 #define QSPI1_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1B0000)
196 #define WEIM_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1C0000)
197 #define SDMA_PORT_IPS_HOST_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1D0000)
198 #define ENET_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1E0000)
199 #define ENET2_IPS_BASE_ADDR (AIPS3_OFF_BASE_ADDR+0x1F0000)
217 #define SNVS_LPGPR 0x68
218 #define CONFIG_SYS_FSL_SEC_OFFSET 0
221 #define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
268 #define SRC_M4_REG_OFFSET 0xC
269 #define SRC_M4C_NON_SCLR_RST_OFFSET 0
270 #define SRC_M4C_NON_SCLR_RST_MASK BIT(0)
278 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK 0x1u
279 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT 0
280 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK 0x2u
282 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK 0x4u
284 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK 0x8u
286 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK 0x10u
288 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK 0x20u
290 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK 0x40u
295 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_MASK 0x1u
296 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_SHIFT 0
297 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS0_MASK 0x6u
300 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS1_MASK 0x8u
302 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS1_MASK 0x30u
305 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS2_MASK 0x40u
307 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS2_MASK 0x180u
310 #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS3_MASK 0x200u
312 #define IOMUXC_GPR_GPR1_GPR_WEIM_ADDRS3_MASK 0xC00u
315 #define IOMUXC_GPR_GPR1_GPR_IRQ_MASK 0x1000u
317 #define IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK 0x2000u
319 #define IOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK 0x4000u
321 #define IOMUXC_GPR_GPR1_GPR_ANATOP_TESTMODE_MASK 0x8000u
323 #define IOMUXC_GPR_GPR1_GPR_PAD_ADD_DS_MASK 0x10000u
325 #define IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK 0x20000u
327 #define IOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK 0x40000u
329 #define IOMUXC_GPR_GPR1_GPR_EXC_ERR_RESP_EN_MASK 0x400000u
331 #define IOMUXC_GPR_GPR1_GPR_TZASC1_SECURE_BOOT_LOCK_MASK 0x800000u
333 #define IOMUXC_GPR_GPR1_GPR_DBG_ACK_MASK 0x30000000u
336 #define IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK 0x40000000u
339 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_MASK 0x1u
340 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LOWPOWER_SHIFT 0
341 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_SD_MASK 0x2u
343 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_DS_MASK 0x4u
345 #define IOMUXC_GPR_GPR2_GPR_MEM_PXP_LS_MASK 0x8u
347 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LOWPOWER_MASK 0x10u
349 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_SD_MASK 0x20u
351 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_DS_MASK 0x40u
353 #define IOMUXC_GPR_GPR2_GPR_MEM_LCDIF_LS_MASK 0x80u
355 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LOWPOWER_MASK 0x100u
357 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_SD_MASK 0x200u
359 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_DS_MASK 0x400u
361 #define IOMUXC_GPR_GPR2_GPR_MEM_EPDC_LS_MASK 0x800u
363 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LOWPOWER_MASK 0x1000u
365 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_SD_MASK 0x2000u
367 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_DS_MASK 0x4000u
369 #define IOMUXC_GPR_GPR2_GPR_MEM_CPU_LS_MASK 0x8000u
371 #define IOMUXC_GPR_GPR2_GPR_MQS_CLK_DIV_MASK 0xFF0000u
374 #define IOMUXC_GPR_GPR2_GPR_MQS_SW_RST_MASK 0x1000000u
376 #define IOMUXC_GPR_GPR2_GPR_MQS_EN_MASK 0x2000000u
378 #define IOMUXC_GPR_GPR2_GPR_MQS_OVERSAMPLE_MASK 0x4000000u
380 #define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_BYPASS_MASK 0x8000000u
382 #define IOMUXC_GPR_GPR2_GPR_DRAM_RESET_MASK 0x10000000u
384 #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE0_MASK 0x20000000u
386 #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE1_MASK 0x40000000u
388 #define IOMUXC_GPR_GPR2_GPR_DRAM_CKE_BYPASS_MASK 0x80000000u
391 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_MASK 0x1u
392 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_DATA_WAIT_EN_SHIFT 0
393 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_READ_ADDR_PIPELINE_EN_MASK 0x2u
395 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_DATA_PIPELINE_EN_MASK 0x4u
397 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_WRITE_ADDR_PIPELINE_EN_MASK 0x8u
399 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_DATA_WAIT_EN_MASK 0x10u
401 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_READ_ADDR_PIPELINE_EN_MASK 0x20u
403 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_DATA_PIPELINE_EN_MASK 0x40u
405 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_S_WRITE_ADDR_PIPELINE_EN_MASK 0x80u
407 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_DATA_WAIT_EN_MASK 0x100u
409 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_READ_ADDR_PIPELINE_EN_MASK 0x200u
411 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_DATA_PIPELINE_EN_MASK 0x400u
413 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_EPDC_WRITE_ADDR_PIPELINE_EN_MASK 0x800u
415 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_DATA_WAIT_EN_MASK 0x1000u
417 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_READ_ADDR_PIPELINE_EN_MASK 0x2000u
419 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_DATA_PIPELINE_EN_MASK 0x4000u
421 #define IOMUXC_GPR_GPR3_GPR_OCRAM_CTRL_PXP_WRITE_ADDR_PIPELINE_EN_MASK 0x8000u
423 #define IOMUXC_GPR_GPR3_ocram_ctrl_read_data_wait_en_update_pending_MASK 0x10000u
425 #define IOMUXC_GPR_GPR3_ocram_ctrl_read_addr_pipeline_en_update_pending_MASK 0x20000u
427 #define IOMUXC_GPR_GPR3_ocram_ctrl_write_data_pipeline_en_update_pending_MASK 0x40000u
429 #define IOMUXC_GPR_GPR3_ocram_ctrl_write_addr_pipeline_en_update_pending_MASK 0x80000u
431 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_data_wait_en_update_pending_MASK 0x100000u
433 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_read_addr_pipeline_en_update_pending_MASK 0x200000u
435 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_data_pipeline_en_update_pending_MASK 0x400000u
437 #define IOMUXC_GPR_GPR3_ocram_ctrl_s_write_addr_pipeline_en_update_pending_MASK 0x800000u
439 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_data_wait_en_update_pending_MASK 0x1000000u
441 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_read_addr_pipeline_en_update_pending_MASK 0x2000000u
443 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_data_pipeline_en_update_pending_MASK 0x4000000u
445 #define IOMUXC_GPR_GPR3_ocram_ctrl_epdc_write_addr_pipeline_en_update_pending_MASK 0x8000000u
447 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_data_wait_en_update_pending_MASK 0x10000000u
449 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_read_addr_pipeline_en_update_pending_MASK 0x20000000u
451 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_data_pipeline_en_update_pending_MASK 0x40000000u
453 #define IOMUXC_GPR_GPR3_ocram_ctrl_pxp_write_addr_pipeline_en_update_pending_MASK 0x80000000u
456 #define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_MASK 0x1u
457 #define IOMUXC_GPR_GPR4_GPR_SDMA_IPG_STOP_SHIFT 0
458 #define IOMUXC_GPR_GPR4_GPR_CAN1_IPG_STOP_MASK 0x2u
460 #define IOMUXC_GPR_GPR4_GPR_CAN2_IPG_STOP_MASK 0x4u
462 #define IOMUXC_GPR_GPR4_GPR_ENET1_IPG_STOP_MASK 0x8u
464 #define IOMUXC_GPR_GPR4_GPR_ENET2_IPG_STOP_MASK 0x10u
466 #define IOMUXC_GPR_GPR4_GPR_SAI1_IPG_STOP_MASK 0x20u
468 #define IOMUXC_GPR_GPR4_GPR_SAI2_IPG_STOP_MASK 0x40u
470 #define IOMUXC_GPR_GPR4_GPR_SAI3_IPG_STOP_MASK 0x80u
472 #define IOMUXC_GPR_GPR4_sdma_ipg_stop_ack_MASK 0x10000u
474 #define IOMUXC_GPR_GPR4_can1_ipg_stop_ack_MASK 0x20000u
476 #define IOMUXC_GPR_GPR4_can2_ipg_stop_ack_MASK 0x40000u
478 #define IOMUXC_GPR_GPR4_enet1_ipg_stop_ack_MASK 0x80000u
480 #define IOMUXC_GPR_GPR4_enet2_ipg_stop_ack_MASK 0x100000u
482 #define IOMUXC_GPR_GPR4_sai1_ipg_stop_ack_MASK 0x200000u
484 #define IOMUXC_GPR_GPR4_sai2_ipg_stop_ack_MASK 0x400000u
486 #define IOMUXC_GPR_GPR4_sai3_ipg_stop_ack_MASK 0x800000u
488 #define IOMUXC_GPR_GPR4_cpu_STANDBYWFI_MASK 0x6000000u
491 #define IOMUXC_GPR_GPR4_cpu_STANDBYWFE_MASK 0x18000000u
495 #define IOMUXC_GPR_GPR5_GPR_CSI_MUX_CONTROL_MASK 0x10u
497 #define IOMUXC_GPR_GPR5_GPR_LVDS_MUX_CONTROL_MASK 0x20u
499 #define IOMUXC_GPR_GPR5_GPR_WDOG1_MASK_MASK 0x40u
501 #define IOMUXC_GPR_GPR5_GPR_WDOG2_MASK_MASK 0x80u
503 #define IOMUXC_GPR_GPR5_GPR_LCDIF_HANDSHAKE_MASK 0x1000u
505 #define IOMUXC_GPR_GPR5_GPR_PCIE_BTNRST_MASK 0x80000u
507 #define IOMUXC_GPR_GPR5_GPR_WDOG3_MASK_MASK 0x100000u
509 #define IOMUXC_GPR_GPR5_GPR_LCDIF_CSI_VSYNC_SEL_MASK 0x200000u
511 #define IOMUXC_GPR_GPR5_GPR_WDOG4_MASK_MASK 0x400000u
513 #define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN1_SEL_MASK 0x1000000u
515 #define IOMUXC_GPR_GPR5_GPR_GPT4_CAPIN2_SEL_MASK 0x2000000u
517 #define IOMUXC_GPR_GPR5_GPR_ENET1_EVENT3IN_SEL_MASK 0x4000000u
519 #define IOMUXC_GPR_GPR5_GPR_ENET2_EVENT3IN_SEL_MASK 0x8000000u
521 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT1_MASK 0x10000000u
523 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT2_MASK 0x20000000u
525 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT3_MASK 0x40000000u
527 #define IOMUXC_GPR_GPR5_GPR_REF_1M_CLK_GPT4_MASK 0x80000000u
530 #define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_MASK 0x1u
531 #define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_SHIFT 0
532 #define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_MASK 0x2u
534 #define IOMUXC_GPR_GPR6_GPR_ARCACHE_PXP6_EN_MASK 0x4u
536 #define IOMUXC_GPR_GPR6_GPR_AWCACHE_PXP6_EN_MASK 0x8u
539 #define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_MASK 0x1u
540 #define IOMUXC_GPR_GPR7_GPR_chd1_pwd_ldo_usb_1p0_SHIFT 0
541 #define IOMUXC_GPR_GPR7_GPR_chd1_lowpwr_ldo_usb_1p0_MASK 0x2u
543 #define IOMUXC_GPR_GPR7_GPR_chd1_en_ilimit_ldo_usb_1p0_MASK 0x4u
545 #define IOMUXC_GPR_GPR7_GPR_chd1_en_pwrupload_ldo_usb_1p0_MASK 0x8u
547 #define IOMUXC_GPR_GPR7_GPR_chd1_chrg_det_test_MASK 0x30u
550 #define IOMUXC_GPR_GPR7_GPR_chd2_pwd_ldo_usb_1p0_MASK 0x40u
552 #define IOMUXC_GPR_GPR7_GPR_chd2_lowpwr_ldo_usb_1p0_MASK 0x80u
554 #define IOMUXC_GPR_GPR7_GPR_chd2_en_ilimit_ldo_usb_1p0_MASK 0x100u
556 #define IOMUXC_GPR_GPR7_GPR_chd2_en_pwrupload_ldo_usb_1p0_MASK 0x200u
558 #define IOMUXC_GPR_GPR7_GPR_chd2_chrg_det_test_MASK 0xC00u
561 #define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_lnkrst_disable_MASK 0x1000u
563 #define IOMUXC_GPR_GPR7_GPR_pcie_clk_rst_fix_perst_disable_MASK 0x2000u
566 #define IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up_MASK 0xF8u
569 #define IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_MASK 0x100u
572 #define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_MASK 0x1u
573 #define IOMUXC_GPR_GPR9_GPR_TZASC1_MUX_CONTROL_SHIFT 0
574 #define IOMUXC_GPR_GPR9_ddr_phy_ctrl_pd_MASK 0x3Eu
578 #define IOMUXC_GPR_GPR10_GPR0_BF0_MASK 0x1u
579 #define IOMUXC_GPR_GPR10_GPR0_BF0_SHIFT 0
580 #define IOMUXC_GPR_GPR10_GPR_DBG_EN_MASK 0x2u
582 #define IOMUXC_GPR_GPR10_GPR_SEC_ERR_RESP_EN_MASK 0x4u
584 #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION0_MASK 0x8u
586 #define IOMUXC_GPR_GPR10_GPR_OCRAM_CTRL_EPDC_OCRAM_TZ_SECURE_REGION1_MASK 0x3F0u
590 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_MASK 0x1u
591 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION0_SHIFT 0
592 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_OCRAM_TZ_SECURE_REGION1_MASK 0x3Eu
595 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION0_MASK 0x40u
597 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_PXP_OCRAM_TZ_SECURE_REGION1_MASK 0x380u
600 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION0_MASK 0x400u
602 #define IOMUXC_GPR_GPR11_GPR_OCRAM_CTRL_S_OCRAM_TZ_SECURE_REGION1_MASK 0x3800u
606 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_MASK 0x1u
607 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_REG_RST_CH0_SHIFT 0
608 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_TRSV_RST_CH0_MASK 0x2u
610 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_SSC_EN_MASK 0x8u
612 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_CMN_REG_RST_MASK 0x10u
614 #define IOMUXC_GPR_GPR12_GPR_PCIE_PHY_REFCLK_SEL_MASK 0x20u
616 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DEVICE_TYPE_MASK 0xF000u
619 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_STATUS_BUS_SELECT_MASK 0x1E0000u
622 #define IOMUXC_GPR_GPR12_GPR_PCIE_CTRL_DIAG_CTRL_BUS_MASK 0xE00000u
626 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_MASK 0x1u
627 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_USDHC_SHIFT 0
628 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_USDHC_MASK 0x2u
630 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_MASK 0x4u
632 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_MASK 0x8u
634 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_MASK 0x10u
636 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_MASK 0x20u
638 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_MASK 0x40u
640 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_MASK 0x80u
642 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PXP_EN_MASK 0x100u
644 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PXP_EN_MASK 0x200u
646 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_PCIE_EN_MASK 0x400u
648 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_PCIE_EN_MASK 0x800u
650 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_LCDIF_EN_MASK 0x1000u
652 #define IOMUXC_GPR_GPR13_GPR_ARCACHE_EPDC_EN_MASK 0x2000u
654 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_MASK 0x4000u
656 #define IOMUXC_GPR_GPR13_GPR_AWCACHE_EPDC_EN_MASK 0x8000u
658 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_AFC_CODE_OUT_CH0_MASK 0xFF0000u
661 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_VCO_BAND_MASK 0xF000000u
664 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_CDR_LOCKED_CH0_MASK 0x10000000u
666 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PMA_RX_PRESENT_CH0_MASK 0x20000000u
668 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_CDR_VCO_MON_CH0_MASK 0x40000000u
670 #define IOMUXC_GPR_GPR13_GPR_PCIE_PHY_PCS_REFCLK_DISABLE_MASK 0x80000000u
673 #define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_MASK 0x1u
674 #define IOMUXC_GPR_GPR14_GPR_SIM1_SIMV2_EMV_SEL_SHIFT 0
675 #define IOMUXC_GPR_GPR14_GPR_SIM2_SIMV2_EMV_SEL_MASK 0x2u
678 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_MASK 0x1u
679 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_VBLK_FLAG_SHIFT 0
680 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_AUTO_SEL_MASK 0x2u
682 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_DESKEW_CNT_SET_MASK 0x3FFCu
685 #define IOMUXC_GPR_GPR15_GPR_LVDS_I_LOCK_PPM_SET_MASK 0x3F0000u
689 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_MASK 0x3u
690 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_REG_CUR_SHIFT 0
692 #define IOMUXC_GPR_GPR16_GPR_LVDS_SEL_DATABF_MASK 0x4u
694 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNTB_TDLY_MASK 0x8u
696 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEW_EN_H_MASK 0x10u
698 #define IOMUXC_GPR_GPR16_GPR_LVDS_SKEWINI_MASK 0x20u
700 #define IOMUXC_GPR_GPR16_GPR_LVDS_SK_BIAS_MASK 0x3C0u
703 #define IOMUXC_GPR_GPR16_GPR_LVDS_AUTO_DSK_SEL_MASK 0x400u
705 #define IOMUXC_GPR_GPR16_GPR_LVDS_LOCK_CNT_MASK 0x800u
707 #define IOMUXC_GPR_GPR16_GPR_LVDS_OUTCON_MASK 0x1000u
709 #define IOMUXC_GPR_GPR16_GPR_LVDS_FC_CODE_MASK 0xE000u
712 #define IOMUXC_GPR_GPR16_GPR_LVDS_SRC_TRH_MASK 0x10000u
714 #define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_HIGH_S_MASK 0x20000u
716 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_CNT_MASK 0x180000u
719 #define IOMUXC_GPR_GPR16_GPR_LVDS_CNNCT_MODE_SEL_MASK 0x200000u
721 #define IOMUXC_GPR_GPR16_GPR_LVDS_FLT_CNT_MASK 0x400000u
723 #define IOMUXC_GPR_GPR16_GPR_LVDS_VOD_ONLY_CNT_MASK 0x800000u
726 #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_MASK 0xFFu
727 #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_PEN_H_SHIFT 0
729 #define IOMUXC_GPR_GPR17_GPR_LVDS_CNT_VOD_H_MASK 0xFF00u
733 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_MASK 0x7u
734 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CH_SEL_SHIFT 0
736 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_DATA_INV_MASK 0x18u
739 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_CLK_INV_MASK 0x60u
742 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_SKEW_CTRL_MASK 0x3F00u
745 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_FORCE_ERROR_MASK 0x4000u
747 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_USER_PATTERN_MASK 0x7F0000u
750 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_PAT_SEL_MASK 0x3000000u
753 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_EN_MASK 0x4000000u
755 #define IOMUXC_GPR_GPR18_GPR_LVDS_I_BIST_RESETB_MASK 0x8000000u
757 #define IOMUXC_GPR_GPR18_GPR_LVDS_DLYS_BST_MASK 0x10000000u
759 #define IOMUXC_GPR_GPR18_GPR_LVDS_SKINI_BST_MASK 0x20000000u
762 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_MASK 0x1u
763 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_STATUS_SHIFT 0
764 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_ERR_COUNT_MASK 0xFF00u
767 #define IOMUXC_GPR_GPR19_GPR_LVDS_O_BIST_SYNC_MASK 0x10000u
769 #define IOMUXC_GPR_GPR19_GPR_LVDS_MON_FOR_CNNCT_MASK 0x20000u
772 #define IOMUXC_GPR_GPR20_GPR_LVDS_P_MASK 0x3Fu
773 #define IOMUXC_GPR_GPR20_GPR_LVDS_P_SHIFT 0
775 #define IOMUXC_GPR_GPR20_GPR_LVDS_M_MASK 0x3F00u
778 #define IOMUXC_GPR_GPR20_GPR_LVDS_S_MASK 0x30000u
781 #define IOMUXC_GPR_GPR20_GPR_LVDS_VSEL_MASK 0x1000000u
783 #define IOMUXC_GPR_GPR20_GPR_LVDS_CK_POL_SEL_MASK 0x2000000u
785 #define IOMUXC_GPR_GPR20_GPR_LVDS_I_TX2801X_DUMMY_MASK 0x38000000u
789 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_MASK 0x7u
790 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC0_SHIFT 0
792 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC1_MASK 0x38u
795 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC2_MASK 0x1C0u
798 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKCCK_MASK 0xE00u
801 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC3_MASK 0x7000u
804 #define IOMUXC_GPR_GPR21_GPR_LVDS_SKC4_MASK 0x38000u
807 #define IOMUXC_GPR_GPR21_SJC_BYPASS_CJTAGC_MASK 0x40000u
809 #define IOMUXC_GPR_GPR21_DAP_BYPASS_CJTAGC_MASK 0x80000u
812 #define IOMUXC_GPR_GPR22_ddrc_mrr_data_out_MASK 0xFF0000u
815 #define IOMUXC_GPR_GPR22_ddrc_mrr_valid_out_MASK 0x1000000u
817 #define IOMUXC_GPR_GPR22_ddr_phy_dfi_init_complete_MASK 0x2000000u
819 #define IOMUXC_GPR_GPR22_GPR_chd2_dvdd_usb_stable_MASK 0x4000000u
821 #define IOMUXC_GPR_GPR22_aux_chrg_det_2_usb_iso_enable_1_MASK 0x8000000u
823 #define IOMUXC_GPR_GPR22_GPR_chd1_dvdd_usb_stable_MASK 0x10000000u
825 #define IOMUXC_GPR_GPR22_aux_chrg_det_1_usb_iso_enable_1_MASK 0x20000000u
827 #define IOMUXC_GPR_GPR22_GPR_PCIE_PHY_PLL_LOCKED_MASK 0x80000000u
830 #define IMX7D_GPR5_CSI1_MUX_CTRL_MASK (0x1 << 4)
831 #define IMX7D_GPR5_CSI1_MUX_CTRL_PARALLEL_CSI (0x0 << 4)
832 #define IMX7D_GPR5_CSI1_MUX_CTRL_MIPI_CSI (0x1 << 4)
840 u32 gpr[23]; /* 0x000 */
859 #define MXC_CSPICTRL_EN (1 << 0)
862 #define MXC_CSPICTRL_MODE_MASK (0xf << 4)
863 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
864 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
865 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
866 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
867 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
868 #define MXC_CSPICTRL_MAXBITS 0xfff
878 #define MXC_CSPICON_PHA 0 /* SCLK phase control */
889 #define CSU_INIT_SEC_LEVEL0 0x00FF00FF
928 u32 rsvd13[0xc3];
930 struct fuse_bank { /* offset 0x400 */
931 u32 fuse_regs[0x10];
1002 u32 rsvd[0xe];
1063 #define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x1f << 21)
1070 #define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0x3 << 14)
1072 #define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3 << 12)
1074 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0x3 << 10)
1076 #define LCDIF_CTRL_LCD_DATABUS_WIDTH_16BIT (0 << 10)
1080 #define LCDIF_CTRL_WORD_LENGTH_MASK (0x3 << 8)
1082 #define LCDIF_CTRL_WORD_LENGTH_16BIT (0 << 8)
1091 #define LCDIF_CTRL_RUN (1 << 0)
1101 #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16)
1113 #define LCDIF_CTRL1_RESET (1 << 0)
1115 #define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0x7 << 21)
1117 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_1 (0x0 << 21)
1118 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_2 (0x1 << 21)
1119 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_4 (0x2 << 21)
1120 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_8 (0x3 << 21)
1121 #define LCDIF_CTRL2_OUTSTANDING_REQS_REQ_16 (0x4 << 21)
1123 #define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x7 << 16)
1125 #define LCDIF_CTRL2_ODD_LINE_PATTERN_RGB (0x0 << 16)
1126 #define LCDIF_CTRL2_ODD_LINE_PATTERN_RBG (0x1 << 16)
1127 #define LCDIF_CTRL2_ODD_LINE_PATTERN_GBR (0x2 << 16)
1128 #define LCDIF_CTRL2_ODD_LINE_PATTERN_GRB (0x3 << 16)
1129 #define LCDIF_CTRL2_ODD_LINE_PATTERN_BRG (0x4 << 16)
1130 #define LCDIF_CTRL2_ODD_LINE_PATTERN_BGR (0x5 << 16)
1131 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7 << 12)
1133 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_RGB (0x0 << 12)
1134 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_RBG (0x1 << 12)
1135 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_GBR (0x2 << 12)
1136 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_GRB (0x3 << 12)
1137 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_BRG (0x4 << 12)
1138 #define LCDIF_CTRL2_EVEN_LINE_PATTERN_BGR (0x5 << 12)
1142 #define LCDIF_CTRL2_READ_MODE_NUM_PACKED_SUBWORDS_MASK (0x7 << 4)
1144 #define LCDIF_CTRL2_INITIAL_DUMMY_READ_MASK (0x7 << 1)
1147 #define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16)
1149 #define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0)
1150 #define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0
1152 #define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff
1153 #define LCDIF_CUR_BUF_ADDR_OFFSET 0
1155 #define LCDIF_NEXT_BUF_ADDR_MASK 0xffffffff
1156 #define LCDIF_NEXT_BUF_ADDR_OFFSET 0
1158 #define LCDIF_TIMING_CMD_HOLD_MASK (0xff << 24)
1160 #define LCDIF_TIMING_CMD_SETUP_MASK (0xff << 16)
1162 #define LCDIF_TIMING_DATA_HOLD_MASK (0xff << 8)
1164 #define LCDIF_TIMING_DATA_SETUP_MASK (0xff << 0)
1165 #define LCDIF_TIMING_DATA_SETUP_OFFSET 0
1177 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff
1178 #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0
1180 #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff
1181 #define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0
1183 #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18)
1185 #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff
1186 #define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0
1190 #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16)
1192 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0)
1193 #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0
1195 #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29)
1198 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff
1199 #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0
1210 #define is_boot_from_usb(void) (readl(USBOTG1_IPS_BASE_ADDR + 0x158) || \
1211 readl(USBOTG2_IPS_BASE_ADDR + 0x158))
1212 #define disconnect_from_pc(void) writel(0x0, USBOTG1_IPS_BASE_ADDR + 0x140)