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/openbmc/linux/drivers/net/ethernet/dec/tulip/
H A Deeprom.c29 {"Asante", 0, 0, 0x94, {0x1e00, 0x0000, 0x0800, 0x0100, 0x018c,
30 0x0000, 0x0000, 0xe078, 0x0001, 0x0050, 0x0018 }},
31 {"SMC9332DST", 0, 0, 0xC0, { 0x1e00, 0x0000, 0x0800, 0x041f,
32 0x0000, 0x009E, /* 10baseT */
33 0x0004, 0x009E, /* 10baseT-FD */
34 0x0903, 0x006D, /* 100baseTx */
35 0x0905, 0x006D, /* 100baseTx-FD */ }},
36 {"Cogent EM100", 0, 0, 0x92, { 0x1e00, 0x0000, 0x0800, 0x063f,
37 0x0107, 0x8021, /* 100baseFx */
38 0x0108, 0x8021, /* 100baseFx-FD */
[all …]
/openbmc/linux/arch/riscv/include/asm/
H A Dkvm_aia_aplic.h14 #define APLIC_DOMAINCFG 0x0000
15 #define APLIC_DOMAINCFG_RDONLY 0x80000000
18 #define APLIC_DOMAINCFG_BE BIT(0)
20 #define APLIC_SOURCECFG_BASE 0x0004
22 #define APLIC_SOURCECFG_CHILDIDX_MASK 0x000003ff
23 #define APLIC_SOURCECFG_SM_MASK 0x00000007
24 #define APLIC_SOURCECFG_SM_INACTIVE 0x0
25 #define APLIC_SOURCECFG_SM_DETACH 0x1
26 #define APLIC_SOURCECFG_SM_EDGE_RISE 0x4
27 #define APLIC_SOURCECFG_SM_EDGE_FALL 0x5
[all …]
/openbmc/linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/
H A Ddcore0_tpc0_eml_spmu_regs.h23 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR0_EL0 0x1000
25 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR1_EL0 0x1008
27 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR2_EL0 0x1010
29 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR3_EL0 0x1018
31 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR4_EL0 0x1020
33 #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR5_EL0 0x1028
35 #define mmDCORE0_TPC0_EML_SPMU_PMCCNTR_L_EL0 0x10F8
37 #define mmDCORE0_TPC0_EML_SPMU_PMCCNTR_H_EL0 0x10FC
39 #define mmDCORE0_TPC0_EML_SPMU_PMTRC 0x1200
41 #define mmDCORE0_TPC0_EML_SPMU_TRC_CTRL_HOST 0x1204
[all …]
/openbmc/linux/sound/soc/codecs/
H A Drt722-sdca.c36 if (ret < 0) in rt722_sdca_index_write()
52 if (ret < 0) in rt722_sdca_index_read()
67 if (ret < 0) in rt722_sdca_index_update_bits()
76 if ((*buffer & 0xf0) == 0x10 || (*buffer & 0x0f) == 0x01 || (*(buffer + 1) == 0x01) || in rt722_sdca_btn_type()
77 (*(buffer + 1) == 0x10)) in rt722_sdca_btn_type()
79 else if ((*buffer & 0xf in rt722_sdca_btn_type()
[all...]
H A Drt1011.c37 { RT1011_POWER_9, 0xa840 },
39 { RT1011_ADC_SET_5, 0x0a20 },
40 { RT1011_DAC_SET_2, 0xa032 },
42 { RT1011_SPK_PRO_DC_DET_1, 0xb00c },
43 { RT1011_SPK_PRO_DC_DET_2, 0xcccc },
45 { RT1011_A_TIMING_1, 0x6054 },
47 { RT1011_POWER_7, 0x3e55 },
48 { RT1011_POWER_8, 0x0520 },
49 { RT1011_BOOST_CON_1, 0xe188 },
50 { RT1011_POWER_4, 0x16f2 },
[all …]
H A Drt712-sdca.c35 if (ret < 0) in rt712_sdca_index_write()
51 if (ret < 0) in rt712_sdca_index_read()
66 if (ret < 0) in rt712_sdca_index_update_bits()
75 unsigned int val, loop_rc = 0, loop_dc = 0; in rt712_sdca_calibration()
79 int ret = 0; in rt712_sdca_calibration()
85 rt712_sdca_index_write(rt712, RT712_VENDOR_REG, RT712_CC_DET1, 0x043a); in rt712_sdca_calibration()
88 rt712_sdca_index_write(rt712, RT712_VENDOR_REG, RT712_FSM_CTL, 0x4100); in rt712_sdca_calibration()
91 rt712_sdca_index_write(rt712, RT712_VENDOR_CALI, RT712_DAC_DC_CALI_CTL1, 0x7883); in rt712_sdca_calibration()
94 rt712_sdca_index_write(rt712, RT712_VENDOR_CALI, RT712_DAC_DC_CALI_CTL1, 0xf893); in rt712_sdca_calibration()
100 for (loop_dc = 0; loop_dc < chk_cnt && in rt712_sdca_calibration()
[all …]
/openbmc/u-boot/board/freescale/common/
H A Dcds_via.c17 pci_hose_write_config_byte(hose, dev, 0x48, 0x08); in mpc85xx_config_via()
22 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); in mpc85xx_config_via()
23 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); in mpc85xx_config_via()
27 * open from 0x00000000-0x00001fff in PCI I/O space. in mpc85xx_config_via()
31 bridge = PCI_BDF(0,BRIDGE_ID,0); in mpc85xx_config_via()
32 pci_hose_write_config_byte(hose, bridge, PCI_IO_BASE, 0); in mpc85xx_config_via()
33 pci_hose_write_config_word(hose, bridge, PCI_IO_BASE_UPPER16, 0); in mpc85xx_config_via()
34 pci_hose_write_config_byte(hose, bridge, PCI_IO_LIMIT, 0x10); in mpc85xx_config_via()
35 pci_hose_write_config_word(hose, bridge, PCI_IO_LIMIT_UPPER16, 0); in mpc85xx_config_via()
49 pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0x1ff8); in mpc85xx_config_via_usbide()
[all …]
/openbmc/linux/drivers/gpu/drm/i915/soc/
H A Dintel_pch.h19 PCH_NONE = 0, /* No PCH present */
35 #define INTEL_PCH_DEVICE_ID_MASK 0xff80
36 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
37 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
38 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
39 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
40 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
41 #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80
42 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80
43 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dbrcm,sata-phy.yaml46 const: 0
49 "^sata-phy@[0-9]+$":
60 const: 0
83 minimum: 0
130 reg = <0xf0458100 0x1e00>;
133 #size-cells = <0>;
135 sata-phy@0 {
136 reg = <0>;
137 #phy-cells = <0>;
142 #phy-cells = <0>;
/openbmc/u-boot/fs/ext4/
H A Dcrc16.c13 /** CRC table for the CRC-16. The poly is 0x8005 (x16 + x15 + x2 + 1) */
15 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
16 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
17 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
18 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
19 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
20 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
21 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
22 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
23 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/openbmc/linux/lib/
H A Dcrc16.c10 /** CRC table for the CRC-16. The poly is 0x8005 (x^16 + x^15 + x^2 + 1) */
12 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
13 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
14 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
15 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
16 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
17 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
18 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
19 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
20 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/openbmc/u-boot/fs/ubifs/
H A Dcrc16.c11 /** CRC table for the CRC-16. The poly is 0x8005 (x^16 + x^15 + x^2 + 1) */
13 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
14 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
15 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
16 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
17 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
18 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
19 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
20 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
21 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
[all …]
/openbmc/u-boot/include/pcmcia/
H A Dyenta.h35 #define PCI_STATUS_CAPLIST 0x10
36 #define PCI_CB_CAPABILITY_POINTER 0x14 /* 8 bit */
37 #define PCI_CAPABILITY_ID 0x00 /* 8 bit */
38 #define PCI_CAPABILITY_PM 0x01
39 #define PCI_NEXT_CAPABILITY 0x01 /* 8 bit */
40 #define PCI_PM_CAPABILITIES 0x02 /* 16 bit */
41 #define PCI_PMCAP_PME_D3COLD 0x8000
42 #define PCI_PMCAP_PME_D3HOT 0x4000
43 #define PCI_PMCAP_PME_D2 0x2000
44 #define PCI_PMCAP_PME_D1 0x1000
[all …]
/openbmc/linux/arch/mips/include/asm/mach-ar7/
H A Dar7.h16 #define AR7_SDRAM_BASE 0x14000000
18 #define AR7_REGS_BASE 0x08610000
20 #define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000)
21 #define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900)
22 /* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */
23 #define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00)
24 #define AR7_REGS_CLOCKS (AR7_REGS_POWER + 0x80)
25 #define UR8_REGS_CLOCKS (AR7_REGS_POWER + 0x20)
26 #define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
27 #define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
[all …]
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/
H A Diwl-context-info.h11 #define CSR_CTXT_INFO_BA 0x40
38 IWL_CTXT_INFO_AUTO_FUNC_INIT = 0x0001,
39 IWL_CTXT_INFO_EARLY_DEBUG = 0x0002,
40 IWL_CTXT_INFO_ENABLE_CDMP = 0x0004,
41 IWL_CTXT_INFO_RB_CB_SIZE = 0x00f0,
42 IWL_CTXT_INFO_TFD_FORMAT_LONG = 0x0100,
43 IWL_CTXT_INFO_RB_SIZE = 0x1e00,
44 IWL_CTXT_INFO_RB_SIZE_1K = 0x1,
45 IWL_CTXT_INFO_RB_SIZE_2K = 0x2,
46 IWL_CTXT_INFO_RB_SIZE_4K = 0x4,
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dadder875-redboot.dts24 #size-cells = <0>;
26 PowerPC,875@0 {
28 reg = <0>;
33 timebase-frequency = <0>;
34 bus-frequency = <0>;
35 clock-frequency = <0>;
43 reg = <0 0x01000000>;
51 reg = <0xfa200100 0x40>;
54 0 0 0xfe000000 0x00800000
55 2 0 0xfa100000 0x00008000
[all …]
H A Dadder875-uboot.dts24 #size-cells = <0>;
26 PowerPC,875@0 {
28 reg = <0>;
33 timebase-frequency = <0>;
34 bus-frequency = <0>;
35 clock-frequency = <0>;
43 reg = <0 0x01000000>;
51 reg = <0xff000100 0x40>;
54 0 0 0xfe000000 0x01000000
57 flash@0,0 {
[all …]
H A Dep88xc.dts19 #size-cells = <0>;
21 PowerPC,885@0 {
23 reg = <0x0>;
28 timebase-frequency = <0>;
29 bus-frequency = <0>;
30 clock-frequency = <0>;
38 reg = <0x0 0x0>;
45 reg = <0xfa200100 0x40>;
48 0x0 0x0 0xfc000000 0x4000000
49 0x3 0x0 0xfa000000 0x1000000
[all …]
/openbmc/linux/tools/testing/selftests/intel_pstate/
H A Drun.sh12 # and the value of MSR 0x199 (MSR_IA32_PERF_CTL) which indicates what
24 #/tmp/result.3100:3:msr 0x199: 0x1e00
31 EVALUATE_ONLY=0
37 echo "$0 # Skipped: Test can only run on x86 architectures."
42 if [ $UID != 0 ] && [ $EVALUATE_ONLY == 0 ]; then
52 for cpu in `seq 0 $max_cpus`
67 ./msr 0 >> /tmp/result.$1
86 mkt_freq=${_mkt_freq}0
95 [ $EVALUATE_ONLY -eq 0 ] && for freq in `seq $max_freq -100 $min_freq`
102 [ $EVALUATE_ONLY -eq 0 ] && cpupower frequency-set -g powersave --max=${max_freq}MHz >& /dev/null
[all …]
/openbmc/linux/fs/ntfs/
H A Dupcase.c16 {0x0061, 0x007B, -32}, {0x0451, 0x045D, -80}, {0x1F70, 0x1F72, 74}, in generate_default_upcase()
17 {0x00E0, 0x00F7, -32}, {0x045E, 0x0460, -80}, {0x1F72, 0x1F76, 86}, in generate_default_upcase()
18 {0x00F8, 0x00FF, -32}, {0x0561, 0x0587, -48}, {0x1F76, 0x1F78, 100}, in generate_default_upcase()
19 {0x0256, 0x0258, -205}, {0x1F00, 0x1F08, 8}, {0x1F78, 0x1F7A, 128}, in generate_default_upcase()
20 {0x028A, 0x028C, -217}, {0x1F10, 0x1F16, 8}, {0x1F7A, 0x1F7C, 112}, in generate_default_upcase()
21 {0x03AC, 0x03AD, -38}, {0x1F20, 0x1F28, 8}, {0x1F7C, 0x1F7E, 126}, in generate_default_upcase()
22 {0x03AD, 0x03B0, -37}, {0x1F30, 0x1F38, 8}, {0x1FB0, 0x1FB2, 8}, in generate_default_upcase()
23 {0x03B1, 0x03C2, -32}, {0x1F40, 0x1F46, 8}, {0x1FD0, 0x1FD2, 8}, in generate_default_upcase()
24 {0x03C2, 0x03C3, -31}, {0x1F51, 0x1F52, 8}, {0x1FE0, 0x1FE2, 8}, in generate_default_upcase()
25 {0x03C3, 0x03CC, -32}, {0x1F53, 0x1F54, 8}, {0x1FE5, 0x1FE6, 7}, in generate_default_upcase()
[all …]
/openbmc/linux/drivers/hsi/controllers/
H A Domap_ssi_regs.h15 #define SSI_REVISION_REG 0
16 # define SSI_REV_MAJOR 0xf0
17 # define SSI_REV_MINOR 0xf
18 #define SSI_SYSCONFIG_REG 0x10
19 # define SSI_AUTOIDLE (1 << 0)
21 # define SSI_SIDLEMODE_FORCE 0
24 # define SSI_SIDLEMODE_MASK 0x18
25 # define SSI_MIDLEMODE_FORCE 0
28 # define SSI_MIDLEMODE_MASK 0x3000
29 #define SSI_SYSSTATUS_REG 0x14
[all …]
/openbmc/linux/drivers/block/
H A Dswim_asm.S17 .equ write_data, 0x0000
18 .equ write_mark, 0x0200
19 .equ write_CRC, 0x0400
20 .equ write_parameter,0x0600
21 .equ write_phase, 0x0800
22 .equ write_setup, 0x0a00
23 .equ write_mode0, 0x0c00
24 .equ write_mode1, 0x0e00
25 .equ read_data, 0x1000
26 .equ read_mark, 0x1200
[all …]
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dmxc_nand.h30 #define is_mxc_nfc_21() 0
31 #define is_mxc_nfc_32() 0
34 #define is_mxc_nfc_1() 0
36 #define is_mxc_nfc_32() 0
40 #define is_mxc_nfc_1() 0
41 #define is_mxc_nfc_21() 0
51 #define NAND_MXC_REG_OFFSET 0xe00
56 #define NAND_MXC_REG_OFFSET 0x1e00
60 u8 main_area[NAND_MXC_NR_BUFS][0x200];
128 /* Set FCMD to 1, rest to 0 for Command operation */
[all …]
/openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dfiji_smumgr.c54 #define FIJI_SMC_SIZE 0x20000
58 #define MC_CG_ARB_FREQ_F1 0x0b
64 {600, 1050, 3, 0}, {600, 1050, 6, 1} };
70 { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
73 /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%]
77 {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} };
81 {1, 0xF, 0xFD,
83 0x19, 5, 45}
89 …0x3c0fd047, 0x30750000, 0x00, 0x03, 0x1e00, 0x00200410, 0x87020000, 0x21680000, 0x0c000000…
90 …0xa00fd047, 0x409c0000, 0x01, 0x04, 0x1e00, 0x00800510, 0x87020000, 0x21680000, 0x11000000…
[all …]
/openbmc/linux/drivers/gpu/drm/rockchip/
H A Drockchip_vop2_reg.c103 .id = 0,
109 .offset = 0xc00,
115 .offset = 0xd00,
121 .offset = 0xe00,
146 .base = 0x1c00,
162 .base = 0x1e00,
175 .base = 0x1a00,
188 .base = 0x1800,
198 .base = 0x1000,
202 .layer_sel_id = 0,
[all …]

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