1fd534e9bSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 27ca5dc14SFlorian Fainelli /* 37ca5dc14SFlorian Fainelli * Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org> 47ca5dc14SFlorian Fainelli * Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org> 57ca5dc14SFlorian Fainelli */ 67ca5dc14SFlorian Fainelli 77ca5dc14SFlorian Fainelli #ifndef __AR7_H__ 87ca5dc14SFlorian Fainelli #define __AR7_H__ 97ca5dc14SFlorian Fainelli 107ca5dc14SFlorian Fainelli #include <linux/delay.h> 117ca5dc14SFlorian Fainelli #include <linux/io.h> 127ca5dc14SFlorian Fainelli #include <linux/errno.h> 137ca5dc14SFlorian Fainelli 147ca5dc14SFlorian Fainelli #include <asm/addrspace.h> 157ca5dc14SFlorian Fainelli 167ca5dc14SFlorian Fainelli #define AR7_SDRAM_BASE 0x14000000 177ca5dc14SFlorian Fainelli 187ca5dc14SFlorian Fainelli #define AR7_REGS_BASE 0x08610000 197ca5dc14SFlorian Fainelli 207ca5dc14SFlorian Fainelli #define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000) 217ca5dc14SFlorian Fainelli #define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900) 227ca5dc14SFlorian Fainelli /* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */ 237ca5dc14SFlorian Fainelli #define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00) 247ca5dc14SFlorian Fainelli #define AR7_REGS_CLOCKS (AR7_REGS_POWER + 0x80) 257ca5dc14SFlorian Fainelli #define UR8_REGS_CLOCKS (AR7_REGS_POWER + 0x20) 267ca5dc14SFlorian Fainelli #define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00) 277ca5dc14SFlorian Fainelli #define AR7_REGS_USB (AR7_REGS_BASE + 0x1200) 287ca5dc14SFlorian Fainelli #define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600) 29238dd317SFlorian Fainelli #define AR7_REGS_PINSEL (AR7_REGS_BASE + 0x160C) 307ca5dc14SFlorian Fainelli #define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800) 317ca5dc14SFlorian Fainelli #define AR7_REGS_DCL (AR7_REGS_BASE + 0x1a00) 327ca5dc14SFlorian Fainelli #define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00) 337ca5dc14SFlorian Fainelli #define AR7_REGS_MDIO (AR7_REGS_BASE + 0x1e00) 347ca5dc14SFlorian Fainelli #define AR7_REGS_IRQ (AR7_REGS_BASE + 0x2400) 357ca5dc14SFlorian Fainelli #define AR7_REGS_MAC1 (AR7_REGS_BASE + 0x2800) 367ca5dc14SFlorian Fainelli 377ca5dc14SFlorian Fainelli #define AR7_REGS_WDT (AR7_REGS_BASE + 0x1f00) 387ca5dc14SFlorian Fainelli #define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00) 397ca5dc14SFlorian Fainelli #define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00) 407ca5dc14SFlorian Fainelli 41238dd317SFlorian Fainelli /* Titan registers */ 42238dd317SFlorian Fainelli #define TITAN_REGS_ESWITCH_BASE (0x08640000) 43238dd317SFlorian Fainelli #define TITAN_REGS_MAC0 (TITAN_REGS_ESWITCH_BASE) 44238dd317SFlorian Fainelli #define TITAN_REGS_MAC1 (TITAN_REGS_ESWITCH_BASE + 0x0800) 45238dd317SFlorian Fainelli #define TITAN_REGS_MDIO (TITAN_REGS_ESWITCH_BASE + 0x02000) 46238dd317SFlorian Fainelli #define TITAN_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1c00) 47238dd317SFlorian Fainelli #define TITAN_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1300) 48238dd317SFlorian Fainelli 49e1df057dSFlorian Fainelli #define AR7_RESET_PERIPHERAL 0x0 507ca5dc14SFlorian Fainelli #define AR7_RESET_SOFTWARE 0x4 517ca5dc14SFlorian Fainelli #define AR7_RESET_STATUS 0x8 527ca5dc14SFlorian Fainelli 537ca5dc14SFlorian Fainelli #define AR7_RESET_BIT_CPMAC_LO 17 547ca5dc14SFlorian Fainelli #define AR7_RESET_BIT_CPMAC_HI 21 557ca5dc14SFlorian Fainelli #define AR7_RESET_BIT_MDIO 22 567ca5dc14SFlorian Fainelli #define AR7_RESET_BIT_EPHY 26 577ca5dc14SFlorian Fainelli 58238dd317SFlorian Fainelli #define TITAN_RESET_BIT_EPHY1 28 59238dd317SFlorian Fainelli 607ca5dc14SFlorian Fainelli /* GPIO control registers */ 617ca5dc14SFlorian Fainelli #define AR7_GPIO_INPUT 0x0 627ca5dc14SFlorian Fainelli #define AR7_GPIO_OUTPUT 0x4 637ca5dc14SFlorian Fainelli #define AR7_GPIO_DIR 0x8 647ca5dc14SFlorian Fainelli #define AR7_GPIO_ENABLE 0xc 65238dd317SFlorian Fainelli #define TITAN_GPIO_INPUT_0 0x0 66238dd317SFlorian Fainelli #define TITAN_GPIO_INPUT_1 0x4 67238dd317SFlorian Fainelli #define TITAN_GPIO_OUTPUT_0 0x8 68238dd317SFlorian Fainelli #define TITAN_GPIO_OUTPUT_1 0xc 69238dd317SFlorian Fainelli #define TITAN_GPIO_DIR_0 0x10 70238dd317SFlorian Fainelli #define TITAN_GPIO_DIR_1 0x14 71238dd317SFlorian Fainelli #define TITAN_GPIO_ENBL_0 0x18 72238dd317SFlorian Fainelli #define TITAN_GPIO_ENBL_1 0x1c 737ca5dc14SFlorian Fainelli 747ca5dc14SFlorian Fainelli #define AR7_CHIP_7100 0x18 757ca5dc14SFlorian Fainelli #define AR7_CHIP_7200 0x2b 767ca5dc14SFlorian Fainelli #define AR7_CHIP_7300 0x05 77238dd317SFlorian Fainelli #define AR7_CHIP_TITAN 0x07 78238dd317SFlorian Fainelli #define TITAN_CHIP_1050 0x0f 79238dd317SFlorian Fainelli #define TITAN_CHIP_1055 0x0e 80238dd317SFlorian Fainelli #define TITAN_CHIP_1056 0x0d 81238dd317SFlorian Fainelli #define TITAN_CHIP_1060 0x07 827ca5dc14SFlorian Fainelli 837ca5dc14SFlorian Fainelli /* Interrupts */ 847ca5dc14SFlorian Fainelli #define AR7_IRQ_UART0 15 857ca5dc14SFlorian Fainelli #define AR7_IRQ_UART1 16 867ca5dc14SFlorian Fainelli 877ca5dc14SFlorian Fainelli /* Clocks */ 887ca5dc14SFlorian Fainelli #define AR7_AFE_CLOCK 35328000 897ca5dc14SFlorian Fainelli #define AR7_REF_CLOCK 25000000 907ca5dc14SFlorian Fainelli #define AR7_XTAL_CLOCK 24000000 917ca5dc14SFlorian Fainelli 9272838a17SFlorian Fainelli /* DCL */ 9372838a17SFlorian Fainelli #define AR7_WDT_HW_ENA 0x10 9472838a17SFlorian Fainelli 957ca5dc14SFlorian Fainelli struct plat_cpmac_data { 967ca5dc14SFlorian Fainelli int reset_bit; 977ca5dc14SFlorian Fainelli int power_bit; 987ca5dc14SFlorian Fainelli u32 phy_mask; 997ca5dc14SFlorian Fainelli char dev_addr[6]; 1007ca5dc14SFlorian Fainelli }; 1017ca5dc14SFlorian Fainelli 1027ca5dc14SFlorian Fainelli struct plat_dsl_data { 1037ca5dc14SFlorian Fainelli int reset_bit_dsl; 1047ca5dc14SFlorian Fainelli int reset_bit_sar; 1057ca5dc14SFlorian Fainelli }; 1067ca5dc14SFlorian Fainelli ar7_is_titan(void)107238dd317SFlorian Fainellistatic inline int ar7_is_titan(void) 108238dd317SFlorian Fainelli { 109238dd317SFlorian Fainelli return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x24)) & 0xffff) == 110238dd317SFlorian Fainelli AR7_CHIP_TITAN; 111238dd317SFlorian Fainelli } 112238dd317SFlorian Fainelli ar7_chip_id(void)1137ca5dc14SFlorian Fainellistatic inline u16 ar7_chip_id(void) 1147ca5dc14SFlorian Fainelli { 115238dd317SFlorian Fainelli return ar7_is_titan() ? AR7_CHIP_TITAN : (readl((void *) 116238dd317SFlorian Fainelli KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff); 117238dd317SFlorian Fainelli } 118238dd317SFlorian Fainelli titan_chip_id(void)119238dd317SFlorian Fainellistatic inline u16 titan_chip_id(void) 120238dd317SFlorian Fainelli { 121238dd317SFlorian Fainelli unsigned int val = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 122238dd317SFlorian Fainelli TITAN_GPIO_INPUT_1)); 123238dd317SFlorian Fainelli return ((val >> 12) & 0x0f); 1247ca5dc14SFlorian Fainelli } 1257ca5dc14SFlorian Fainelli ar7_chip_rev(void)1267ca5dc14SFlorian Fainellistatic inline u8 ar7_chip_rev(void) 1277ca5dc14SFlorian Fainelli { 128238dd317SFlorian Fainelli return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + (ar7_is_titan() ? 0x24 : 129238dd317SFlorian Fainelli 0x14))) >> 16) & 0xff; 1307ca5dc14SFlorian Fainelli } 1317ca5dc14SFlorian Fainelli ar7_has_high_cpmac(void)1327ca5dc14SFlorian Fainellistatic inline int ar7_has_high_cpmac(void) 1337ca5dc14SFlorian Fainelli { 1347ca5dc14SFlorian Fainelli u16 chip_id = ar7_chip_id(); 1357ca5dc14SFlorian Fainelli switch (chip_id) { 1367ca5dc14SFlorian Fainelli case AR7_CHIP_7100: 1377ca5dc14SFlorian Fainelli case AR7_CHIP_7200: 1387ca5dc14SFlorian Fainelli return 0; 1397ca5dc14SFlorian Fainelli case AR7_CHIP_7300: 1407ca5dc14SFlorian Fainelli return 1; 1417ca5dc14SFlorian Fainelli default: 1427ca5dc14SFlorian Fainelli return -ENXIO; 1437ca5dc14SFlorian Fainelli } 1447ca5dc14SFlorian Fainelli } 1457ca5dc14SFlorian Fainelli #define ar7_has_high_vlynq ar7_has_high_cpmac 1467ca5dc14SFlorian Fainelli #define ar7_has_second_uart ar7_has_high_cpmac 1477ca5dc14SFlorian Fainelli ar7_device_enable(u32 bit)1487ca5dc14SFlorian Fainellistatic inline void ar7_device_enable(u32 bit) 1497ca5dc14SFlorian Fainelli { 1507ca5dc14SFlorian Fainelli void *reset_reg = 151e1df057dSFlorian Fainelli (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PERIPHERAL); 1527ca5dc14SFlorian Fainelli writel(readl(reset_reg) | (1 << bit), reset_reg); 1537ca5dc14SFlorian Fainelli msleep(20); 1547ca5dc14SFlorian Fainelli } 1557ca5dc14SFlorian Fainelli ar7_device_disable(u32 bit)1567ca5dc14SFlorian Fainellistatic inline void ar7_device_disable(u32 bit) 1577ca5dc14SFlorian Fainelli { 1587ca5dc14SFlorian Fainelli void *reset_reg = 159e1df057dSFlorian Fainelli (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PERIPHERAL); 1607ca5dc14SFlorian Fainelli writel(readl(reset_reg) & ~(1 << bit), reset_reg); 1617ca5dc14SFlorian Fainelli msleep(20); 1627ca5dc14SFlorian Fainelli } 1637ca5dc14SFlorian Fainelli ar7_device_reset(u32 bit)1647ca5dc14SFlorian Fainellistatic inline void ar7_device_reset(u32 bit) 1657ca5dc14SFlorian Fainelli { 1667ca5dc14SFlorian Fainelli ar7_device_disable(bit); 1677ca5dc14SFlorian Fainelli ar7_device_enable(bit); 1687ca5dc14SFlorian Fainelli } 1697ca5dc14SFlorian Fainelli ar7_device_on(u32 bit)1707ca5dc14SFlorian Fainellistatic inline void ar7_device_on(u32 bit) 1717ca5dc14SFlorian Fainelli { 1727ca5dc14SFlorian Fainelli void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER); 1737ca5dc14SFlorian Fainelli writel(readl(power_reg) | (1 << bit), power_reg); 1747ca5dc14SFlorian Fainelli msleep(20); 1757ca5dc14SFlorian Fainelli } 1767ca5dc14SFlorian Fainelli ar7_device_off(u32 bit)1777ca5dc14SFlorian Fainellistatic inline void ar7_device_off(u32 bit) 1787ca5dc14SFlorian Fainelli { 1797ca5dc14SFlorian Fainelli void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER); 1807ca5dc14SFlorian Fainelli writel(readl(power_reg) & ~(1 << bit), power_reg); 1817ca5dc14SFlorian Fainelli msleep(20); 1827ca5dc14SFlorian Fainelli } 1837ca5dc14SFlorian Fainelli 1843bc6968aSFlorian Fainelli int __init ar7_gpio_init(void); 1850bc67917SFlorian Fainelli void __init ar7_init_clocks(void); 1863bc6968aSFlorian Fainelli 187832f5dacSAlban Bedel /* Board specific GPIO functions */ 188832f5dacSAlban Bedel int ar7_gpio_enable(unsigned gpio); 189832f5dacSAlban Bedel int ar7_gpio_disable(unsigned gpio); 190832f5dacSAlban Bedel 1917ca5dc14SFlorian Fainelli #endif /* __AR7_H__ */ 192