nand/raw/mxc_nand.h

30 #define is_mxc_nfc_21()		0
31 #define is_mxc_nfc_32()		0
34 #define is_mxc_nfc_1()		0
36 #define is_mxc_nfc_32()		0
40 #define is_mxc_nfc_1()		0
41 #define is_mxc_nfc_21()		0
51 #define NAND_MXC_REG_OFFSET		0xe00
56 #define NAND_MXC_REG_OFFSET		0x1e00
60 	u8 main_area[NAND_MXC_NR_BUFS][0x200];
128 /* Set FCMD to 1, rest to 0 for Command operation */
129 #define NFC_CMD				0x1
131 /* Set FADD to 1, rest to 0 for Address operation */
132 #define NFC_ADDR			0x2
134 /* Set FDI to 1, rest to 0 for Input operation */
135 #define NFC_INPUT			0x4
137 /* Set FDO to 001, rest to 0 for Data Output operation */
138 #define NFC_OUTPUT			0x8
140 /* Set FDO to 010, rest to 0 for Read ID operation */
141 #define NFC_ID				0x10
143 /* Set FDO to 100, rest to 0 for Read Status operation */
144 #define NFC_STATUS			0x20
151 #define NFC_CONFIG1_SP_EN		(1 << 0)
158 #define NFC_V2_CONFIG1_ECC_MODE_4	(1 << 0)
161 #define NFC_V3_CONFIG1_RBA_MASK		(0x7 << 4)
162 #define NFC_V3_CONFIG1_RBA(x)		(((x) & 0x7) << 4)
165 #define NFC_V3_CONFIG2_PS_MASK		(0x3 << 0)
166 #define NFC_V3_CONFIG2_PS_512		(0 << 0)
167 #define NFC_V3_CONFIG2_PS_2048		(1 << 0)
168 #define NFC_V3_CONFIG2_PS_4096		(2 << 0)
174 #define NFC_V3_CONFIG2_PPB_MASK		(0x3 << 7)
175 #define NFC_V3_CONFIG2_PPB(x)		(((x) & 0x3) << 7)
176 #define NFC_V3_CONFIG2_EDC_MASK		(0x7 << 9)
177 #define NFC_V3_CONFIG2_EDC(x)		(((x) & 0x7) << 9)
178 #define NFC_V3_CONFIG2_NUM_ADDR_PH1(x)	(((x) & 0x3) << 12)
180 #define NFC_V3_CONFIG2_SPAS_MASK	(0xff << 16)
181 #define NFC_V3_CONFIG2_SPAS(x)		(((x) & 0xff) << 16)
182 #define NFC_V3_CONFIG2_ST_CMD_MASK	(0xff << 24)
183 #define NFC_V3_CONFIG2_ST_CMD(x)	(((x) & 0xff) << 24)
185 #define NFC_V3_CONFIG3_ADD_OP(x)	(((x) & 0x3) << 0)
187 #define NFC_V3_CONFIG3_SBB(x)		(((x) & 0x7) << 8)
188 #define NFC_V3_CONFIG3_NUM_OF_DEVS(x)	(((x) & 0x7) << 12)
195 #define NFC_V3_IPC_CREQ			(1 << 0)