hsi/controllers/omap_ssi_regs.h

15 #define SSI_REVISION_REG    0
16 #  define SSI_REV_MAJOR    0xf0
17 #  define SSI_REV_MINOR    0xf
18 #define SSI_SYSCONFIG_REG    0x10
19 #  define SSI_AUTOIDLE    (1 << 0)
21 #  define SSI_SIDLEMODE_FORCE  0
24 #  define SSI_SIDLEMODE_MASK  0x18
25 #  define SSI_MIDLEMODE_FORCE  0
28 #  define SSI_MIDLEMODE_MASK  0x3000
29 #define SSI_SYSSTATUS_REG    0x14
31 #define SSI_MPU_STATUS_REG(port, irq)  (0x808 + ((port) * 0x10) + ((irq) * 2))
32 #define SSI_MPU_ENABLE_REG(port, irq)  (0x80c + ((port) * 0x10) + ((irq) * 8))
38 #define SSI_GDD_MPU_IRQ_STATUS_REG  0x0800
39 #define SSI_GDD_MPU_IRQ_ENABLE_REG  0x0804
41 #define SSI_WAKE_REG(port)    (0xc00 + ((port) * 0x10))
42 #define SSI_CLEAR_WAKE_REG(port)  (0xc04 + ((port) * 0x10))
43 #define SSI_SET_WAKE_REG(port)    (0xc08 + ((port) * 0x10))
45 #  define SSI_WAKE_MASK    0xff
50 #define SSI_SST_ID_REG      0
53 #  define SSI_MODE_SLEEP    0
59 #define SSI_SST_TXSTATE_REG    0xc
60 #  define  SSI_TXSTATE_IDLE  0
61 #define SSI_SST_BUFSTATE_REG    0x10
63 #define SSI_SST_DIVISOR_REG    0x18
65 #define SSI_SST_BREAK_REG    0x20
66 #define SSI_SST_CHANNELS_REG    0x24
68 #define SSI_SST_ARBMODE_REG    0x28
69 #  define SSI_ARBMODE_ROUNDROBIN  0
71 #define SSI_SST_BUFFER_CH_REG(channel)  (0x80 + ((channel) * 4))
72 #define SSI_SST_SWAPBUF_CH_REG(channel)  (0xc0 + ((channel) * 4))
77 #define SSI_SSR_ID_REG      0
80 #define SSI_SSR_RXSTATE_REG    0xc
81 #define SSI_SSR_BUFSTATE_REG    0x10
83 #define SSI_SSR_BREAK_REG    0x1c
84 #define SSI_SSR_ERROR_REG    0x20
85 #define SSI_SSR_ERRORACK_REG    0x24
86 #define SSI_SSR_OVERRUN_REG    0x2c
87 #define SSI_SSR_OVERRUNACK_REG    0x30
88 #define SSI_SSR_TIMEOUT_REG    0x34
89 #  define SSI_TIMEOUT_DEFAULT  0
90 #define SSI_SSR_CHANNELS_REG    0x28
91 #define SSI_SSR_BUFFER_CH_REG(channel)  (0x80 + ((channel) * 4))
92 #define SSI_SSR_SWAPBUF_CH_REG(channel)  (0xc0 + ((channel) * 4))
97 #define SSI_GDD_HW_ID_REG    0
98 #define SSI_GDD_PPORT_ID_REG    0x10
99 #define SSI_GDD_MPORT_ID_REG    0x14
100 #define SSI_GDD_PPORT_SR_REG    0x20
101 #define SSI_GDD_MPORT_SR_REG    0x24
102 #  define SSI_ACTIVE_LCH_NUM_MASK  0xff
103 #define SSI_GDD_TEST_REG    0x40
105 #define SSI_GDD_GCR_REG      0x100
108 #  define  SSI_SWITCH_OFF    (1 << 0)
109 #define SSI_GDD_GRST_REG    0x200
111 #define SSI_GDD_CSDP_REG(channel)  (0x800 + ((channel) * 0x40))
112 #  define SSI_DST_BURST_EN_MASK  0xc000
113 #  define SSI_DST_SINGLE_ACCESS0  0
117 #  define SSI_DST_MASK    0x1e00
120 #  define SSI_SRC_BURST_EN_MASK  0x180
121 #  define SSI_SRC_SINGLE_ACCESS0  0
125 #  define SSI_SRC_MASK    0x3c
130 #define SSI_GDD_CCR_REG(channel)  (0x802 + ((channel) * 0x40))
132 #  define SSI_DST_AMODE_CONST  0
135 #  define SSI_SRC_AMODE_CONST  0
138 #  define SSI_CCR_SYNC_MASK  0x1f
139 #define SSI_GDD_CICR_REG(channel)  (0x804 + ((channel) * 0x40))
142 #  define SSI_TOUT_IE    (1 << 0)
143 #define SSI_GDD_CSR_REG(channel)  (0x806 + ((channel) * 0x40))
147 #  define SSI_CSR_TOUR    (1 << 0)
148 #define SSI_GDD_CSSA_REG(channel)  (0x808 + ((channel) * 0x40))
149 #define SSI_GDD_CDSA_REG(channel)  (0x80c + ((channel) * 0x40))
150 #define SSI_GDD_CEN_REG(channel)  (0x810 + ((channel) * 0x40))
151 #define SSI_GDD_CSAC_REG(channel)  (0x818 + ((channel) * 0x40))
152 #define SSI_GDD_CDAC_REG(channel)  (0x81a + ((channel) * 0x40))
153 #define SSI_GDD_CLNK_CTRL_REG(channel)  (0x828 + ((channel) * 0x40))
156 #  define SSI_NEXT_CH_ID_MASK  0xf