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/openbmc/linux/arch/arm/mach-omap2/
H A Dprm54xx.h24 #define OMAP54XX_PRM_BASE 0x4ae06000
31 #define OMAP54XX_PRM_OCP_SOCKET_INST 0x0000
32 #define OMAP54XX_PRM_CKGEN_INST 0x0100
33 #define OMAP54XX_PRM_MPU_INST 0x0300
34 #define OMAP54XX_PRM_DSP_INST 0x0400
35 #define OMAP54XX_PRM_ABE_INST 0x0500
36 #define OMAP54XX_PRM_COREAON_INST 0x0600
37 #define OMAP54XX_PRM_CORE_INST 0x0700
38 #define OMAP54XX_PRM_IVA_INST 0x1200
39 #define OMAP54XX_PRM_CAM_INST 0x1300
[all …]
H A Dprm7xx.h26 #define DRA7XX_PRM_BASE 0x4ae06000
33 #define DRA7XX_PRM_OCP_SOCKET_INST 0x0000
34 #define DRA7XX_PRM_CKGEN_INST 0x0100
35 #define DRA7XX_PRM_MPU_INST 0x0300
36 #define DRA7XX_PRM_DSP1_INST 0x0400
37 #define DRA7XX_PRM_IPU_INST 0x0500
38 #define DRA7XX_PRM_COREAON_INST 0x0628
39 #define DRA7XX_PRM_CORE_INST 0x0700
40 #define DRA7XX_PRM_IVA_INST 0x0f00
41 #define DRA7XX_PRM_CAM_INST 0x1000
[all …]
H A Dprm44xx.h28 #define OMAP4430_PRM_BASE 0x4a306000
35 #define OMAP4430_PRM_OCP_SOCKET_INST 0x0000
36 #define OMAP4430_PRM_CKGEN_INST 0x0100
37 #define OMAP4430_PRM_MPU_INST 0x0300
38 #define OMAP4430_PRM_TESLA_INST 0x0400
39 #define OMAP4430_PRM_ABE_INST 0x0500
40 #define OMAP4430_PRM_ALWAYS_ON_INST 0x0600
41 #define OMAP4430_PRM_CORE_INST 0x0700
42 #define OMAP4430_PRM_IVAHD_INST 0x0f00
43 #define OMAP4430_PRM_CAM_INST 0x1000
[all …]
/openbmc/linux/arch/s390/include/asm/
H A Dlowcore.h25 __u8 pad_0x0000[0x0014-0x0000]; /* 0x0000 */
26 __u32 ipl_parmblock_ptr; /* 0x0014 */
27 __u8 pad_0x0018[0x0080-0x0018]; /* 0x0018 */
28 __u32 ext_params; /* 0x0080 */
31 __u16 ext_cpu_addr; /* 0x0084 */
32 __u16 ext_int_code; /* 0x0086 */
36 __u32 svc_int_code; /* 0x0088 */
39 __u16 pgm_ilc; /* 0x008c */
40 __u16 pgm_code; /* 0x008e */
44 __u32 data_exc_code; /* 0x0090 */
[all …]
/openbmc/linux/drivers/regulator/
H A Dslg51000-regulator.h14 #define SLG51000_SYSCTL_PATN_ID_B0 0x1105
15 #define SLG51000_SYSCTL_PATN_ID_B1 0x1106
16 #define SLG51000_SYSCTL_PATN_ID_B2 0x1107
17 #define SLG51000_SYSCTL_SYS_CONF_A 0x1109
18 #define SLG51000_SYSCTL_SYS_CONF_D 0x110c
19 #define SLG51000_SYSCTL_MATRIX_CONF_A 0x110d
20 #define SLG51000_SYSCTL_MATRIX_CONF_B 0x110e
21 #define SLG51000_SYSCTL_REFGEN_CONF_C 0x1111
22 #define SLG51000_SYSCTL_UVLO_CONF_A 0x1112
23 #define SLG51000_SYSCTL_FAULT_LOG1 0x1115
[all …]
/openbmc/linux/drivers/video/fbdev/
H A Dcarminefb_regs.h5 #define CARMINE_OVERLAY_EXT_MODE (0x00000002)
6 #define CARMINE_GRAPH_REG (0x00000000)
7 #define CARMINE_DISP0_REG (0x00100000)
8 #define CARMINE_DISP1_REG (0x00140000)
9 #define CARMINE_WB_REG (0x00180000)
10 #define CARMINE_DCTL_REG (0x00300000)
11 #define CARMINE_CTL_REG (0x00400000)
12 #define CARMINE_WINDOW_MODE (0x00000001)
19 #define CARMINE_EXT_CMODE_DIRECT24_RGBA (0xC0000000)
20 #define CARMINE_DCTL_REG_MODE_ADD (0x00)
[all …]
/openbmc/linux/drivers/ufs/host/
H A Dufs-qcom.h14 #define MAX_U32 (~(u32)0)
15 #define MPHY_TX_FSM_STATE 0x41
16 #define TX_FSM_HIBERN8 0x1
24 #define UFS_HW_VER_STEP_MASK GENMASK(15, 0)
34 REG_UFS_SYS1CLK_1US = 0xC0,
35 REG_UFS_TX_SYMBOL_CLK_NS_US = 0xC4,
36 REG_UFS_LOCAL_PORT_ID_REG = 0xC8,
37 REG_UFS_PA_ERR_CODE = 0xCC,
39 REG_UFS_PARAM0 = 0xD0,
41 REG_UFS_CFG0 = 0xD8,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dmediatek,tphy.yaml15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA.
22 shared 0x0000 SPLLC
23 0x0100 FMREG
24 u2 port0 0x0800 U2PHY_COM
25 u3 port0 0x0900 U3PHYD
26 0x0a00 U3PHYD_BANK2
27 0x0b00 U3PHYA
28 0x0c00 U3PHYA_DA
29 u2 port1 0x1000 U2PHY_COM
30 u3 port1 0x1100 U3PHYD
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/wireless/
H A Dqcom,ath10k.yaml109 enum: [0, 1]
271 reg = <0x18800000 0x800000>;
288 iommus = <&anoc2_smmu 0x1900>,
289 <&anoc2_smmu 0x1901>;
298 iommus = <&apps_smmu 0x1c02 0x1>;
308 reg = <0xa000000 0x200000>;
/openbmc/linux/arch/mips/boot/dts/loongson/
H A Dloongson64-2k1000.dtsi15 #size-cells = <0>;
17 cpu0: cpu@0 {
20 reg = <0x0>;
27 #clock-cells = <0>;
33 #address-cells = <0>;
43 ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* ioports */
44 0 0x40000000 0 0x40000000 0 0x40000000
45 0xfe 0x00000000 0xfe 0x00000000 0 0x40000000>;
51 ranges = <1 0x0 0x0 0x18000000 0x4000>;
56 reg = <0 0x1fe07000 0 0x422>;
[all …]
H A Dls7a-pch.dtsi8 ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* PIO & CONF & APB */
9 0 0x20000000 0 0x20000000 0 0x10000000
10 0 0x40000000 0 0x40000000 0 0x40000000 /* PCI MEM */
11 0xe00 0x00000000 0xe00 0x00000000 0x100 0x0000000>;
15 reg = <0 0x10000000 0 0x400>;
18 loongson,pic-base-vec = <0>;
24 reg = <0 0x100d0100 0 0x78>;
31 reg = <0 0x10080000 0 0x100>;
41 reg = <0 0x10080100 0 0x100>;
51 reg = <0 0x10080200 0 0x100>;
[all …]
/openbmc/u-boot/arch/arm/mach-mvebu/serdes/axp/
H A Dboard_env_spec.h12 #define MV_6710_DEV_ID 0x6710
14 #define MV_6710_Z1_REV 0x0
19 #define MV_78130_DEV_ID 0x7813
20 #define MV_78160_DEV_ID 0x7816
21 #define MV_78230_DEV_ID 0x7823
22 #define MV_78260_DEV_ID 0x7826
23 #define MV_78460_DEV_ID 0x7846
24 #define MV_78000_DEV_ID 0x7888
26 #define MV_FPGA_DEV_ID 0x2107
28 #define MV_78XX0_Z1_REV 0x0
[all …]
/openbmc/linux/drivers/net/ethernet/hisilicon/hns3/hns3_common/
H A Dhclge_comm_cmd.h10 #define HCLGE_COMM_CMD_FLAG_IN BIT(0)
18 #define HCLGE_COMM_LINK_EVENT_REPORT_EN_B 0
28 #define HCLGE_COMM_TYPE_CRQ 0
34 #define HCLGE_COMM_NIC_CSQ_BASEADDR_L_REG 0x27000
35 #define HCLGE_COMM_NIC_CSQ_BASEADDR_H_REG 0x27004
36 #define HCLGE_COMM_NIC_CSQ_DEPTH_REG 0x27008
37 #define HCLGE_COMM_NIC_CSQ_TAIL_REG 0x27010
38 #define HCLGE_COMM_NIC_CSQ_HEAD_REG 0x27014
39 #define HCLGE_COMM_NIC_CRQ_BASEADDR_L_REG 0x27018
40 #define HCLGE_COMM_NIC_CRQ_BASEADDR_H_REG 0x2701C
[all …]
/openbmc/linux/drivers/comedi/drivers/
H A Dni_atmio.c87 .isapnp_id = 0x0000, /* XXX unknown */
89 .ai_maxdata = 0x0fff,
94 .ao_maxdata = 0x0fff,
102 .isapnp_id = 0x1900,
104 .ai_maxdata = 0x0fff,
109 .ao_maxdata = 0x0fff,
117 .isapnp_id = 0x2400,
119 .ai_maxdata = 0x0fff,
124 .ao_maxdata = 0x0fff,
131 .isapnp_id = 0x2500,
[all …]
/openbmc/linux/drivers/media/i2c/
H A Dmsp3400-kthreads.c28 { 0x0000, 0, 0, "could not detect sound standard", V4L2_STD_ALL },
29 { 0x0001, 0, 0, "autodetect start", V4L2_STD_ALL },
30 { 0x0002, MSP_CARRIER(4.5), MSP_CARRIER(4.72),
32 { 0x0003, MSP_CARRIER(5.5), MSP_CARRIER(5.7421875),
34 { 0x0004, MSP_CARRIER(6.5), MSP_CARRIER(6.2578125),
36 { 0x0005, MSP_CARRIER(6.5), MSP_CARRIER(6.7421875),
38 { 0x0006, MSP_CARRIER(6.5), MSP_CARRIER(6.5),
40 { 0x0007, MSP_CARRIER(6.5), MSP_CARRIER(5.7421875),
42 { 0x0008, MSP_CARRIER(5.5), MSP_CARRIER(5.85),
44 { 0x0009, MSP_CARRIER(6.5), MSP_CARRIER(5.85),
[all …]
/openbmc/u-boot/drivers/pinctrl/uniphier/
H A Dpinctrl-uniphier-core.c17 #define UNIPHIER_PINCTRL_PINMUX_BASE 0x1000
18 #define UNIPHIER_PINCTRL_LOAD_PINMUX 0x1700
19 #define UNIPHIER_PINCTRL_DRVCTRL_BASE 0x1800
20 #define UNIPHIER_PINCTRL_DRV2CTRL_BASE 0x1900
21 #define UNIPHIER_PINCTRL_DRV3CTRL_BASE 0x1980
22 #define UNIPHIER_PINCTRL_PUPDCTRL_BASE 0x1a00
23 #define UNIPHIER_PINCTRL_IECTRL 0x1d00
48 for (i = 0; i < pins_count; i++) in uniphier_pinctrl_get_pin_name()
108 return 0; in uniphier_pinconf_input_enable_perpin()
126 return 0; in uniphier_pinconf_input_enable_legacy()
[all …]
/openbmc/linux/drivers/net/dsa/mv88e6xxx/
H A Dport.h16 /* Offset 0x00: Port Status Register */
17 #define MV88E6XXX_PORT_STS 0x00
18 #define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000
19 #define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000
20 #define MV88E6XXX_PORT_STS_HD_FLOW 0x2000
21 #define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000
22 #define MV88E6250_PORT_STS_LINK 0x1000
23 #define MV88E6250_PORT_STS_PORTMODE_MASK 0x0f00
24 #define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF 0x0800
25 #define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF 0x0900
[all …]
/openbmc/linux/drivers/bus/
H A Domap_l3_noc.h16 #define CUSTOM_ERROR 0x2
17 #define STANDARD_ERROR 0x0
18 #define INBAND_ERROR 0x0
19 #define L3_APPLICATION_ERROR 0x0
20 #define L3_DEBUG_ERROR 0x1
23 #define L3_TARG_STDERRLOG_MAIN 0x48
24 #define L3_TARG_STDERRLOG_HDR 0x4c
25 #define L3_TARG_STDERRLOG_MSTADDR 0x50
26 #define L3_TARG_STDERRLOG_INFO 0x58
27 #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c
[all …]
/openbmc/linux/drivers/gpu/drm/loongson/
H A Dlsdc_regs.h24 #define LS7A1000_PIXPLL0_REG 0x04B0
25 #define LS7A1000_PIXPLL1_REG 0x04C0
28 #define LS7A1000_PLL_GFX_REG 0x0490
30 #define LS7A1000_CONF_REG_BASE 0x10010000
34 #define LS7A2000_PIXPLL0_REG 0x04B0
35 #define LS7A2000_PIXPLL1_REG 0x04C0
38 #define LS7A2000_PLL_GFX_REG 0x0490
40 #define LS7A2000_CONF_REG_BASE 0x10010000
43 #define CFG_PIX_FMT_MASK GENMASK(2, 0)
46 LSDC_PF_NONE = 0,
[all …]
/openbmc/linux/drivers/net/wireless/realtek/rtlwifi/
H A Ddebug.c80 int max = 0xff; in rtl_debug_get_mac_page()
82 for (n = 0; n <= max; ) { in rtl_debug_get_mac_page()
84 for (i = 0; i < 4 && n <= max; i++, n += 4) in rtl_debug_get_mac_page()
89 return 0; in rtl_debug_get_mac_page()
98 RTL_DEBUG_IMPL_MAC_SERIES(0, 0x0000);
99 RTL_DEBUG_IMPL_MAC_SERIES(1, 0x0100);
100 RTL_DEBUG_IMPL_MAC_SERIES(2, 0x0200);
101 RTL_DEBUG_IMPL_MAC_SERIES(3, 0x0300);
102 RTL_DEBUG_IMPL_MAC_SERIES(4, 0x0400);
103 RTL_DEBUG_IMPL_MAC_SERIES(5, 0x0500);
[all …]
/openbmc/qemu/include/hw/pci-host/
H A Dpnv_phb4_regs.h32 * stacks, thus for PEC2, the global registers are at offset 0, the
33 * PHB3 registers at offset 0x40, the PHB4 at offset 0x80 etc....
36 * it is 0 based, ie PHB3 is at 0x100 PHB4 is a 0x140 etc..
38 #define PEC_STACK_OFFSET 0x40
41 #define PEC_NEST_PBCQ_HW_CONFIG 0x00
42 #define PEC_NEST_DROP_PRIO_CTRL 0x01
43 #define PEC_NEST_PBCQ_ERR_INJECT 0x02
44 #define PEC_NEST_PCI_NEST_CLK_TRACE_CTL 0x03
45 #define PEC_NEST_PBCQ_PMON_CTRL 0x04
46 #define PEC_NEST_PBCQ_PBUS_ADDR_EXT 0x05
[all …]
/openbmc/linux/drivers/clk/imx/
H A Dclk-imx93.c58 { IMX93_CLK_A55_PERIPH, "a55_periph_root", 0x0000, FAST_SEL, CLK_IS_CRITICAL },
59 { IMX93_CLK_A55_MTR_BUS, "a55_mtr_bus_root", 0x0080, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
60 { IMX93_CLK_A55, "a55_alt_root", 0x0100, FAST_SEL, CLK_IS_CRITICAL },
61 { IMX93_CLK_M33, "m33_root", 0x0180, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
62 { IMX93_CLK_BUS_WAKEUP, "bus_wakeup_root", 0x0280, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
63 { IMX93_CLK_BUS_AON, "bus_aon_root", 0x0300, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL },
64 { IMX93_CLK_WAKEUP_AXI, "wakeup_axi_root", 0x0380, FAST_SEL, CLK_IS_CRITICAL },
65 { IMX93_CLK_SWO_TRACE, "swo_trace_root", 0x0400, LOW_SPEED_IO_SEL, },
66 { IMX93_CLK_M33_SYSTICK, "m33_systick_root", 0x0480, LOW_SPEED_IO_SEL, },
67 { IMX93_CLK_FLEXIO1, "flexio1_root", 0x0500, LOW_SPEED_IO_SEL, },
[all …]
/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/
H A Dg98.fuc0s23 ctx_dma_query: .b32 0
24 ctx_dma_src: .b32 0
25 ctx_dma_dst: .b32 0
27 ctx_query_address_high: .b32 0
28 ctx_query_address_low: .b32 0
29 ctx_query_counter: .b32 0
30 ctx_cond_address_high: .b32 0
31 ctx_cond_address_low: .b32 0
32 ctx_cond_off: .b32 0
33 ctx_src_address_high: .b32 0
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc8xx/
H A Dstart.S11 * The processor starts at 0x00000100 and the code is executed
21 * address and (s)dram will be positioned at address 0
64 .long 0x27051956 /* U-Boot Magic Number */
67 .ascii U_BOOT_VERSION_STRING, "\0"
138 li r2, 0x0007
159 ori r4, r4, (0x2000 - 4)
160 li r0, (0x2000 / 4)
162 li r0, 0
187 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
190 STD_EXCEPTION(0x300, DataStorage, UnknownException)
[all …]
/openbmc/linux/drivers/media/i2c/ccs/
H A Dsmiapp-reg-defs.h16 #define SMIAPP_REG_U16_MODEL_ID (0x0000 | CCS_FL_16BIT)
17 #define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR 0x0002
18 #define SMIAPP_REG_U8_MANUFACTURER_ID 0x0003
19 #define SMIAPP_REG_U8_SMIA_VERSION 0x0004
20 #define SMIAPP_REG_U8_FRAME_COUNT 0x0005
21 #define SMIAPP_REG_U8_PIXEL_ORDER 0x0006
22 #define SMIAPP_REG_U16_DATA_PEDESTAL (0x0008 | CCS_FL_16BIT)
23 #define SMIAPP_REG_U8_PIXEL_DEPTH 0x000c
24 #define SMIAPP_REG_U8_REVISION_NUMBER_MINOR 0x0010
25 #define SMIAPP_REG_U8_SMIAPP_VERSION 0x0011
[all …]

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