12874c5fdSThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-or-later */ 218abed21SVivien Didelot /* 318abed21SVivien Didelot * Marvell 88E6xxx Switch Port Registers support 418abed21SVivien Didelot * 518abed21SVivien Didelot * Copyright (c) 2008 Marvell Semiconductor 618abed21SVivien Didelot * 74333d619SVivien Didelot * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 84333d619SVivien Didelot * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 918abed21SVivien Didelot */ 1018abed21SVivien Didelot 1118abed21SVivien Didelot #ifndef _MV88E6XXX_PORT_H 1218abed21SVivien Didelot #define _MV88E6XXX_PORT_H 1318abed21SVivien Didelot 144d5f2ba7SVivien Didelot #include "chip.h" 1518abed21SVivien Didelot 165f83dc93SVivien Didelot /* Offset 0x00: Port Status Register */ 175f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS 0x00 185f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_PAUSE_EN 0x8000 195f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_MY_PAUSE 0x4000 205f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_HD_FLOW 0x2000 215f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_PHY_DETECT 0x1000 22ce91c453SRasmus Villemoes #define MV88E6250_PORT_STS_LINK 0x1000 23ce91c453SRasmus Villemoes #define MV88E6250_PORT_STS_PORTMODE_MASK 0x0f00 24ce91c453SRasmus Villemoes #define MV88E6250_PORT_STS_PORTMODE_PHY_10_HALF 0x0800 25ce91c453SRasmus Villemoes #define MV88E6250_PORT_STS_PORTMODE_PHY_100_HALF 0x0900 26ce91c453SRasmus Villemoes #define MV88E6250_PORT_STS_PORTMODE_PHY_10_FULL 0x0a00 27ce91c453SRasmus Villemoes #define MV88E6250_PORT_STS_PORTMODE_PHY_100_FULL 0x0b00 280142cbb8SMatthias Schiffer /* - Modes with PHY suffix use output instead of input clock 290142cbb8SMatthias Schiffer * - Modes without RMII or RGMII use MII 300142cbb8SMatthias Schiffer * - Modes without speed do not have a fixed speed specified in the manual 310142cbb8SMatthias Schiffer * ("DC to x MHz" - variable clock support?) 320142cbb8SMatthias Schiffer */ 330142cbb8SMatthias Schiffer #define MV88E6250_PORT_STS_PORTMODE_MII_DISABLED 0x0000 340142cbb8SMatthias Schiffer #define MV88E6250_PORT_STS_PORTMODE_MII_100_RGMII 0x0100 350142cbb8SMatthias Schiffer #define MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL_PHY 0x0200 360142cbb8SMatthias Schiffer #define MV88E6250_PORT_STS_PORTMODE_MII_200_RMII_FULL_PHY 0x0400 370142cbb8SMatthias Schiffer #define MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL 0x0600 380142cbb8SMatthias Schiffer #define MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL 0x0700 390142cbb8SMatthias Schiffer #define MV88E6250_PORT_STS_PORTMODE_MII_HALF 0x0800 400142cbb8SMatthias Schiffer #define MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_HALF_PHY 0x0900 410142cbb8SMatthias Schiffer #define MV88E6250_PORT_STS_PORTMODE_MII_FULL 0x0a00 420142cbb8SMatthias Schiffer #define MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL_PHY 0x0b00 430142cbb8SMatthias Schiffer #define MV88E6250_PORT_STS_PORTMODE_MII_10_HALF_PHY 0x0c00 440142cbb8SMatthias Schiffer #define MV88E6250_PORT_STS_PORTMODE_MII_100_HALF_PHY 0x0d00 450142cbb8SMatthias Schiffer #define MV88E6250_PORT_STS_PORTMODE_MII_10_FULL_PHY 0x0e00 460142cbb8SMatthias Schiffer #define MV88E6250_PORT_STS_PORTMODE_MII_100_FULL_PHY 0x0f00 475f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_LINK 0x0800 485f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_DUPLEX 0x0400 495f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_SPEED_MASK 0x0300 505f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_SPEED_10 0x0000 515f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_SPEED_100 0x0100 525f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_SPEED_1000 0x0200 53c9a2356fSRussell King #define MV88E6XXX_PORT_STS_SPEED_10000 0x0300 545f83dc93SVivien Didelot #define MV88E6352_PORT_STS_EEE 0x0040 555f83dc93SVivien Didelot #define MV88E6165_PORT_STS_AM_DIS 0x0040 565f83dc93SVivien Didelot #define MV88E6185_PORT_STS_MGMII 0x0040 575f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_TX_PAUSED 0x0020 585f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_FLOW_CTL 0x0010 595f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_MASK 0x000f 60d4ebf12bSRussell King (Oracle) #define MV88E6XXX_PORT_STS_CMODE_MII_PHY 0x0001 61d4ebf12bSRussell King (Oracle) #define MV88E6XXX_PORT_STS_CMODE_MII 0x0002 62d4ebf12bSRussell King (Oracle) #define MV88E6XXX_PORT_STS_CMODE_GMII 0x0003 63d4ebf12bSRussell King (Oracle) #define MV88E6XXX_PORT_STS_CMODE_RMII_PHY 0x0004 64d4ebf12bSRussell King (Oracle) #define MV88E6XXX_PORT_STS_CMODE_RMII 0x0005 65927441adSMarek Behún #define MV88E6XXX_PORT_STS_CMODE_RGMII 0x0007 663bbb8867SMarek Behún #define MV88E6XXX_PORT_STS_CMODE_100BASEX 0x0008 673bbb8867SMarek Behún #define MV88E6XXX_PORT_STS_CMODE_1000BASEX 0x0009 685f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_SGMII 0x000a 695f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_2500BASEX 0x000b 705f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_XAUI 0x000c 715f83dc93SVivien Didelot #define MV88E6XXX_PORT_STS_CMODE_RXAUI 0x000d 72de776d0dSPavana Sharma #define MV88E6393X_PORT_STS_CMODE_5GBASER 0x000c 73de776d0dSPavana Sharma #define MV88E6393X_PORT_STS_CMODE_10GBASER 0x000d 74de776d0dSPavana Sharma #define MV88E6393X_PORT_STS_CMODE_USXGMII 0x000e 756c422e34SRussell King #define MV88E6185_PORT_STS_CDUPLEX 0x0008 766c422e34SRussell King #define MV88E6185_PORT_STS_CMODE_MASK 0x0007 776c422e34SRussell King #define MV88E6185_PORT_STS_CMODE_GMII_FD 0x0000 786c422e34SRussell King #define MV88E6185_PORT_STS_CMODE_MII_100_FD_PS 0x0001 796c422e34SRussell King #define MV88E6185_PORT_STS_CMODE_MII_100 0x0002 806c422e34SRussell King #define MV88E6185_PORT_STS_CMODE_MII_10 0x0003 816c422e34SRussell King #define MV88E6185_PORT_STS_CMODE_SERDES 0x0004 826c422e34SRussell King #define MV88E6185_PORT_STS_CMODE_1000BASE_X 0x0005 836c422e34SRussell King #define MV88E6185_PORT_STS_CMODE_PHY 0x0006 846c422e34SRussell King #define MV88E6185_PORT_STS_CMODE_DISABLED 0x0007 855f83dc93SVivien Didelot 865ee55577SVivien Didelot /* Offset 0x01: MAC (or PCS or Physical) Control Register */ 875ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL 0x01 885ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK 0x8000 895ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK 0x4000 906c422e34SRussell King #define MV88E6185_PORT_MAC_CTL_SYNC_OK 0x4000 915ee55577SVivien Didelot #define MV88E6390_PORT_MAC_CTL_FORCE_SPEED 0x2000 925ee55577SVivien Didelot #define MV88E6390_PORT_MAC_CTL_ALTSPEED 0x1000 935ee55577SVivien Didelot #define MV88E6352_PORT_MAC_CTL_200BASE 0x1000 94de776d0dSPavana Sharma #define MV88E6XXX_PORT_MAC_CTL_EEE 0x0200 95de776d0dSPavana Sharma #define MV88E6XXX_PORT_MAC_CTL_FORCE_EEE 0x0100 966c422e34SRussell King #define MV88E6185_PORT_MAC_CTL_AN_EN 0x0400 976c422e34SRussell King #define MV88E6185_PORT_MAC_CTL_AN_RESTART 0x0200 986c422e34SRussell King #define MV88E6185_PORT_MAC_CTL_AN_DONE 0x0100 995ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_FC 0x0080 1005ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_FORCE_FC 0x0040 1015ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_LINK_UP 0x0020 1025ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_FORCE_LINK 0x0010 1035ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL 0x0008 1045ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX 0x0004 1055ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_SPEED_MASK 0x0003 1065ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_SPEED_10 0x0000 1075ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_SPEED_100 0x0001 1085ee55577SVivien Didelot #define MV88E6065_PORT_MAC_CTL_SPEED_200 0x0002 1095ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_SPEED_1000 0x0002 1105ee55577SVivien Didelot #define MV88E6390_PORT_MAC_CTL_SPEED_10000 0x0003 1115ee55577SVivien Didelot #define MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED 0x0003 1125ee55577SVivien Didelot 1136c96bbfdSVivien Didelot /* Offset 0x02: Jamming Control Register */ 1146c96bbfdSVivien Didelot #define MV88E6097_PORT_JAM_CTL 0x02 1156c96bbfdSVivien Didelot #define MV88E6097_PORT_JAM_CTL_LIMIT_OUT_MASK 0xff00 1166c96bbfdSVivien Didelot #define MV88E6097_PORT_JAM_CTL_LIMIT_IN_MASK 0x00ff 1176c96bbfdSVivien Didelot 1186c96bbfdSVivien Didelot /* Offset 0x02: Flow Control Register */ 1196c96bbfdSVivien Didelot #define MV88E6390_PORT_FLOW_CTL 0x02 1206c96bbfdSVivien Didelot #define MV88E6390_PORT_FLOW_CTL_UPDATE 0x8000 1216c96bbfdSVivien Didelot #define MV88E6390_PORT_FLOW_CTL_PTR_MASK 0x7f00 1226c96bbfdSVivien Didelot #define MV88E6390_PORT_FLOW_CTL_LIMIT_IN 0x0000 1236c96bbfdSVivien Didelot #define MV88E6390_PORT_FLOW_CTL_LIMIT_OUT 0x0100 1246c96bbfdSVivien Didelot #define MV88E6390_PORT_FLOW_CTL_DATA_MASK 0x00ff 1256c96bbfdSVivien Didelot 126107fcc10SVivien Didelot /* Offset 0x03: Switch Identifier Register */ 127107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID 0x03 128107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_MASK 0xfff0 12971d94a43SMatthias Schiffer #define MV88E6XXX_PORT_SWITCH_ID_PROD_6020 0x0200 130372188c8SLukasz Majewski #define MV88E6XXX_PORT_SWITCH_ID_PROD_6071 0x0710 131107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6085 0x04a0 132107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6095 0x0950 133107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6097 0x0990 134107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6190X 0x0a00 135107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6390X 0x0a10 136107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6131 0x1060 137107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6320 0x1150 138107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6123 0x1210 139107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6161 0x1610 140107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6165 0x1650 141107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6171 0x1710 142107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6172 0x1720 143107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6175 0x1750 144107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6176 0x1760 145107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6190 0x1900 146107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6191 0x1910 147de776d0dSPavana Sharma #define MV88E6XXX_PORT_SWITCH_ID_PROD_6191X 0x1920 148de776d0dSPavana Sharma #define MV88E6XXX_PORT_SWITCH_ID_PROD_6193X 0x1930 149107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6185 0x1a70 15049022647SHubert Feurstein #define MV88E6XXX_PORT_SWITCH_ID_PROD_6220 0x2200 151107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6240 0x2400 1521f71836fSRasmus Villemoes #define MV88E6XXX_PORT_SWITCH_ID_PROD_6250 0x2500 15312899f29SAlexis Lothoré #define MV88E6XXX_PORT_SWITCH_ID_PROD_6361 0x2610 154107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6290 0x2900 155107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6321 0x3100 156107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6141 0x3400 157107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6341 0x3410 158107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6352 0x3520 159107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6350 0x3710 160107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6351 0x3750 161107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_PROD_6390 0x3900 162de776d0dSPavana Sharma #define MV88E6XXX_PORT_SWITCH_ID_PROD_6393X 0x3930 163107fcc10SVivien Didelot #define MV88E6XXX_PORT_SWITCH_ID_REV_MASK 0x000f 164107fcc10SVivien Didelot 165a89b433bSVivien Didelot /* Offset 0x04: Port Control Register */ 166a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0 0x04 167a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_USE_CORE_TAG 0x8000 16834ea415fSHans Schultz #define MV88E6XXX_PORT_CTL0_SA_FILT_MASK 0xc000 16934ea415fSHans Schultz #define MV88E6XXX_PORT_CTL0_SA_FILT_DISABLED 0x0000 17034ea415fSHans Schultz #define MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_LOCK 0x4000 17134ea415fSHans Schultz #define MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_UNLOCK 0x8000 17234ea415fSHans Schultz #define MV88E6XXX_PORT_CTL0_SA_FILT_DROP_ON_CPU 0xc000 173a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK 0x3000 174a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED 0x0000 175a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED 0x1000 176a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED 0x2000 177a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA 0x3000 178a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_HEADER 0x0800 179a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP 0x0400 180a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_DOUBLE_TAG 0x0200 181a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK 0x0300 182a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL 0x0000 183a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA 0x0100 184a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER 0x0200 185a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA 0x0300 186a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_DSA_TAG 0x0100 187a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_VLAN_TUNNEL 0x0080 188a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_TAG_IF_BOTH 0x0040 189a89b433bSVivien Didelot #define MV88E6185_PORT_CTL0_USE_IP 0x0020 190a89b433bSVivien Didelot #define MV88E6185_PORT_CTL0_USE_TAG 0x0010 191a89b433bSVivien Didelot #define MV88E6185_PORT_CTL0_FORWARD_UNKNOWN 0x0004 192a8b659e7SVladimir Oltean #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_UC 0x0004 193a8b659e7SVladimir Oltean #define MV88E6352_PORT_CTL0_EGRESS_FLOODS_MC 0x0008 194a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_STATE_MASK 0x0003 195a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_STATE_DISABLED 0x0000 196a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_STATE_BLOCKING 0x0001 197a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_STATE_LEARNING 0x0002 198a89b433bSVivien Didelot #define MV88E6XXX_PORT_CTL0_STATE_FORWARDING 0x0003 199a89b433bSVivien Didelot 200cd985bbfSVivien Didelot /* Offset 0x05: Port Control 1 */ 201cd985bbfSVivien Didelot #define MV88E6XXX_PORT_CTL1 0x05 202cd985bbfSVivien Didelot #define MV88E6XXX_PORT_CTL1_MESSAGE_PORT 0x8000 20357e661aaSTobias Waldekranz #define MV88E6XXX_PORT_CTL1_TRUNK_PORT 0x4000 20457e661aaSTobias Waldekranz #define MV88E6XXX_PORT_CTL1_TRUNK_ID_MASK 0x0f00 20557e661aaSTobias Waldekranz #define MV88E6XXX_PORT_CTL1_TRUNK_ID_SHIFT 8 206cd985bbfSVivien Didelot #define MV88E6XXX_PORT_CTL1_FID_11_4_MASK 0x00ff 207cd985bbfSVivien Didelot 2087e5cc5f1SVivien Didelot /* Offset 0x06: Port Based VLAN Map */ 2097e5cc5f1SVivien Didelot #define MV88E6XXX_PORT_BASE_VLAN 0x06 2107e5cc5f1SVivien Didelot #define MV88E6XXX_PORT_BASE_VLAN_FID_3_0_MASK 0xf000 2117e5cc5f1SVivien Didelot 212b7929fb3SVivien Didelot /* Offset 0x07: Default Port VLAN ID & Priority */ 213b7929fb3SVivien Didelot #define MV88E6XXX_PORT_DEFAULT_VLAN 0x07 214b7929fb3SVivien Didelot #define MV88E6XXX_PORT_DEFAULT_VLAN_MASK 0x0fff 215b7929fb3SVivien Didelot 21681c6edb2SVivien Didelot /* Offset 0x08: Port Control 2 Register */ 21781c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2 0x08 21881c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_IGNORE_FCS 0x8000 21981c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_VTU_PRI_OVERRIDE 0x4000 22081c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_SA_PRIO_OVERRIDE 0x2000 22181c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_DA_PRIO_OVERRIDE 0x1000 22281c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK 0x3000 22381c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522 0x0000 22481c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048 0x1000 22581c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240 0x2000 22681c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK 0x0c00 22781c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED 0x0000 22881c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK 0x0400 22981c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK 0x0800 23081c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE 0x0c00 23181c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_DISCARD_TAGGED 0x0200 23281c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_DISCARD_UNTAGGED 0x0100 23381c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_MAP_DA 0x0080 23481c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD 0x0040 23581c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_EGRESS_MONITOR 0x0020 23681c6edb2SVivien Didelot #define MV88E6XXX_PORT_CTL2_INGRESS_MONITOR 0x0010 23781c6edb2SVivien Didelot #define MV88E6095_PORT_CTL2_CPU_PORT_MASK 0x000f 23881c6edb2SVivien Didelot 2392cb8cb14SVivien Didelot /* Offset 0x09: Egress Rate Control */ 2402cb8cb14SVivien Didelot #define MV88E6XXX_PORT_EGRESS_RATE_CTL1 0x09 2412cb8cb14SVivien Didelot 2422cb8cb14SVivien Didelot /* Offset 0x0A: Egress Rate Control 2 */ 2432cb8cb14SVivien Didelot #define MV88E6XXX_PORT_EGRESS_RATE_CTL2 0x0a 2442cb8cb14SVivien Didelot 2452a4614e4SVivien Didelot /* Offset 0x0B: Port Association Vector */ 2462a4614e4SVivien Didelot #define MV88E6XXX_PORT_ASSOC_VECTOR 0x0b 2472a4614e4SVivien Didelot #define MV88E6XXX_PORT_ASSOC_VECTOR_HOLD_AT_1 0x8000 2482a4614e4SVivien Didelot #define MV88E6XXX_PORT_ASSOC_VECTOR_INT_AGE_OUT 0x4000 2492a4614e4SVivien Didelot #define MV88E6XXX_PORT_ASSOC_VECTOR_LOCKED_PORT 0x2000 2502a4614e4SVivien Didelot #define MV88E6XXX_PORT_ASSOC_VECTOR_IGNORE_WRONG 0x1000 2512a4614e4SVivien Didelot #define MV88E6XXX_PORT_ASSOC_VECTOR_REFRESH_LOCKED 0x0800 2522a4614e4SVivien Didelot 253b8109594SVivien Didelot /* Offset 0x0C: Port ATU Control */ 254b8109594SVivien Didelot #define MV88E6XXX_PORT_ATU_CTL 0x0c 255b8109594SVivien Didelot 256b8109594SVivien Didelot /* Offset 0x0D: Priority Override Register */ 257b8109594SVivien Didelot #define MV88E6XXX_PORT_PRI_OVERRIDE 0x0d 258b8109594SVivien Didelot 259b8109594SVivien Didelot /* Offset 0x0E: Policy Control Register */ 260b8109594SVivien Didelot #define MV88E6XXX_PORT_POLICY_CTL 0x0e 261f3a2cd32SVivien Didelot #define MV88E6XXX_PORT_POLICY_CTL_DA_MASK 0xc000 262f3a2cd32SVivien Didelot #define MV88E6XXX_PORT_POLICY_CTL_SA_MASK 0x3000 263f3a2cd32SVivien Didelot #define MV88E6XXX_PORT_POLICY_CTL_VTU_MASK 0x0c00 264f3a2cd32SVivien Didelot #define MV88E6XXX_PORT_POLICY_CTL_ETYPE_MASK 0x0300 265f3a2cd32SVivien Didelot #define MV88E6XXX_PORT_POLICY_CTL_PPPOE_MASK 0x00c0 266f3a2cd32SVivien Didelot #define MV88E6XXX_PORT_POLICY_CTL_VBAS_MASK 0x0030 267f3a2cd32SVivien Didelot #define MV88E6XXX_PORT_POLICY_CTL_OPT82_MASK 0x000c 268f3a2cd32SVivien Didelot #define MV88E6XXX_PORT_POLICY_CTL_UDP_MASK 0x0003 269f3a2cd32SVivien Didelot #define MV88E6XXX_PORT_POLICY_CTL_NORMAL 0x0000 270f3a2cd32SVivien Didelot #define MV88E6XXX_PORT_POLICY_CTL_MIRROR 0x0001 271f3a2cd32SVivien Didelot #define MV88E6XXX_PORT_POLICY_CTL_TRAP 0x0002 272f3a2cd32SVivien Didelot #define MV88E6XXX_PORT_POLICY_CTL_DISCARD 0x0003 273b8109594SVivien Didelot 274de776d0dSPavana Sharma /* Offset 0x0E: Policy & MGMT Control Register (FAMILY_6393X) */ 275de776d0dSPavana Sharma #define MV88E6393X_PORT_POLICY_MGMT_CTL 0x0e 276de776d0dSPavana Sharma #define MV88E6393X_PORT_POLICY_MGMT_CTL_UPDATE 0x8000 277de776d0dSPavana Sharma #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_MASK 0x3f00 278de776d0dSPavana Sharma #define MV88E6393X_PORT_POLICY_MGMT_CTL_DATA_MASK 0x00ff 279de776d0dSPavana Sharma #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XLO 0x2000 280de776d0dSPavana Sharma #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000000XHI 0x2100 281de776d0dSPavana Sharma #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XLO 0x2400 282de776d0dSPavana Sharma #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_01C280000002XHI 0x2500 283de776d0dSPavana Sharma #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_INGRESS_DEST 0x3000 284de776d0dSPavana Sharma #define MV88E6393X_PORT_POLICY_MGMT_CTL_PTR_CPU_DEST 0x3800 285de776d0dSPavana Sharma #define MV88E6393X_PORT_POLICY_MGMT_CTL_CPU_DEST_MGMTPRI 0x00e0 286de776d0dSPavana Sharma 287b8109594SVivien Didelot /* Offset 0x0F: Port Special Ether Type */ 288b8109594SVivien Didelot #define MV88E6XXX_PORT_ETH_TYPE 0x0f 289b8109594SVivien Didelot #define MV88E6XXX_PORT_ETH_TYPE_DEFAULT 0x9100 290b8109594SVivien Didelot 291b8109594SVivien Didelot /* Offset 0x10: InDiscards Low Counter */ 292b8109594SVivien Didelot #define MV88E6XXX_PORT_IN_DISCARD_LO 0x10 293b8109594SVivien Didelot 294de776d0dSPavana Sharma /* Offset 0x10: Extended Port Control Command */ 295de776d0dSPavana Sharma #define MV88E6393X_PORT_EPC_CMD 0x10 296de776d0dSPavana Sharma #define MV88E6393X_PORT_EPC_CMD_BUSY 0x8000 2971323e0c6SMarco Migliore #define MV88E6393X_PORT_EPC_CMD_WRITE 0x3000 298de776d0dSPavana Sharma #define MV88E6393X_PORT_EPC_INDEX_PORT_ETYPE 0x02 299de776d0dSPavana Sharma 300de776d0dSPavana Sharma /* Offset 0x11: Extended Port Control Data */ 301de776d0dSPavana Sharma #define MV88E6393X_PORT_EPC_DATA 0x11 302de776d0dSPavana Sharma 303b8109594SVivien Didelot /* Offset 0x11: InDiscards High Counter */ 304b8109594SVivien Didelot #define MV88E6XXX_PORT_IN_DISCARD_HI 0x11 305b8109594SVivien Didelot 306b8109594SVivien Didelot /* Offset 0x12: InFiltered Counter */ 307b8109594SVivien Didelot #define MV88E6XXX_PORT_IN_FILTERED 0x12 308b8109594SVivien Didelot 309b8109594SVivien Didelot /* Offset 0x13: OutFiltered Counter */ 310b8109594SVivien Didelot #define MV88E6XXX_PORT_OUT_FILTERED 0x13 311b8109594SVivien Didelot 3128009df9eSVivien Didelot /* Offset 0x18: IEEE Priority Mapping Table */ 3138009df9eSVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE 0x18 3148009df9eSVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE 0x8000 315ddcbabf4SVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_MASK 0x7000 3168009df9eSVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP 0x0000 3178009df9eSVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP 0x1000 3188009df9eSVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP 0x2000 3198009df9eSVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP 0x3000 3208009df9eSVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_DSCP 0x5000 3218009df9eSVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_DSCP 0x6000 3228009df9eSVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_DSCP 0x7000 323ddcbabf4SVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK 0x0e00 324ddcbabf4SVivien Didelot #define MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK 0x01ff 3258009df9eSVivien Didelot 3268009df9eSVivien Didelot /* Offset 0x18: Port IEEE Priority Remapping Registers (0-3) */ 3278009df9eSVivien Didelot #define MV88E6095_PORT_IEEE_PRIO_REMAP_0123 0x18 3288009df9eSVivien Didelot 3298009df9eSVivien Didelot /* Offset 0x19: Port IEEE Priority Remapping Registers (4-7) */ 3308009df9eSVivien Didelot #define MV88E6095_PORT_IEEE_PRIO_REMAP_4567 0x19 331d2a160b5SVivien Didelot 332ea89098eSAndrew Lunn /* Offset 0x1a: Magic undocumented errata register */ 33360907013SMarek Behún #define MV88E6XXX_PORT_RESERVED_1A 0x1a 33460907013SMarek Behún #define MV88E6XXX_PORT_RESERVED_1A_BUSY 0x8000 33560907013SMarek Behún #define MV88E6XXX_PORT_RESERVED_1A_WRITE 0x4000 33660907013SMarek Behún #define MV88E6XXX_PORT_RESERVED_1A_READ 0x0000 33760907013SMarek Behún #define MV88E6XXX_PORT_RESERVED_1A_PORT_SHIFT 5 33860907013SMarek Behún #define MV88E6XXX_PORT_RESERVED_1A_BLOCK_SHIFT 10 33960907013SMarek Behún #define MV88E6XXX_PORT_RESERVED_1A_CTRL_PORT 0x04 34060907013SMarek Behún #define MV88E6XXX_PORT_RESERVED_1A_DATA_PORT 0x05 3417a3007d2SMarek Behún #define MV88E6341_PORT_RESERVED_1A_FORCE_CMODE 0x8000 3427a3007d2SMarek Behún #define MV88E6341_PORT_RESERVED_1A_SGMII_AN 0x2000 343ea89098eSAndrew Lunn 34418abed21SVivien Didelot int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, 34518abed21SVivien Didelot u16 *val); 34618abed21SVivien Didelot int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, 34718abed21SVivien Didelot u16 val); 348de776d0dSPavana Sharma int mv88e6xxx_port_wait_bit(struct mv88e6xxx_chip *chip, int port, int reg, 349de776d0dSPavana Sharma int bit, int val); 35018abed21SVivien Didelot 35154186b91SAndrew Lunn int mv88e6185_port_set_pause(struct mv88e6xxx_chip *chip, int port, 35254186b91SAndrew Lunn int pause); 35391e87045SSteffen Bätz int mv88e6320_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 35491e87045SSteffen Bätz phy_interface_t mode); 355a0a0f622SVivien Didelot int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 356a0a0f622SVivien Didelot phy_interface_t mode); 357a0a0f622SVivien Didelot int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip *chip, int port, 358a0a0f622SVivien Didelot phy_interface_t mode); 359a0a0f622SVivien Didelot 36008ef7f10SVivien Didelot int mv88e6xxx_port_set_link(struct mv88e6xxx_chip *chip, int port, int link); 36108ef7f10SVivien Didelot 3624efe7662SChris Packham int mv88e6xxx_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup); 3634efe7662SChris Packham int mv88e6185_port_sync_link(struct mv88e6xxx_chip *chip, int port, unsigned int mode, bool isup); 3644efe7662SChris Packham 365f365c6f7SRussell King int mv88e6185_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 366f365c6f7SRussell King int speed, int duplex); 367f365c6f7SRussell King int mv88e6250_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 368f365c6f7SRussell King int speed, int duplex); 369f365c6f7SRussell King int mv88e6341_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 370f365c6f7SRussell King int speed, int duplex); 371f365c6f7SRussell King int mv88e6352_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 372f365c6f7SRussell King int speed, int duplex); 373f365c6f7SRussell King int mv88e6390_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 374f365c6f7SRussell King int speed, int duplex); 375f365c6f7SRussell King int mv88e6390x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 376f365c6f7SRussell King int speed, int duplex); 377de776d0dSPavana Sharma int mv88e6393x_port_set_speed_duplex(struct mv88e6xxx_chip *chip, int port, 378de776d0dSPavana Sharma int speed, int duplex); 37996a2b40cSVivien Didelot 38018e1b742SAlexis Lothoré phy_interface_t mv88e6341_port_max_speed_mode(struct mv88e6xxx_chip *chip, 38118e1b742SAlexis Lothoré int port); 38218e1b742SAlexis Lothoré phy_interface_t mv88e6390_port_max_speed_mode(struct mv88e6xxx_chip *chip, 38318e1b742SAlexis Lothoré int port); 38418e1b742SAlexis Lothoré phy_interface_t mv88e6390x_port_max_speed_mode(struct mv88e6xxx_chip *chip, 38518e1b742SAlexis Lothoré int port); 38618e1b742SAlexis Lothoré phy_interface_t mv88e6393x_port_max_speed_mode(struct mv88e6xxx_chip *chip, 38718e1b742SAlexis Lothoré int port); 3887cbbee05SAndrew Lunn 389e28def33SVivien Didelot int mv88e6xxx_port_set_state(struct mv88e6xxx_chip *chip, int port, u8 state); 390e28def33SVivien Didelot 3915a7921f4SVivien Didelot int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip *chip, int port, u16 map); 3925a7921f4SVivien Didelot 393b4e48c50SVivien Didelot int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip *chip, int port, u16 *fid); 394b4e48c50SVivien Didelot int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip *chip, int port, u16 fid); 395b4e48c50SVivien Didelot 39677064f37SVivien Didelot int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip *chip, int port, u16 *pvid); 39777064f37SVivien Didelot int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip *chip, int port, u16 pvid); 39877064f37SVivien Didelot 39934ea415fSHans Schultz int mv88e6xxx_port_set_lock(struct mv88e6xxx_chip *chip, int port, 40034ea415fSHans Schultz bool locked); 40134ea415fSHans Schultz 402385a0995SVivien Didelot int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip *chip, int port, 403385a0995SVivien Didelot u16 mode); 404ef0a7318SAndrew Lunn int mv88e6095_port_tag_remap(struct mv88e6xxx_chip *chip, int port); 405ef0a7318SAndrew Lunn int mv88e6390_port_tag_remap(struct mv88e6xxx_chip *chip, int port); 40656995cbcSAndrew Lunn int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip *chip, int port, 40731bef4e9SVivien Didelot enum mv88e6xxx_egress_mode mode); 40856995cbcSAndrew Lunn int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 40956995cbcSAndrew Lunn enum mv88e6xxx_frame_mode mode); 41056995cbcSAndrew Lunn int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip *chip, int port, 41156995cbcSAndrew Lunn enum mv88e6xxx_frame_mode mode); 412a8b659e7SVladimir Oltean int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip *chip, 413a8b659e7SVladimir Oltean int port, bool unicast); 414a8b659e7SVladimir Oltean int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip *chip, 415a8b659e7SVladimir Oltean int port, bool multicast); 416a8b659e7SVladimir Oltean int mv88e6352_port_set_ucast_flood(struct mv88e6xxx_chip *chip, int port, 417a8b659e7SVladimir Oltean bool unicast); 418a8b659e7SVladimir Oltean int mv88e6352_port_set_mcast_flood(struct mv88e6xxx_chip *chip, int port, 419a8b659e7SVladimir Oltean bool multicast); 420f3a2cd32SVivien Didelot int mv88e6352_port_set_policy(struct mv88e6xxx_chip *chip, int port, 421f3a2cd32SVivien Didelot enum mv88e6xxx_policy_mapping mapping, 422f3a2cd32SVivien Didelot enum mv88e6xxx_policy_action action); 4236584b260SMarek Behún int mv88e6393x_port_set_policy(struct mv88e6xxx_chip *chip, int port, 4246584b260SMarek Behún enum mv88e6xxx_policy_mapping mapping, 4256584b260SMarek Behún enum mv88e6xxx_policy_action action); 42656995cbcSAndrew Lunn int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 42756995cbcSAndrew Lunn u16 etype); 428de776d0dSPavana Sharma int mv88e6393x_set_egress_port(struct mv88e6xxx_chip *chip, 429de776d0dSPavana Sharma enum mv88e6xxx_egress_direction direction, 430de776d0dSPavana Sharma int port); 431de776d0dSPavana Sharma int mv88e6393x_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 432de776d0dSPavana Sharma int upstream_port); 433de776d0dSPavana Sharma int mv88e6393x_port_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip); 434de776d0dSPavana Sharma int mv88e6393x_port_set_ether_type(struct mv88e6xxx_chip *chip, int port, 435de776d0dSPavana Sharma u16 etype); 436ea698f4fSVivien Didelot int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, 437ea698f4fSVivien Didelot bool message_port); 43857e661aaSTobias Waldekranz int mv88e6xxx_port_set_trunk(struct mv88e6xxx_chip *chip, int port, 43957e661aaSTobias Waldekranz bool trunk, u8 id); 440cd782656SVivien Didelot int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, 441cd782656SVivien Didelot size_t size); 442ef70b111SAndrew Lunn int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); 443ef70b111SAndrew Lunn int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); 444041bd545STobias Waldekranz int mv88e6xxx_port_set_assoc_vector(struct mv88e6xxx_chip *chip, int port, 445041bd545STobias Waldekranz u16 pav); 4460898432cSVivien Didelot int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 4470898432cSVivien Didelot u8 out); 4480898432cSVivien Didelot int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, 4490898432cSVivien Didelot u8 out); 4507a3007d2SMarek Behún int mv88e6341_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 4517a3007d2SMarek Behún phy_interface_t mode); 452fdc71eeaSAndrew Lunn int mv88e6390_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 453fdc71eeaSAndrew Lunn phy_interface_t mode); 454f39908d3SAndrew Lunn int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 455f39908d3SAndrew Lunn phy_interface_t mode); 456de776d0dSPavana Sharma int mv88e6393x_port_set_cmode(struct mv88e6xxx_chip *chip, int port, 457de776d0dSPavana Sharma phy_interface_t mode); 4582d2e1dd2SAndrew Lunn int mv88e6185_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 4592d2e1dd2SAndrew Lunn int mv88e6352_port_get_cmode(struct mv88e6xxx_chip *chip, int port, u8 *cmode); 4608b6836d8SVladimir Oltean int mv88e6xxx_port_drop_untagged(struct mv88e6xxx_chip *chip, int port, 4618b6836d8SVladimir Oltean bool drop_untagged); 4627af4a361STobias Waldekranz int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip *chip, int port, bool map); 463a23b2961SAndrew Lunn int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip *chip, int port, 464a23b2961SAndrew Lunn int upstream_port); 465f0942e00SIwan R Timmer int mv88e6xxx_port_set_mirror(struct mv88e6xxx_chip *chip, int port, 466f0942e00SIwan R Timmer enum mv88e6xxx_egress_direction direction, 467f0942e00SIwan R Timmer bool mirror); 468c8c94891SVivien Didelot 469c8c94891SVivien Didelot int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port); 4709dbfb4e1SVivien Didelot int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip *chip, int port); 471c8c94891SVivien Didelot 47260907013SMarek Behún int mv88e6xxx_port_hidden_write(struct mv88e6xxx_chip *chip, int block, 47360907013SMarek Behún int port, int reg, u16 val); 47460907013SMarek Behún int mv88e6xxx_port_hidden_wait(struct mv88e6xxx_chip *chip); 47560907013SMarek Behún int mv88e6xxx_port_hidden_read(struct mv88e6xxx_chip *chip, int block, int port, 47660907013SMarek Behún int reg, u16 *val); 47760907013SMarek Behún 47818abed21SVivien Didelot #endif /* _MV88E6XXX_PORT_H */ 479